From: Tarek Dakhran t.dakh...@samsung.com
EXYNOS5410 is SoC in Samsung's Exynos5 SoC series.
Add initial support for this SoC.
Signed-off-by: Tarek Dakhran t.dakh...@samsung.com
Signed-off-by: Vyacheslav Tyrtov v.tyr...@samsung.com
---
arch/arm/mach-exynos/Kconfig | 12
From: Tarek Dakhran t.dakh...@samsung.com
Add EDCS(Exynos Dual Cluster Support) for Samsung Exynos5410 SoC.
This enables all 8 cores, 4 x A7 and 4 x A15 run at the same time.
Signed-off-by: Tarek Dakhran t.dakh...@samsung.com
Signed-off-by: Vyacheslav Tyrtov v.tyr...@samsung.com
---
From: Tarek Dakhran t.dakh...@samsung.com
The EXYNOS5410 clocks are statically listed and registered
using the Samsung specific common clock helper functions.
Signed-off-by: Tarek Dakhran t.dakh...@samsung.com
Signed-off-by: Vyacheslav Tyrtov v.tyr...@samsung.com
---
The series of patches represent support of Exynos 5410 SoC
The Exynos 5410 is the first Samsung SoC based on bigLITTLE architecture
Patches allow all 8 CPU cores (4 x A7 and 4 x A15) to run at the same time
Patches add new platform description, support of clock controller,
dual cluster support
Hi Mark Brown,
On Wed, Nov 6, 2013 at 1:51 PM, Mark Brown broo...@kernel.org wrote:
On Wed, Nov 06, 2013 at 10:23:07AM +0530, Rajeshwari Birje wrote:
On Thu, Oct 31, 2013 at 6:07 PM, Tomasz Figa t.f...@samsung.com wrote:
The driver as of today's linux-next does not seem to support word
[CCing Sylwester, Andrzej and Lukasz]
On Thursday 07 of November 2013 14:52:36 Rajeshwari Birje wrote:
Hi Mark Brown,
On Wed, Nov 6, 2013 at 1:51 PM, Mark Brown broo...@kernel.org wrote:
On Wed, Nov 06, 2013 at 10:23:07AM +0530, Rajeshwari Birje wrote:
On Thu, Oct 31, 2013 at 6:07 PM,
On 11/07/2013 10:39 AM, Tomasz Figa wrote:
[CCing Sylwester, Andrzej and Lukasz]
On Thursday 07 of November 2013 14:52:36 Rajeshwari Birje wrote:
Hi Mark Brown,
On Wed, Nov 6, 2013 at 1:51 PM, Mark Brown broo...@kernel.org wrote:
On Wed, Nov 06, 2013 at 10:23:07AM +0530, Rajeshwari Birje
Hi,
On Thursday, November 07, 2013 11:22:42 AM Naveen Krishna Chatradhi wrote:
On Exynos5250, the FALL interrupt related en, status and clear bits are
available at an offset of
16 in INTEN, INTSTAT registers and at an offset of
12 in INTCLEAR register.
On Exynos5420, the FALL interrupt
Hi Bartlomiej,
On 7 November 2013 16:18, Bartlomiej Zolnierkiewicz
b.zolnier...@samsung.com wrote:
Hi,
On Thursday, November 07, 2013 11:22:42 AM Naveen Krishna Chatradhi wrote:
On Exynos5250, the FALL interrupt related en, status and clear bits are
available at an offset of
16 in INTEN,
This patch adds pmusysreg node to Exynos5 dtsi file to handle PMU
register accesses in a centralized way using syscon driver
Signed-off-by: Leela Krishna Amudala l.kris...@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
---
arch/arm/boot/dts/exynos5.dtsi |5 +
1 file changed, 5
The syscon regmap interface is used to configure AUTOMATIC_WDT_RESET_DISABLE
and MASK_WDT_RESET_REQUEST registers of PMU to mask/unmask enable/disable of
watchdog in probe and s2r scenarios.
Signed-off-by: Leela Krishna Amudala l.kris...@samsung.com
---
Adds watchdog device nodes to the DT device list for Exynos5250 and Exynos5420
Signed-off-by: Leela Krishna Amudala l.kris...@samsung.com
---
arch/arm/boot/dts/exynos5.dtsi|7 ---
arch/arm/boot/dts/exynos5250.dtsi |6 +-
arch/arm/boot/dts/exynos5420.dtsi |9 +
3
This patchset does the following things
- Adds pmusysreg device node to exynos5.dtsi file
- Adds watchdog DT nodes to Exynos5250 and 5420
- Uses syscon regmap interface to configure pmu registers
to mask/unmask enable/disable of watchdog.
This patch set
On Exynos5420 the TMU(4) for GPU has a seperate clock enable bit from
the other TMU channels(0 ~ 3). Hence, accessing TRIMINFO for base_second
should be acompanied by enabling the respective clock.
This patch which allow for a clk_sec clock to be specified in the
device-tree which will be ungated
Exynos5420 SoC has per core thermal management unit.
5 TMU channels 4 for CPUs and 5th for GPU.
This patch adds the device tree nodes to the DT device list.
Nodes carry the misplaced second base address and the second
clock to access the misplaced base address.
Signed-off-by: Leela Krishna
Exynos5420 SoC has 7 High speed I2C channels, This patch adds
the device tree nodes to the DT device list.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Signed-off-by: Andrew Bresticker abres...@chromium.org
---
arch/arm/boot/dts/exynos5420.dtsi | 98
On 7 November 2013 18:52, Naveen Krishna Chatradhi
ch.nav...@samsung.com wrote:
Exynos5420 SoC has 7 High speed I2C channels, This patch adds
the device tree nodes to the DT device list.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Signed-off-by: Andrew Bresticker
Hi Sachin,
Please see my comments inline.
On Tuesday 05 of November 2013 17:09:20 Sachin Kamat wrote:
Added high speed I2C nodes to Exynos5420 DT file.
Signed-off-by: Sachin Kamat sachin.ka...@linaro.org
---
arch/arm/boot/dts/exynos5420.dtsi | 98
+
Hi Naveen,
On Thursday 07 of November 2013 18:12:34 Naveen Krishna Chatradhi wrote:
On Exynos5420 the TMU(4) for GPU has a seperate clock enable bit from
the other TMU channels(0 ~ 3). Hence, accessing TRIMINFO for base_second
should be acompanied by enabling the respective clock.
This
Hi Naveen,
On Thursday 07 of November 2013 18:37:49 Naveen Krishna Chatradhi wrote:
Exynos5420 SoC has per core thermal management unit.
5 TMU channels 4 for CPUs and 5th for GPU.
This patch adds the device tree nodes to the DT device list.
Nodes carry the misplaced second base address
Hi Naveen,
On Thursday 07 of November 2013 11:22:42 Naveen Krishna Chatradhi wrote:
On Exynos5250, the FALL interrupt related en, status and clear bits are
available at an offset of
16 in INTEN, INTSTAT registers and at an offset of
12 in INTCLEAR register.
On Exynos5420, the FALL
Hi Naveen,
On Thursday 07 of November 2013 11:23:32 Naveen Krishna Chatradhi wrote:
This patch adds the neccessary register changes and arch information
to support Exynos5420 SoCs
Exynos5420 has 5 TMU channels one for each CPU 0, 1, 2 and 3 and GPU
Also updated the Documentation at
On 7 November 2013 19:48, Tomasz Figa t.f...@samsung.com wrote:
Hi Naveen,
On Thursday 07 of November 2013 18:12:34 Naveen Krishna Chatradhi wrote:
On Exynos5420 the TMU(4) for GPU has a seperate clock enable bit from
the other TMU channels(0 ~ 3). Hence, accessing TRIMINFO for base_second
Hi Naveen,
On Thursday 07 of November 2013 22:02:10 Naveen Krishna Ch wrote:
Hello Tomasz,
On 7 November 2013 19:53, Tomasz Figa t.f...@samsung.com wrote:
Hi Naveen,
On Thursday 07 of November 2013 18:37:49 Naveen Krishna Chatradhi wrote:
Exynos5420 SoC has per core thermal management
Hello Tomasz,
On 7 November 2013 22:15, Tomasz Figa t.f...@samsung.com wrote:
Hi Naveen,
On Thursday 07 of November 2013 22:02:10 Naveen Krishna Ch wrote:
Hello Tomasz,
On 7 November 2013 19:53, Tomasz Figa t.f...@samsung.com wrote:
Hi Naveen,
On Thursday 07 of November 2013 18:37:49
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