Hi Chanwoo,
On Tuesday 03 February 2015 05:43 AM, Chanwoo Choi wrote:
This patch adds the mux/divider/gate clocks for CMU_ATLAS domain which
generates the clocks for Cortex-A57 Quad-core processsor, L2 cache controller
and CoreSight.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz
Hi,
On 02/06/2015 02:59 AM, Gustavo Padovan wrote:
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
The primary plane default zpos is now 0, so remove checks for zpos ==
-1. We don't need to set win to 0 anymore it is already zero.
Could you also remove DEFAULT_ZPOS define? And zpos
Hi,
On 02/06/2015 02:59 AM, Gustavo Padovan wrote:
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
Usually userspace don't want to have two overlay planes on the same zpos
so this change assign a different zpos for each plane. Before this change
a zpos of value zero was created for
Hi, Vivek.
On 02/06/2015 02:52 PM, Vivek Gautam wrote:
Hi Jaehoon,
On Fri, Feb 6, 2015 at 6:48 AM, Jaehoon Chung jh80.ch...@samsung.com wrote:
Hi, Alim.
On my board, this patch isn't working fine.
So when i complete to test on my board(exynos5), i will reply with comments.
Sorry for
Hi,
On Fri, Feb 6, 2015 at 11:33 AM, Jaehoon Chung jh80.ch...@samsung.com wrote:
Hi, Vivek.
On 02/06/2015 02:52 PM, Vivek Gautam wrote:
Hi Jaehoon,
On Fri, Feb 6, 2015 at 6:48 AM, Jaehoon Chung jh80.ch...@samsung.com wrote:
Hi, Alim.
On my board, this patch isn't working fine.
So when
Hi,
On 02/05/2015 11:45 PM, Javier Martinez Canillas wrote:
Hello Andrzej,
Thanks a lot for finally finding what was causing the HDMI issue.
On 02/05/2015 01:35 PM, Andrzej Hajda wrote:
Hi,
Exynos chipsets since 542x have asynchronous bridges connecting different
IPs.
These bridges
Hi Jaehoon,
On Fri, Feb 6, 2015 at 6:48 AM, Jaehoon Chung jh80.ch...@samsung.com wrote:
Hi, Alim.
On my board, this patch isn't working fine.
So when i complete to test on my board(exynos5), i will reply with comments.
Sorry for late testing.
I tested this series on linux-next, on
Hi,
On 02/05/2015 10:06 PM, Daniel Vetter wrote:
On Thu, Feb 05, 2015 at 12:48:07PM +, Daniel Stone wrote:
Hi,
On 5 February 2015 at 12:26, Rob Clark robdcl...@gmail.com wrote:
On Thu, Feb 5, 2015 at 4:15 AM, Daniel Vetter dan...@ffwll.ch wrote:
Yeah I noticed the zpos fun when hacking
Hi Gustavo,
On 02/06/2015 02:59 AM, Gustavo Padovan wrote:
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
struct {fimd,mixer,vidi}_win_data was just keeping the same data
as struct exynos_drm_plane thus get ride of it and use exynos_drm_plane
directly.
It changes how planes are
On Thu, Feb 05, 2015 at 12:48:07PM +, Daniel Stone wrote:
Hi,
On 5 February 2015 at 12:26, Rob Clark robdcl...@gmail.com wrote:
On Thu, Feb 5, 2015 at 4:15 AM, Daniel Vetter dan...@ffwll.ch wrote:
Yeah I noticed the zpos fun when hacking around too. Exynos should
probably switch
Since Exynos5420 there are async-bridges (ASB) between different IPs. These
bridges must be operational during power domain on/off, ie. clocks used
by these bridges should be enabled.
This patch enabled these clocks during domain on/off.
Signed-off-by: Andrzej Hajda a.ha...@samsung.com
---
The patch adds bindings for clocks required by async-bridges
present in the particular power domain.
Signed-off-by: Andrzej Hajda a.ha...@samsung.com
---
Documentation/devicetree/bindings/arm/exynos/power_domain.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git
disp1 power domain requires operational async-bridge associated with HDMI,
ie its clock should be enabled during power on/off.
This patch fixes broken Odroid XU3 HDMI support.
Signed-off-by: Andrzej Hajda a.ha...@samsung.com
---
arch/arm/boot/dts/exynos5420.dtsi | 6 --
1 file changed, 4
Hi,
On 5 February 2015 at 12:26, Rob Clark robdcl...@gmail.com wrote:
On Thu, Feb 5, 2015 at 4:15 AM, Daniel Vetter dan...@ffwll.ch wrote:
Yeah I noticed the zpos fun when hacking around too. Exynos should
probably switch defaults so that overlays are visible by default. And we
need to
Hi Pankaj and Sylwester,
On Thu, Feb 5, 2015 at 6:56 PM, Sylwester Nawrocki
s.nawro...@samsung.com wrote:
On 05/02/15 08:44, Pankaj Dubey wrote:
+static struct samsung_gate_clock apollo_gate_clks[] __initdata = {
+
+ /* ENABLE_PCLK_APOLLO */
+ GATE(CLK_PCLK_ASAPBMST_CSSYS_APOLLO,
Commit: e725d26c4857e5e41975b5e74e64ce6ab09a7121 provided possibility to
use device tree to asses if cpu can be used as cooling device. Since the
code was somewhat awkward, simpler approach has been proposed.
Test HW: Exynos 4412 - Odroid U3.
Suggested-by: Viresh Kumar viresh.ku...@linaro.org
Hi Krzysztof
On 5 February 2015 at 12:53, Krzysztof Kozlowski
k.kozlow...@samsung.com wrote:
Since 32b0aa9aaeb4 (ARM: EXYNOS: Remove i2c sys configuration related
code) the Exynos 5250 no longer saves additional registers under
'exynos_pm_data.extra_save' field.
No one else uses this code
This patch is based on exynos-drm-next branch of Inki Dae's tree at:
git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos.git
DECON(Display and Enhancement Controller) is the new IP
in exynos7 SOC for generating video signals using pixel data.
DECON driver can be used to drive 2
On Thu, Feb 05, 2015 at 10:05:43AM +0900, Joonyoung Shim wrote:
Hi Daniel,
On 02/04/2015 11:16 PM, Daniel Vetter wrote:
On Wed, Feb 04, 2015 at 04:42:57PM +0900, Joonyoung Shim wrote:
Hi,
On 02/04/2015 04:14 AM, Gustavo Padovan wrote:
From: Gustavo Padovan
Hi,
On 02/05/2015 06:00 AM, SF Markus Elfring wrote:
From: Markus Elfring elfr...@users.sourceforge.net
Date: Wed, 4 Feb 2015 21:54:45 +0100
The functions phy_power_on() and vunmap() perform also input
parameter validation. Thus the test around their calls is not needed.
This issue was
Hi Chanwoo,
On Tuesday 03 February 2015 05:43 AM, Chanwoo Choi wrote:
This patch adds the mux/divider/gate clocks for CMU_MSCL domain which
generates the clocks for M2M (Memory to Memory) scaler, JPEG IPs.
Cc: Sylwester Nawrocki s.nawro...@samsung.com
Cc: Tomasz Figa tomasz.f...@gmail.com
Hello Andrzej,
Thanks a lot for finally finding what was causing the HDMI issue.
On 02/05/2015 01:35 PM, Andrzej Hajda wrote:
Hi,
Exynos chipsets since 542x have asynchronous bridges connecting different IPs.
These bridges should be operational during power domain switching, ie
associated
Hi, Alim.
On my board, this patch isn't working fine.
So when i complete to test on my board(exynos5), i will reply with comments.
Sorry for late testing.
Best Regards,
Jaehoon Chung
On 01/29/2015 11:41 AM, Alim Akhtar wrote:
This adds HS400 mode support for exynos dw_mmc host controller.
On Thu, Feb 05, 2015 at 11:37:13AM +0900, Joonyoung Shim wrote:
Hi Daniel,
On 02/04/2015 11:28 PM, Daniel Vetter wrote:
On Wed, Feb 04, 2015 at 04:44:12PM +0900, Joonyoung Shim wrote:
Hi,
On 02/04/2015 04:14 AM, Gustavo Padovan wrote:
From: Gustavo Padovan
Hi Krzysztof,
On Thursday 05 February 2015 12:53 PM, Krzysztof Kozlowski wrote:
The 'pm_data', 'exynos_release_ret_regs', 'exynos3250_release_ret_regs'
and 'exynos5420_release_ret_regs' are not exported nor used outside of
suspend.c file. Make them static.
This fixes following sparse warnings:
On 05/02/15 08:44, Pankaj Dubey wrote:
+static struct samsung_gate_clock apollo_gate_clks[] __initdata = {
+
+ /* ENABLE_PCLK_APOLLO */
+ GATE(CLK_PCLK_ASAPBMST_CSSYS_APOLLO, pclk_asapbmst_cssys_apollo,
+ div_pclk_dbg_apollo, ENABLE_PCLK_APOLLO,
+ 2,
From: Tomasz Figa t.f...@samsung.com
Add clock controller for CMU ISP clock domain on Exynos3250,
providing clocks for FIMC-IS subsystem.
[b.michalska: initial setup of ISP block source clocks
(setting root oscillator clock as the input);
use samsung_cmu_register_one to register the provider;
Hi,
Exynos chipsets since 542x have asynchronous bridges connecting different IPs.
These bridges should be operational during power domain switching, ie associated
clocks cannot be gated.
This patchset adds binding to provide such clocks per power domain and adds code
which enables them during
On Wed, Feb 4, 2015 at 11:21 AM, Marek Szyprowski
m.szyprow...@samsung.com wrote:
Hello,
On 2015-02-04 10:23, Carlo Caione wrote:
From: Jasper St. Pierre jstpie...@mecheye.net
Even without an iommu, NO_KERNEL_MAPPING is still convenient to save on
kernel address space in places where we
On Thu, Feb 5, 2015 at 4:15 AM, Daniel Vetter dan...@ffwll.ch wrote:
On Thu, Feb 05, 2015 at 11:37:13AM +0900, Joonyoung Shim wrote:
Hi Daniel,
On 02/04/2015 11:28 PM, Daniel Vetter wrote:
On Wed, Feb 04, 2015 at 04:44:12PM +0900, Joonyoung Shim wrote:
Hi,
On 02/04/2015 04:14 AM,
Hi,
On Thursday, February 05, 2015 08:12:20 AM Krzysztof Kozlowski wrote:
On śro, 2015-02-04 at 19:07 +0100, Bartlomiej Zolnierkiewicz wrote:
Hi,
On Wednesday, February 04, 2015 11:27:26 AM Krzysztof Kozlowski wrote:
The Exynos cpuidle driver has coupled cpuidle built-in so it cannot
On Thu, Feb 05, 2015 at 11:48:18AM +0900, Joonyoung Shim wrote:
Hi Daniel,
On 02/04/2015 11:30 PM, Daniel Vetter wrote:
On Wed, Feb 04, 2015 at 04:49:25PM +0900, Joonyoung Shim wrote:
Hi,
On 02/04/2015 04:14 AM, Gustavo Padovan wrote:
From: Gustavo Padovan
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
struct {fimd,mixer,vidi}_win_data was just keeping the same data
as struct exynos_drm_plane thus get ride of it and use exynos_drm_plane
directly.
It changes how planes are created and remove .win_mode_set() callback
that was only filling all
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
Usually userspace don't want to have two overlay planes on the same zpos
so this change assign a different zpos for each plane. Before this change
a zpos of value zero was created for all planes so the userspace had to
set up the zpos of every
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
Define the function args as 'win' to avoid the assignment later in the
functions.
Signed-off-by: Gustavo Padovan gustavo.pado...@collabora.co.uk
---
drivers/gpu/drm/exynos/exynos_drm_fimd.c | 6 ++
From: Gustavo Padovan gustavo.pado...@collabora.co.uk
The primary plane default zpos is now 0, so remove checks for zpos ==
-1. We don't need to set win to 0 anymore it is already zero.
Signed-off-by: Gustavo Padovan gustavo.pado...@collabora.co.uk
---
drivers/gpu/drm/exynos/exynos_drm_fimd.c |
On Tue, Feb 03, 2015 at 03:06:22PM +0100, Sylwester Nawrocki wrote:
I2S1, I2S2 on Exynos4 SoC series have limited functionality compared
to I2S0, samsung,s3c6410-i2s compatible should be used for them.
I've applied this even though I really shouldn't in order to get it in.
Since it's a bug fix
Hi Mike,
This pull request includes driver for clock controller of the Exynos
5433 SoC. As the hardware is quite complex, with many peripherals and
corresponding clock management units the driver is rather huge. I guess
it will require a bit more cleanups than last time to balance lines
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