2 : IE U
BTA: 0x2fc4SP: 0x5ff8bd64 FP: 0x
LPS: 0x200524a0 LPE: 0x200524b6 LPC: 0x0006
[-other-info-]
_
This patch fix
STAR 9001146055: waitpid02: Invalid Write @ 0x by insn @ 0x000123ec
Signed-off-by: Eugeniy Paltsev
shown.
Changes v1->v2 (Thanks to Vineet and Christoph):
* Panic if both IOC and HIGHMEM_ZONE are enabled.
* Move arch_setup_dma_ops to arch/arc/mm/dma.c
* Tweak the boot printing about IOC
* Print info about cache ops used for each device.
* Refactor arch_setup_dma_ops
Signed-off-by: E
Hi Vineet, Christoph,
thanks for responding.
On Mon, 2018-06-18 at 15:53 -0700, Vineet Gupta wrote:
> On 06/15/2018 05:58 AM, Eugeniy Paltsev wrote:
> > The ARC HS processor provides an IOC port (I/O coherency bus
> > interface) that allows external devices such as DMA device
ecial cache ops like "arc_ioc_ops" which will handle
ZONE_HIGHMEM case.
(BTW: current ARC dma_noncoherent_ops implementation also has same
problem if IOC and HIGHMEM are enabled.)
NOTE 2:
In this RFC only hsdk.dts changes are shown to reduce patch size.
AXS103 device tree changes are
On Mon, 2018-04-23 at 08:47 +0200, Ulf Hansson wrote:
> On 20 April 2018 at 17:53, Eugeniy Paltsev
> wrote:
> > Hi Ulf,
> >
> > On Fri, 2018-04-20 at 09:35 +0200, Ulf Hansson wrote:
> > > [...]
> > >
> > > >
> > > > 2. Ad
thead <===
rsi_91x: rsi_core_qos_processor: Queue number = 1
rsi_91x: rsi_sdio_check_buffer_status: Failed to read status register
----->8----
Any ideas what could be wrong?
--
Eugeniy Paltsev
___
l
s are used...
This patch at least shouldn't break anything for current users (which use
it in single slot mode)
Moreover we tested this dual-slot implementation and don't catch any problems
(probably yet) except bus performance decrease in dual-slot mode (which is
quite expected).
>
This came to light in some internal discussions and it is nice to have
this documented rather than digging up the PRM (Prog Ref Manual) again.
Acked-by: Vineet Gupta
Signed-off-by: Eugeniy Paltsev
---
Changes v1->v2:
* Minor comment fix.
drivers/clocksource/arc_timer.c |
This came to light in some internal discussions and it is nice to have
this documented rather than digging up the PRM (Prog Ref Manual) again.
Signed-off-by: Eugeniy Paltsev
---
drivers/clocksource/arc_timer.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers
board too to catch any regressions.
Signed-off-by: Eugeniy Paltsev
---
drivers/mmc/host/dw_mmc.c | 325 ++
drivers/mmc/host/dw_mmc.h | 14 +-
2 files changed, 253 insertions(+), 86 deletions(-)
diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host
Revert "mmc: dw_mmc: remove the deprecated "num-slots""
Revert "mmc: dw_mmc: fix the wrong condition check of getting num-slots from DT"
Revert "mmc: dw_mmc: remove the unnecessary slot variable"
Revert "mmc: dw_mmc: update kernel-doc comments for dw_mci"
Revert "mmc: dw_mmc: use the 'slot' instead
ay I tested this changes (in singleslot and multislot
modes) only on Synopsys HSDK board. But I will get ODROID-XU4 board
(with Exynos5422 which has DW MMC controller) the next week
so I will test it on this board too to catch any regressions.
Eugeniy Paltsev (2):
dw_mmc: revert re
t this?
All comments and suggestions are more than welcome.
--
Eugeniy Paltsev
___
linux-snps-arc mailing list
linux-snps-arc@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-snps-arc
etical order.
Eugeniy Paltsev (2):
dmaengine: Introduce DW AXI DMAC driver
dt-bindings: Document the Synopsys DW AXI DMA bindings
.../devicetree/bindings/dma/snps,dw-axi-dmac.txt | 41 +
MAINTAINERS|6 +
drivers/dma/K
This patch adds documentation of device tree bindings for the Synopsys
DesignWare AXI DMA controller.
Signed-off-by: Eugeniy Paltsev
---
Changes v2->v3:
* None.
.../devicetree/bindings/dma/snps,dw-axi-dmac.txt | 41 ++
1 file changed, 41 insertions(+)
create mode 100
This patch adds support for the DW AXI DMAC controller.
DW AXI DMAC is a part of HSDK development board from Synopsys.
In this driver implementation only DMA_MEMCPY transfers are
supported.
Signed-off-by: Eugeniy Paltsev
---
Changes v2->v3 (suggested by Andy Shevchenko and Vinod Koul):
*
On Mon, 2018-02-26 at 18:42 +0200, Andy Shevchenko wrote:
> On Mon, Feb 26, 2018 at 4:56 PM, Eugeniy Paltsev
> wrote:
>
> > + chip->core_clk = devm_clk_get(chip->dev, "core-clk");
>
> Does the name come from datasheet?
>
> > + chip
On Mon, 2018-02-26 at 18:42 +0200, Andy Shevchenko wrote:
> On Mon, Feb 26, 2018 at 4:56 PM, Eugeniy Paltsev
> wrote:
> > +static int parse_device_properties(struct axi_dma_chip *chip)
> > +{
> > + ret = device_property_read_u32(dev, "snps,dma-masters&qu
This patch adds documentation of device tree bindings for the Synopsys
DesignWare AXI DMA controller.
Signed-off-by: Eugeniy Paltsev
---
.../devicetree/bindings/dma/snps,dw-axi-dmac.txt | 41 ++
1 file changed, 41 insertions(+)
create mode 100644 Documentation/devicetree
This patch adds support for the DW AXI DMAC controller.
DW AXI DMAC is a part of HSDK development board from Synopsys.
In this driver implementation only DMA_MEMCPY transfers are
supported.
Signed-off-by: Eugeniy Paltsev
---
MAINTAINERS|6 +
drivers/dma
tor axi_chan_get_xfer_width function.
* Fix timeout calculation in dma_chan_pause.
* Add record to MAINTAINERS in correct alphabetical order.
Eugeniy Paltsev (2):
dmaengine: Introduce DW AXI DMAC driver
dt-bindings: Document the Synopsys DW AXI DMA bindings
.../devicetree/bindings/dma/snps,dw-
rated from "possible_cpus" as we
want it set correctly even if we run kernel on HW which has fewer cores
than expected (or we launch kernel via debugger and kick fever cores
than HW has)
Signed-off-by: Alexey Brodkin
Signed-off-by: Eugeniy Paltsev
---
Changes v1->v2:
* wrap access to __mcip_
As we have option in u-boot to set CPU mask for running linux,
we want to pass information to kernel about CPU cores should
be brought up. So we patch kernel dtb in u-boot to set
possible-cpus property.
This also allows us to have correctly setuped MCIP debug mask.
Signed-off-by: Eugeniy Paltsev
As of today we use hardcoded MCIP debug mask, so if we launch
kernel via debugger and kick fever cores than HW has all cpus
hang at the momemt of setup MCIP debug mask.
So update MCIP debug mask when the new cpu came online, instead of
use hardcoded MCIP debug mask.
Signed-off-by: Eugeniy
_spin_lock_irqsave(&mcip_lock);
__mcip_cmd(cmd, 0);
ret = read_aux_reg(ARC_REG_MCIP_READBACK);
raw_spin_unlock_irqrestore(&mcip_lock);
return ret;
}
--->8
--
Eugeniy Paltsev
___
linux-snps-arc maili
be called concurrently by multiple cpus and mcip doesn't
> guarantee any internal serialization/buffering. Granted, current use
case is fine
> as mcip_setup_per_cpu --> plat_smp_ops.init_per_cpu is serialized by master
> core,
> we could run into issue when say
.
Starting from ARC HS v3.0 it's possible to tie GFRC to state of up-to 4
ARC cores with help of GFRC's CORE register where we set a mask for
cores which state we need to rely on.
Signed-off-by: Eugeniy Paltsev
Signed-off-by: Alexey Brodkin
---
NOTE: with this patch previous patch is no
Setup MCIP debug mask according cpu possible mask instead of
use hardcoded one.
Signed-off-by: Eugeniy Paltsev
---
arch/arc/kernel/mcip.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/arch/arc/kernel/mcip.c b/arch/arc/kernel/mcip.c
index e87a4ea..da73258
As we have option in u-boot to set CPU mask for running linux,
we want to pass information to kernel about CPU cores should
be brought up. So we patch kernel dtb in u-boot to set
possible-cpus property.
This also allows us to have correctly setuped MCIP debug mask.
Signed-off-by: Eugeniy Paltsev
This patch adds documentation of device tree bindings for the Synopsys
DesignWare AXI DMA controller.
Signed-off-by: Eugeniy Paltsev
---
.../devicetree/bindings/dma/snps,dw-axi-dmac.txt | 41 ++
1 file changed, 41 insertions(+)
create mode 100644 Documentation/devicetree
This patch adds support for the DW AXI DMAC controller.
DW AXI DMAC is a part of HSDK development board from Synopsys.
In this driver implementation only DMA_MEMCPY transfers are
supported.
Signed-off-by: Eugeniy Paltsev
---
MAINTAINERS|6 +
drivers/dma
This patch series add support for the DW AXI DMAC controller.
DW AXI DMAC is a part of HSDK development board from Synopsys.
In this driver implementation only DMA_MEMCPY transfers
are supported.
Eugeniy Paltsev (2):
dmaengine: Introduce DW AXI DMAC driver
dt-bindings: Document the Synopsys
As for today slc_entire_op with OP_FLUSH command flush and invalidate
SLC entry instead of flush only. Fix that.
NOTE:
As for today we use slc_entire_op only with OP_FLUSH_N_INV command,
so it is kinda preventiv fix.
Signed-off-by: Eugeniy Paltsev
---
V1 patch is for u-boot (with u-boot AUX
As for today slc_entire_op with OP_FLUSH command flush and invalidate
SLC entry instead of flush only. Fix that.
NOTE:
As for today we use slc_entire_op only with OP_FLUSH_N_INV command,
so it is kinda preventiv fix.
Signed-off-by: Eugeniy Paltsev
---
arch/arc/mm/cache.c | 5 -
1 file
:
"okay" - The CPU is running; "disabled" - The CPU is in a
quiescent state."
Also we setup MCIP debug mask according cpu possible mask.
Signed-off-by: Eugeniy Paltsev
---
arch/arc/kernel/mcip.c | 10 --
arch/arc/kernel/smp.c | 30 +++
Refactor the quad core DT quirk code:
get rid of waste division and multiplication by 100 constant.
Signed-off-by: Eugeniy Paltsev
---
arch/arc/plat-axs10x/axs10x.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/arch/arc/plat-axs10x/axs10x.c b/arch/arc/plat
Set initial core pll output frequency specified in device tree to
100MHz for SMP configuration and 90MHz for UP configuration.
It will be applied at the core pll driver probing.
Update platform quirk for decreasing core frequency for quad core
configuration.
Signed-off-by: Eugeniy Paltsev
Get rid of core pll frequency set in platform code as we set it via
device tree using 'assigned-clock-rates' property.
Signed-off-by: Eugeniy Paltsev
---
arch/arc/plat-hsdk/platform.c | 42 --
1 file changed, 42 deletions(-)
diff --git a/arc
Set initial core pll output frequency on HSDK and AXS103 via
"assigned-clock-rates" property in device tree.
It will be applied at the core pll driver probing.
Eugeniy Paltsev (4):
ARC: [plat-hsdk]: Set initial core pll output frequency
ARC: [plat-hsdk]: Get rid of core pll freque
Set initial core pll output frequency specified in device tree to
1GHz. It will be applied at the core pll driver probing.
Signed-off-by: Eugeniy Paltsev
---
arch/arc/boot/dts/hsdk.dts | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arc/boot/dts/hsdk.dts b/arch/arc/boot/dts
On Tue, 2017-11-14 at 15:46 -0800, sb...@codeaurora.org wrote:
> On 11/14, Alexey Brodkin wrote:
> > Hi Vladimir,
> >
> > On Tue, 2017-11-14 at 19:01 +0200, Vladimir Zapolskiy wrote:
> > > On 11/14/2017 02:20 PM, Eugeniy Paltsev wrote:
> > > >
> >
Get rid of core pll frequency set in platform code as we set it via
device tree using 'assigned-clock-rates' property.
Signed-off-by: Eugeniy Paltsev
---
arch/arc/plat-hsdk/platform.c | 42 --
1 file changed, 42 deletions(-)
diff --git a/arc
Set initial core pll output frequency specified in device tree to
100MHz for SMP configuration and 90MHz for UP configuration.
It will be applied at the core pll driver probing.
Update platform quirk for decreasing core frequency for quad core
configuration.
Signed-off-by: Eugeniy Paltsev
Refactor the quad core DT quirk code:
get rid of waste division and multiplication by 100 constant.
Signed-off-by: Eugeniy Paltsev
---
arch/arc/plat-axs10x/axs10x.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/arch/arc/plat-axs10x/axs10x.c b/arch/arc/plat
Set initial core pll output frequency on HSDK and AXS103 via
"assigned-clock-rates" property in device tree.
It will be applied at the core pll driver probing.
Eugeniy Paltsev (4):
ARC: [plat-hsdk]: Set initial core pll output frequency
ARC: [plat-hsdk]: Get rid of core pll freque
Set initial core pll output frequency specified in device tree to
1GHz. It will be applied at the core pll driver probing.
Signed-off-by: Eugeniy Paltsev
---
arch/arc/boot/dts/hsdk.dts | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arc/boot/dts/hsdk.dts b/arch/arc/boot/dts
DW ethernet controller on axs10x hangs sometimes after SW reset, so
add reset node to make possible to reset DW ethernet controller HW.
Signed-off-by: Eugeniy Paltsev
---
arch/arc/boot/dts/axs10x_mb.dtsi | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arc/boot/dts
Use reset controller driver instead of platform quirk for AXS10x boards
to reset DW ethernet controller HW.
Eugeniy Paltsev (2):
ARC: [plat-axs10x]: DTS: Add reset controller node to manage ethernet
reset
ARC: [plat-axs10x]: Remove platform quirk to reset ethernet IP
arch/arc/boot/dts
Remove platform quirk to reset ethernet IP as AXS10x reset driver
(reset-axs10x.c) was applied.
Signed-off-by: Eugeniy Paltsev
---
arch/arc/plat-axs10x/axs10x.c | 7 ---
1 file changed, 7 deletions(-)
diff --git a/arch/arc/plat-axs10x/axs10x.c b/arch/arc/plat-axs10x/axs10x.c
index cf14ebc
s.infradead.org/msg02689.html
Signed-off-by: Eugeniy Paltsev
---
.../bindings/clock/snps,hsdk-pll-clock.txt | 5
.../devicetree/bindings/clock/snps,pll-clock.txt | 5
drivers/clk/axs10x/pll_clock.c | 34 --
drivers/clk
Hi Stephen, Michael,
Please treat this message as a polite reminder to review my patch.
It would be really nice to see this patch in 4.15.
Thanks.
On Fri, 2017-09-29 at 16:13 +0300, Eugeniy Paltsev wrote:
> Add option to set initial output frequency of plls via
> "clock-frequency&q
visor (div-by-2) in HSDK platform
code.
Reported-by: Vineet Gupta
Tested-by: Vineet Gupta
Signed-off-by: Eugeniy Paltsev
---
arch/arc/boot/dts/hsdk.dts| 11 ++-
arch/arc/plat-hsdk/platform.c | 10 ++
2 files changed, 16 insertions(+), 5 deletions(-)
diff --git a/arch/arc/boo
Increase SDIO CIU frequency from 1250Hz to 5000Hz by
switching from the default divisor value (div-by-8) to the
minimum possible value of the divisor (div-by-2) in HSDK platform
code.
Signed-off-by: Eugeniy Paltsev
---
NOTE: This patch can possibly fix last issue with SD card
On Thu, 2017-10-05 at 06:04 -0700, Vineet Gupta wrote:
> Hi Eugeniy,
>
> On 09/22/2017 09:49 AM, Eugeniy Paltsev wrote:
> > DW ethernet controller on HSDK hangs sometimes after SW reset, so
> > add reset node to make possible to reset DW ethernet controller HW.
> >
On Fri, 2017-09-29 at 11:34 -0700, Vineet Gupta wrote:
> On 09/28/2017 07:33 AM, Eugeniy Paltsev wrote:
> > Add temporary fix to HSDK platform code to setup CPU frequency
> > to 1GHz on early boot.
> > We can remove this fix when smart hsdk pll driver will be
> >
s.infradead.org/msg02689.html
Signed-off-by: Eugeniy Paltsev
---
.../bindings/clock/snps,hsdk-pll-clock.txt | 5
.../devicetree/bindings/clock/snps,pll-clock.txt | 5
drivers/clk/axs10x/pll_clock.c | 34 --
drivers/clk
Add temporary fix to HSDK platform code to setup CPU frequency
to 1GHz on early boot.
We can remove this fix when smart hsdk pll driver will be
introduced, see discussion:
https://www.mail-archive.com/linux-snps-arc@lists.infradead.org/msg02689.html
Signed-off-by: Eugeniy Paltsev
---
arch/arc
On Wed, 2017-09-27 at 10:40 -0700, Vineet Gupta wrote:
> On 09/22/2017 09:49 AM, Eugeniy Paltsev wrote:
> > DW ethernet controller on HSDK hangs sometimes after SW reset, so
> > add reset node to make possible to reset DW ethernet controller HW.
> >
> > Sig
DW ethernet controller on HSDK hangs sometimes after SW reset, so
add reset node to make possible to reset DW ethernet controller HW.
Signed-off-by: Eugeniy Paltsev
---
Changes v2 -> v3:
* Remove v1 suffix as we finaly got rid of v1 suffix in reset
driver and docs.
* Rename reset node
line after reset.
As of today only the following lines are used:
- DW GMAC - line 5
Signed-off-by: Eugeniy Paltsev
---
Changes v1 -> v2:
* The creg reset register is self-clearing so we don't need to clear it
manually. Fixed it.
* Use reset callback instead of assert/
On Tue, 2017-09-12 at 11:38 -0700, Vineet Gupta wrote:
> On 09/12/2017 11:20 AM, Eugeniy Paltsev wrote:
> > DW sdio controller has external ciu clock divider controlled
> > via register in SDIO IP. It divides sdio_ref_clk
> > (which comes from CGU) by 16 for default. So def
: Eugeniy Paltsev
---
arch/arc/boot/dts/axs10x_mb.dtsi | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/arch/arc/boot/dts/axs10x_mb.dtsi b/arch/arc/boot/dts/axs10x_mb.dtsi
index 0ff7e07..7bdf581 100644
--- a/arch/arc/boot/dts/axs10x_mb.dtsi
+++ b/arch/arc/boot/dts
1
to 1250 Hz until we fix dw sdio driver itself.
Signed-off-by: Eugeniy Paltsev
---
arch/arc/boot/dts/hsdk.dts | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/arch/arc/boot/dts/hsdk.dts b/arch/arc/boot/dts/hsdk.dts
index 8412669..b922f3f 100644
--- a/arch/arc
On Wed, 2017-09-06 at 12:54 -0700, Vineet Gupta wrote:
> On 09/06/2017 11:21 AM, Eugeniy Paltsev wrote:
> > DW ethernet controller on AXS10x hangs sometimes after SW reset, so
> > add temporary quirk to reset DW ethernet controller IP core.
> > This quirk can be removed afte
/9903375/)
will be available in upstream.
Signed-off-by: Eugeniy Paltsev
---
arch/arc/plat-axs10x/axs10x.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arc/plat-axs10x/axs10x.c b/arch/arc/plat-axs10x/axs10x.c
index f1ac679..cf14ebc 100644
--- a/arch/arc/plat-axs10x/axs10x.c
+++ b/arch
Hi Petr,
On Tue, 2017-09-05 at 16:54 +0200, Petr Mladek wrote:
> On Mon 2017-08-28 19:58:07, Eugeniy Paltsev wrote:
> > In the current implementation we take the first console that
> > registers if we didn't select one.
> >
> > But if we specify console via "
Add core pll node (core_clk) to manage cpu frequency.
core_clk node represents pll itself.
input_clk node represents clock signal source (basically xtal)
which comes to pll input.
Signed-off-by: Eugeniy Paltsev
---
arch/arc/boot/dts/hsdk.dts | 11 +--
arch/arc/configs
Hi,
Maybe you have any comments or remarks about this patch?
And if you don't could you please apply it.
Thanks.
On Mon, 2017-08-21 at 19:22 +0300, Eugeniy Paltsev wrote:
> For now baud field of earlycon structure device is't initialised at all
> in of_setup_earlycon
Hi Philipp,
Do you have plans to add reset-simple driver into 4.14?
It would be nice to use it for AXS10x in 4.14.
Thanks.
On Mon, 2017-08-14 at 13:37 +, Eugeniy Paltsev wrote:
> On Fri, 2017-08-11 at 15:46 +0200, Philipp Zabel wrote:
> > Hi Eugeniy,
> >
> > On Thu
Don't select first registered console if one is specified by the device tree
via the stdout-path (or linux,stdout-path) chosen node properties.
Eugeniy Paltsev (2):
OF: move extern declarations of of_stdout inside ifdef
console: don't select first registered console if stdout
Move extern declarations of "of_stdout" pointer inside "CONFIG_OF"
ifdef to be able to get rid of "CONFIG_OF" ifdef in its usage places.
Acked-by: Rob Herring
Suggested-by: Steven Rostedt
Signed-off-by: Eugeniy Paltsev
---
include/linux/of.h | 4 +++-
1 fi
" used)
as a special case:
tty0 will be registered even if it was specified neither
in "bootargs" nor in "stdout-path".
We had to retain this behavior because a lot of ARM boards (and some
powerpc) rely on it.
Signed-off-by: Eugeniy Paltsev
---
Changes v1->v2:
* Add
On Sat, 2017-08-26 at 02:44 +0900, Sergey Senozhatsky wrote:
> On (08/25/17 16:14), Eugeniy Paltsev wrote:
> > In the current implementation we take the first console that
> > registers if we didn't select one.
> >
> > But if we specify console via "stdout
plls (arc cpus pll and others),
so we had to use two different init types: CLK_OF_DECLARE for arc cpus pll
and regular probing for others plls.
Signed-off-by: Eugeniy Paltsev
---
Changes v3 -> v4:
* Rename HSDKv1 to HSDK
Changes v2 -> v3:
* Add special management of arc core interface d
Move extern declarations of "of_stdout" pointer inside "CONFIG_OF"
ifdef to be able to get rid of "CONFIG_OF" ifdef in its usage places.
Suggested-by: Steven Rostedt
Signed-off-by: Eugeniy Paltsev
---
For example see: https://lkml.org/lkml/2017/8/25/337
Changes v
On Tue, 2017-08-22 at 14:44 -0700, Vineet Gupta wrote:
> On 07/12/2017 02:40 AM, Eugeniy Paltsev wrote:
> > Most of the time we indeed use the one and only LINUX_LINK_BASE
> > set to 0x8000_. But there might be good reasons to move
> > the kernel to another location like
On Fri, 2017-08-25 at 11:12 -0400, Steven Rostedt wrote:
> On Fri, 25 Aug 2017 18:00:26 +0300
> Eugeniy Paltsev wrote:
>
> > Move extern declarations of "of_root", "of_chosen", "of_aliases",
> > "of_stdout" pointers inside "CONFIG
Move extern declarations of "of_root", "of_chosen", "of_aliases",
"of_stdout" pointers inside "CONFIG_OF" ifdef to be able to get rid
of "CONFIG_OF" ifdef in their usage places.
Suggested-by: Steven Rostedt
Signed-off-by: Eugeniy Palts
mple if some console
is registered earlier than console is pointed in "stdout-path"
property because console pointed in "stdout-path" property can be add as
preferred quite late - when it's driver is probed.
Signed-off-by: Eugeniy Paltsev
---
kernel/printk/printk.c |
On Tue, 2017-08-22 at 13:45 -0700, Vineet Gupta wrote:
> On 08/14/2017 09:12 AM, Eugeniy Paltsev wrote:
> > Add core pll node (core_clk) to manage cpu frequency.
> > core_clk represents pll itself.
> > input_clk represents clock signal source (basically xtal) which
&
On Tue, 2017-08-22 at 14:40 -0700, Vineet Gupta wrote:
> On 08/14/2017 09:12 AM, Eugeniy Paltsev wrote:
> > Set cpu frequency explicitly via "cpu-freq" param in cpu 0 node
> > in device tree.
> >
> > We add "cpu-freq" only to cpu 0 as all cpus are c
e if I specify uart device via "console" parameter in
bootargs:
-->8
chosen {
bootargs = "console=ttyS1"
stdout-path = &serial1;
};
serial0: uart0@... {}
serial1: uart1@... {} /* serial1 is used as console (ttyS1)
several plls (arc cpus pll and others),
so we had to use two different init types: CLK_OF_DECLARE for arc cpus pll
and regular probing for others plls.
Signed-off-by: Eugeniy Paltsev
---
Changes v2 -> v3:
* Add special management of arc core interface divider.
Changes v1 -> v2:
* Remove all
So initialise baud field of earlycon device structure by value of
"current-speed" property from device tree or from options
(if they exist) when we use of_setup_earlycon
Signed-off-by: Eugeniy Paltsev
---
Changes v2 -> v3:
* Use simple_strtoul instead of kstrtoul as with kstrtoul we ca
So initialise baud field of earlycon device structure by value of
"current-speed" property from device tree or from options
(if they exist) when we use of_setup_earlycon
Signed-off-by: Eugeniy Paltsev
---
Changes v1 -> v2:
* Use standart property name "current-speed" instead of c
On Thu, 2017-08-17 at 11:11 +, Eugeniy Paltsev wrote:
> Hi Alexandru,
>
> On Wed, 2017-08-16 at 15:15 -0700, Alexandru Gagniuc wrote:
> > This is split into the SOC bindings, and the board dts. The Endor
> > board is currently an FPGA emulation. Once real, silicon arrive
RC700 CPU */
> +#include "skeleton.dtsi"
Perhaps it is better not to use skeleton.dtsi as we are planning to
get rid of it.
--
Eugeniy Paltsev
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On Wed, 2017-08-16 at 08:46 -0500, Rob Herring wrote:
> On Wed, Aug 16, 2017 at 6:52 AM, Eugeniy Paltsev
> wrote:
> > Hi Rob,
> >
> > On Tue, 2017-08-15 at 14:26 -0500, Rob Herring wrote:
> > > On Tue, Aug 15, 2017 at 12:21 PM, Eugeniy Paltsev
> > >
Hi Rob,
On Tue, 2017-08-15 at 14:26 -0500, Rob Herring wrote:
> On Tue, Aug 15, 2017 at 12:21 PM, Eugeniy Paltsev
> wrote:
> > [snip]
> > @@ -282,7 +283,15 @@ int __init of_setup_earlycon(const struct
> > earlycon_id *match,
> > }
>
; and "ARC: Set IO-coherency aperture base to
LINUX_LINK_BASE") are prerequisites for HDSK support as its hardware
configuration differs quite a bit from what we used to have on other
ARC boards.
Alexey Brodkin (1):
ARC: hsdk: initial port for HSDK board
Eugeniy Paltsev (2):
ARC: Set I
DMA clients does not work due to an RTL bug,
so CREG_PAE register must be programmed to all zeroes, otherwise it will
cause problems with DMA to/from peripherals even if PAE40 is not used.
Acked-by: Rob Herring
Signed-off-by: Alexey Brodkin
Signed-off-by: Eugeniy Paltsev
---
Changes v8 ->
uired asserts:
checking IOC aperture base address and size to be supported by IOC.
Signed-off-by: Eugeniy Paltsev
---
arch/arc/mm/cache.c | 33 -
1 file changed, 24 insertions(+), 9 deletions(-)
diff --git a/arch/arc/mm/cache.c b/arch/arc/mm/cache.c
index a867575..38
ode.
This patch only makes possible to set kernel memory address not equal to
kernel link address.
Signed-off-by: Eugeniy Paltsev
---
arch/arc/Kconfig| 5 +
arch/arc/include/asm/page.h | 2 +-
arch/arc/mm/cache.c | 2 +-
arch/arc/mm/init.c | 6 +++---
4 files ch
I'll add this to
[PATCH 3/3 v9] ARC: hsdk: initial port for HSDK board
On Tue, 2017-08-15 at 20:12 +0300, Alexey Brodkin wrote:
> This is required for user-space apps to work with keyboard/mice.
>
> Signed-off-by: Alexey Brodkin
> Cc: Eugeniy Paltsev
> ---
> arch/arc
So initialise baud field of earlycon device structure by baud value
from device tree or from options (if they exist) when we use
of_setup_earlycon
Signed-off-by: Eugeniy Paltsev
---
drivers/tty/serial/earlycon.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/tty/serial/ea
several plls (arc cpus pll and others),
so we had to use two different init types: CLK_OF_DECLARE for arc cpus pll
and regular probing for others plls.
Signed-off-by: Eugeniy Paltsev
---
Changes v1 -> v2:
* Remove all MODULE* defines as this driver can't be build as module.
* Si
* Set and print cpu frequency at boot time generic way.
* Get rid of platform specific cpu clock configuration for AXS103 in
arch/arc/plat-axs10x/axs10x.c
* Add core pll node to AXS103 device tree to manage cpu frequency
* Refactor clock managment in arch/arc/plat-axs10x/axs10x.c
Eugeniy Paltsev
Use cpu's node "cpu-freq" param instead of platform-specific
"/cpu_card/core_clk" as it works only if we use fixed-clock for cpu
clocking.
Signed-off-by: Eugeniy Paltsev
---
arch/arc/plat-axs10x/axs10x.c | 12
1 file changed, 4 insertions(+), 8 deletions(
Set cpu frequency explicitly via "cpu-freq" param in cpu 0 node
in device tree.
We add "cpu-freq" only to cpu 0 as all cpus are clocking from same
clock source (same pll in our case).
We override cpus node in skeleton as we don't need this change for
nsim.
Signe
Add core pll node (core_clk) to manage cpu frequency.
core_clk represents pll itself.
input_clk represents clock signal source (basically xtal) which
comes to pll input.
Signed-off-by: Eugeniy Paltsev
---
arch/arc/boot/dts/axc003.dtsi | 11 +--
arch/arc/boot/dts/axc003_idu.dtsi | 11
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