ARC cores on reset have all interrupt lines of built-in INTC enabled.
Which means once we globally enable interrupts (very early on boot)
faulty hardware blocks may trigger an interrupt that Linux kernel
cannot handle yet as corresponding handler is not yet installed.
In that case system falls in
ARC AXS10x boards support custom IP-block which allows to control
reset signals of selected peripherals. For example DW GMAC, etc...
This block is controlled via memory-mapped register (AKA CREG) which
represents up-to 32 reset lines.
As of today only the following lines are used:
- DW GMAC - lin
On 08/10/2017 08:07 AM, Alexey Brodkin wrote:
ARC cores on reset have all interrupt lines of built-in INTC enabled.
Which means once we globally enable interrupts (very early on boot)
faulty hardware blocks may trigger an interrupt that Linux kernel
cannot handle yet as corresponding handler is n
Hi,
Looking under arch/arc, I see the current way is to add a plat-[socname]
for each new SoC. However, it seems that plat-sim, and plat-tb10x are
just place-holders for the compatible bindings.
I was going to do the same for plat-anarion, which required an early
boot workaround. However, wi
Hi Alexandru,
On 08/11/2017 12:58 AM, Alexandru Gagniuc wrote:
Hi,
Looking under arch/arc, I see the current way is to add a plat-[socname] for each
new SoC. However, it seems that plat-sim, and plat-tb10x are just place-holders
for the compatible bindings.
I was going to do the same for pl
