On 11.09.2019 02:48, Linus Walleij wrote:
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>
> On Tue, Sep 10, 2019 at 2:50 PM Claudiu Beznea
> wrote:
>> From: Alexandre Belloni
>>
>> The driver currently uses aliases to know whether the timer is the
>> clocksource or the clockevent.
>
> OK maybe that wasn't the most e
On 11.09.2019 03:03, Linus Walleij wrote:
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> On Tue, Sep 10, 2019 at 4:11 PM Alexandre Belloni
> wrote:
>> On 10/09/2019 16:08:26+0100, Sudeep Holla wrote:
>>> On Tue, Sep 10, 2019 at 02:51:50PM +, claudiu.bez...@microchip.com
>>> wrote:
>
>>> In that case, why can'
Hi,
On 10/09/2019 15:47, Claudiu Beznea wrote:
> From: Alexandre Belloni
>
> Some timer drivers may behave either as clocksource or clockevent
> or both. Until now, in case of platforms with multiple hardware
> resources of the same type, the drivers were chosing the first
> registered hardware
On 11/09/2019 09:34:27+0200, Neil Armstrong wrote:
> Hi,
>
> On 10/09/2019 15:47, Claudiu Beznea wrote:
> > From: Alexandre Belloni
> >
> > Some timer drivers may behave either as clocksource or clockevent
> > or both. Until now, in case of platforms with multiple hardware
> > resources of the s
On Tue, Sep 10, 2019 at 11:52 PM wrote:
> On 10.09.2019 19:05, John Stultz wrote:
> > External E-Mail
> > On Tue, Sep 10, 2019 at 6:47 AM Claudiu Beznea
> > wrote:
> >>
> >> This series adds support to permit the selection of clocksource/clockevent
> >> via DT.
> >
> > Sorry about this, but could
This series adds a test validation for architecture exported page table
helpers. Patch in the series adds basic transformation tests at various
levels of the page table. Before that it exports gigantic page allocation
function from HugeTLB.
This test was originally suggested by Catalin during arm6
This adds a test module which will validate architecture page table helpers
and accessors regarding compliance with generic MM semantics expectations.
This will help various architectures in validating changes to the existing
page table helpers or addition of new ones.
Test page table and memory p
