Hi Ondrej,
On Tue, 4 Jun 2019 at 18:21, Ondřej Jirman wrote:
>
> Hi Clément,
>
> On Tue, Jun 04, 2019 at 06:14:15PM +0200, Clément Péron wrote:
> > Hi Ondrej,
> >
> > On Tue, 4 Jun 2019 at 17:40, megous via linux-sunxi
> > wrote:
> > >
> > > From: Ondrej Jirman
> > >
> > > The current code
Allwiner A31 has a different memory mapping so add the compatible
we will need it later.
Signed-off-by: Clément Péron
Acked-by: Sean Young
---
drivers/media/rc/sunxi-cir.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/media/rc/sunxi-cir.c b/drivers/media/rc/sunxi-cir.c
There are some minor differences between A31 and A64 driver.
But A31 IR driver is compatible with A64.
Signed-off-by: Clément Péron
Acked-by: Sean Young
---
Documentation/devicetree/bindings/media/sunxi-ir.txt | 1 +
1 file changed, 1 insertion(+)
diff --git
There are some minor differences between A31 or A64 with H6 IR peripheral.
But A31 IR driver is compatible with H6.
Signed-off-by: Clément Péron
Acked-by: Sean Young
---
Documentation/devicetree/bindings/media/sunxi-ir.txt | 1 +
1 file changed, 1 insertion(+)
diff --git
This driver is used in various Allwinner SoC with different configuration.
Introduce a quirks struct to know the fifo size and if a reset is required.
Signed-off-by: Clément Péron
Acked-by: Sean Young
---
drivers/media/rc/sunxi-cir.c | 61 +++-
1 file changed,
Allwinner H6 IR is similar to A31 and can use same driver.
Add support for it.
Signed-off-by: Clément Péron
Acked-by: Sean Young
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 19 +++
1 file changed, 19 insertions(+)
diff --git
Enable CONFIG_IR_SUNXI option for ARM64, so that Allwinner A64/H6 SoCs
can use their IR receiver controller.
Signed-off-by: Clément Péron
Acked-by: Sean Young
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig
Beelink GS1, OrangePi H6 boards and Pine H64 have an IR receiver.
Enable it in their device-tree.
Signed-off-by: Clément Péron
---
arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts | 4
arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi | 4
From: Igors Makejevs
IR peripheral is completely compatible with A31 one.
Signed-off-by: Igors Makejevs
Signed-off-by: Jernej Skrabec
Signed-off-by: Clément Péron
Acked-by: Sean Young
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 18 ++
1 file changed, 18
Since A31, memory mapping of the IR driver has changed.
Prefer the A31 bindings instead of A13.
Signed-off-by: Clément Péron
Acked-by: Sean Young
---
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
We are using RXINT bits definition when looking at RXSTA register.
These bits are equal but it's not really proper.
Introduce the RXSTA bits and use them to have coherency.
Signed-off-by: Clément Péron
---
drivers/media/rc/sunxi-cir.c | 18 --
1 file changed, 12 insertions(+),
Since A31, memory mapping of the IR driver has changed.
Prefer the A31 bindings instead of A13.
Signed-off-by: Clément Péron
Acked-by: Sean Young
---
arch/arm/boot/dts/sun6i-a31.dtsi | 2 +-
arch/arm/boot/dts/sun8i-a83t.dtsi | 2 +-
arch/arm/boot/dts/sun9i-a80.dtsi | 2 +-
3 files changed,
Hi,
A64 IR support series[1] pointed out that an A31 bindings should be
introduced.
This series introduce the A31 compatible bindings, then switch it on
the already existing board.
Finally introduce A64 and H6 support.
I have reenable the other H6 boards IR support as Ondrej solve the issue.
Allwinner A31 has introduced a new memory mapping and a
reset line.
The difference in memory mapping are :
- In the configure register there is a new sample bit
and Allwinner has introduced the active threshold feature.
- In the status register a new STAT bit is present.
Note: CGPO and
Hi Clément,
On Tue, Jun 04, 2019 at 06:14:15PM +0200, Clément Péron wrote:
> Hi Ondrej,
>
> On Tue, 4 Jun 2019 at 17:40, megous via linux-sunxi
> wrote:
> >
> > From: Ondrej Jirman
> >
> > The current code defines W1 clock gate to be at 0x1cc, overlaying it
> > with the IR gate.
> >
> > Clock
Hi Ondrej,
On Tue, 4 Jun 2019 at 17:40, megous via linux-sunxi
wrote:
>
> From: Ondrej Jirman
>
> The current code defines W1 clock gate to be at 0x1cc, overlaying it
> with the IR gate.
>
> Clock gate for r-apb1-w1 is at 0x1ec. This fixes issues with IR receiver
> causing interrupt floods on
Hi Ondrej,
On Tue, 4 Jun 2019 at 17:30, Ondřej Jirman wrote:
>
> Hi Clément,
>
> On Tue, Jun 04, 2019 at 05:04:07PM +0200, Clément Péron wrote:
> > Hi Ondrej,
> >
> > On Tue, 4 Jun 2019 at 16:47, Ondřej Jirman wrote:
> > >
> > > Hi Clément,
> > >
> > > On Tue, Jun 04, 2019 at 02:33:55PM +0200,
Hello Jernej,
On Tue, Jun 04, 2019 at 05:35:48PM +0200, Jernej Škrabec wrote:
> Hi!
>
> Dne torek, 04. junij 2019 ob 17:31:20 CEST je 'Ondřej Jirman' via linux-sunxi
> napisal(a):
> > Hi Jernej,
> >
> > On Tue, Jun 04, 2019 at 05:03:55PM +0200, Jernej Škrabec wrote:
> > > Dne torek, 04. junij
From: Ondrej Jirman
The current code defines W1 clock gate to be at 0x1cc, overlaying it
with the IR gate.
Clock gate for r-apb1-w1 is at 0x1ec. This fixes issues with IR receiver
causing interrupt floods on H6 (because interrupt flags can't be cleared,
due to IR module's bus being disabled).
Hi!
Dne torek, 04. junij 2019 ob 17:31:20 CEST je 'Ondřej Jirman' via linux-sunxi
napisal(a):
> Hi Jernej,
>
> On Tue, Jun 04, 2019 at 05:03:55PM +0200, Jernej Škrabec wrote:
> > Dne torek, 04. junij 2019 ob 17:00:54 CEST je megous via linux-sunxi
> >
> > napisal(a):
> > > From: Ondrej Jirman
Hi Jernej,
On Tue, Jun 04, 2019 at 05:03:55PM +0200, Jernej Škrabec wrote:
> Dne torek, 04. junij 2019 ob 17:00:54 CEST je megous via linux-sunxi
> napisal(a):
> > From: Ondrej Jirman
> >
> > The current code defines W1 clock gate to be at 0x1cc, overlaying it
> > with the IR gate.
> >
> >
Hi Clément,
On Tue, Jun 04, 2019 at 05:04:07PM +0200, Clément Péron wrote:
> Hi Ondrej,
>
> On Tue, 4 Jun 2019 at 16:47, Ondřej Jirman wrote:
> >
> > Hi Clément,
> >
> > On Tue, Jun 04, 2019 at 02:33:55PM +0200, verejna wrote:
> > > Hi Clément,
> > >
> > > On Mon, Jun 03, 2019 at 09:58:23PM
Hi,
On Tue, 4 Jun 2019 at 16:54, Ondřej Jirman wrote:
>
> On Tue, May 28, 2019 at 06:14:31PM +0200, Clément Péron wrote:
> > Allwiner A31 has a different memory mapping so add the compatible
> > we will need it later.
> >
> > Signed-off-by: Clément Péron
> > ---
> >
Hi Ondrej,
On Tue, 4 Jun 2019 at 16:47, Ondřej Jirman wrote:
>
> Hi Clément,
>
> On Tue, Jun 04, 2019 at 02:33:55PM +0200, verejna wrote:
> > Hi Clément,
> >
> > On Mon, Jun 03, 2019 at 09:58:23PM +0200, Clément Péron wrote:
> > > Hi Ondrej,
> > >
> > > On Fri, 31 May 2019 at 14:46, Ondřej
Dne torek, 04. junij 2019 ob 17:00:54 CEST je megous via linux-sunxi
napisal(a):
> From: Ondrej Jirman
>
> The current code defines W1 clock gate to be at 0x1cc, overlaying it
> with the IR gate.
>
> Clock gate for r-apb1-w1 is at 0x1ec. This fixes issues with IR receiver
> causing interrupt
From: Ondrej Jirman
The current code defines W1 clock gate to be at 0x1cc, overlaying it
with the IR gate.
Clock gate for r-apb1-w1 is at 0x1ec. This fixes issues with IR receiver
causing interrupt floods on H6 (because interrupt flags can't be cleared,
due to IR module's bus being disabled).
On Tue, May 28, 2019 at 06:14:31PM +0200, Clément Péron wrote:
> Allwiner A31 has a different memory mapping so add the compatible
> we will need it later.
>
> Signed-off-by: Clément Péron
> ---
> drivers/media/rc/sunxi-cir.c | 9 +
> 1 file changed, 9 insertions(+)
>
> diff --git
Hi Clément,
On Tue, Jun 04, 2019 at 02:33:55PM +0200, verejna wrote:
> Hi Clément,
>
> On Mon, Jun 03, 2019 at 09:58:23PM +0200, Clément Péron wrote:
> > Hi Ondrej,
> >
> > On Fri, 31 May 2019 at 14:46, Ondřej Jirman wrote:
> > >
> > > Hello Clément,
> > >
> > > On Fri, May 31, 2019 at
On Fri, May 24, 2019 at 03:37:36PM +0530, Jagan Teki wrote:
> On Fri, May 24, 2019 at 2:18 AM Maxime Ripard
> wrote:
> >
> > On Mon, May 20, 2019 at 02:33:11PM +0530, Jagan Teki wrote:
> > > pll-video => pll-mipi => tcon0 => tcon0-pixel-clock is the typical
> > > MIPI clock topology in Allwinner
Hi Clément,
On Mon, Jun 03, 2019 at 09:58:23PM +0200, Clément Péron wrote:
> Hi Ondrej,
>
> On Fri, 31 May 2019 at 14:46, Ondřej Jirman wrote:
> >
> > Hello Clément,
> >
> > On Fri, May 31, 2019 at 12:25:32AM +0200, Clément Péron wrote:
> > > Hi Ondrej,
> > >
> > > On Thu, 30 May 2019 at 16:55,
On Tue, 4 Jun 2019 at 09:53, Chen-Yu Tsai wrote:
>
> On Tue, Jun 4, 2019 at 1:47 AM wrote:
> >
> > From: Marcus Cooper
> >
> > On the newer SoCs this is set by default to transfer a 0 after
> > each sample in each slot. However the platform that this driver
> > was developed on had the default
On Wed, May 29, 2019 at 11:44:56PM +0530, Jagan Teki wrote:
> On Wed, May 29, 2019 at 8:24 PM Maxime Ripard
> wrote:
> >
> > On Fri, May 24, 2019 at 03:48:51PM +0530, Jagan Teki wrote:
> > > On Fri, May 24, 2019 at 2:04 AM Maxime Ripard
> > > wrote:
> > > >
> > > > On Mon, May 20, 2019 at
On Tue, 4 Jun 2019 at 11:02, Christopher Obbard wrote:
>
> On Tue, 4 Jun 2019 at 09:43, Code Kipper wrote:
> >
> > On Tue, 4 Jun 2019 at 09:58, Maxime Ripard
> > wrote:
> > >
> > > On Mon, Jun 03, 2019 at 07:47:32PM +0200, codekip...@gmail.com wrote:
> > > > From: Marcus Cooper
> > > >
> > >
On Tue, 4 Jun 2019 at 09:46, Maxime Ripard wrote:
>
> On Mon, Jun 03, 2019 at 07:47:30PM +0200, codekip...@gmail.com wrote:
> > From: Marcus Cooper
> >
> > We have a number of flags used to identify the functionality
> > of the IP block found on the sun8i-h3 and later devices. As it
> > is only
On Tue, 4 Jun 2019 at 09:43, Code Kipper wrote:
>
> On Tue, 4 Jun 2019 at 09:58, Maxime Ripard wrote:
> >
> > On Mon, Jun 03, 2019 at 07:47:32PM +0200, codekip...@gmail.com wrote:
> > > From: Marcus Cooper
> > >
> > > The i2s block supports multi-lane i2s output however this functionality
> > >
On Tue, 4 Jun 2019 at 09:58, Maxime Ripard wrote:
>
> On Mon, Jun 03, 2019 at 07:47:32PM +0200, codekip...@gmail.com wrote:
> > From: Marcus Cooper
> >
> > The i2s block supports multi-lane i2s output however this functionality
> > is only possible in earlier SoCs where the pins are exposed and
On Mon, Jun 03, 2019 at 07:09:48PM +, Kamps, John-Eric wrote:
> >Do you have a setup that works with the BSP? Usually in cases like
> >this I would dump the >registers of the whole display engine and
> >the TCON, and compare them to see what's going on.
>
> Not yet tested, because the new
On Mon, Jun 03, 2019 at 07:47:35PM +0200, codekip...@gmail.com wrote:
> From: Marcus Cooper
>
> Bypass the regmap cache when flushing the i2s FIFOs and modify the tables
> to reflect this.
>
> Signed-off-by: Marcus Cooper
> ---
> sound/soc/sunxi/sun4i-i2s.c | 29 +
>
On Mon, Jun 03, 2019 at 07:47:34PM +0200, codekip...@gmail.com wrote:
> From: Marcus Cooper
>
> Extend the functionality of the driver to include support of 20 and
> 24 bits per sample for the earlier SoCs.
>
> Newer SoCs can also handle 32bit samples.
>
> Signed-off-by: Marcus Cooper
> ---
>
On Tue, 4 Jun 2019 at 09:39, Chen-Yu Tsai wrote:
>
> On Tue, Jun 4, 2019 at 3:34 PM Maxime Ripard
> wrote:
> >
> > On Mon, Jun 03, 2019 at 07:47:27PM +0200, codekip...@gmail.com wrote:
> > > From: Marcus Cooper
> > >
> > > Although not causing any noticeable issues, the mask for the
> > >
On Mon, Jun 03, 2019 at 07:47:32PM +0200, codekip...@gmail.com wrote:
> From: Marcus Cooper
>
> The i2s block supports multi-lane i2s output however this functionality
> is only possible in earlier SoCs where the pins are exposed and for
> the i2s block used for HDMI audio on the later SoCs.
>
>
On Tue, Jun 4, 2019 at 1:47 AM wrote:
>
> From: Marcus Cooper
>
> On the newer SoCs this is set by default to transfer a 0 after
> each sample in each slot. However the platform that this driver
> was developed on had the default setting where it padded the
> audio gain with zeros. This isn't a
On Mon, Jun 03, 2019 at 07:47:31PM +0200, codekip...@gmail.com wrote:
> From: Marcus Cooper
>
> Some codecs require a different amount of a bit clocks per frame than
Which codec? And what are the actual requirements?
> what is calculated by the sample width. Use the tdm slot bindings to
>
On Mon, Jun 03, 2019 at 07:47:30PM +0200, codekip...@gmail.com wrote:
> From: Marcus Cooper
>
> We have a number of flags used to identify the functionality
> of the IP block found on the sun8i-h3 and later devices. As it
> is only neccessary to identify this new block then replace
> these flags
On Mon, Jun 03, 2019 at 07:47:29PM +0200, codekip...@gmail.com wrote:
> From: Marcus Cooper
>
> On the newer SoCs this is set by default to transfer a 0 after
Which SoCs?
> each sample in each slot. However the platform that this driver
Which platform?
> was developed on had the default
On Tue, Jun 4, 2019 at 3:37 PM Maxime Ripard wrote:
>
> On Mon, Jun 03, 2019 at 07:47:28PM +0200, codekip...@gmail.com wrote:
> > From: Marcus Cooper
> >
> > Whilst testing the capture functionality of the i2s on the newer
> > SoCs it was noticed that the recording was somewhat distorted.
> >
On Mon, Jun 03, 2019 at 07:47:28PM +0200, codekip...@gmail.com wrote:
> From: Marcus Cooper
>
> Whilst testing the capture functionality of the i2s on the newer
> SoCs it was noticed that the recording was somewhat distorted.
> This was due to the offset not being set correctly on the receiver
>
On Mon, Jun 03, 2019 at 07:47:27PM +0200, codekip...@gmail.com wrote:
> From: Marcus Cooper
>
> Although not causing any noticeable issues, the mask for the
> channel offset is covering too many bits.
>
> Signed-off-by: Marcus Cooper
Acked-by: Maxime Ripard
Maxime
--
Maxime Ripard, Bootlin
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