sun8i_dwmac_unpower_internal_phy already checks if the PHY is powered,
so there is no need to do it again here.
Signed-off-by: Samuel Holland
---
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/net/ethernet
Adjust the spacing and use an explicit "return 0" in the success path
to make the function easier to parse.
Signed-off-by: Samuel Holland
---
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethern
This is a deinitialization function that always returned zero, and that
return value was always ignored. Have it return void instead.
Signed-off-by: Samuel Holland
---
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a
requires
changing the sun8i_dwmac_set_syscon parameters to priv's two relevant
members.
Fixes: 9f93ac8d4085 ("net-next: stmmac: Add dwmac-sun8i")
Fixes: 634db83b8265 ("net: stmmac: dwmac-sun8i: Handle integrated/external
MDIOs")
Signed-off-by: Samuel Holland
---
.../ne
t;net: stmmac: dwmac-sun8i: Handle integrated/external
MDIOs")
Signed-off-by: Samuel Holland
---
.../net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 31 ++-
1 file changed, 23 insertions(+), 8 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
b/drivers/ne
n in
exit path")
Signed-off-by: Samuel Holland
---
.../net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 25 +++
1 file changed, 15 insertions(+), 10 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.
handling and driver removal.
Samuel Holland (4):
net: stmmac: dwmac-sun8i: Fix probe error handling
net: stmmac: dwmac-sun8i: Balance internal PHY resource references
net: stmmac: dwmac-sun8i: Balance internal PHY power
net: stmmac: dwmac-sun8i: Balance syscon (de)initialization
.../net
("net: stmmac: dwmac-sun8i: Handle integrated/external
MDIOs")
Signed-off-by: Samuel Holland
---
.../net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 27 ++-
1 file changed, 21 insertions(+), 6 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
b/drive
RSB clock frequency is stored in `struct sunxi_rsb` so it
will be available when reinitializing the hardware.
Signed-off-by: Samuel Holland
---
drivers/bus/sunxi-rsb.c | 127 ++--
1 file changed, 71 insertions(+), 56 deletions(-)
diff --git a/drivers/bus/sunxi
enabled, to handle
wakeup event IRQs coming from the PMIC. Thus it uses NOIRQ callbacks.
Signed-off-by: Samuel Holland
---
drivers/bus/sunxi-rsb.c | 30 ++
1 file changed, 30 insertions(+)
diff --git a/drivers/bus/sunxi-rsb.c b/drivers/bus/sunxi-rsb.c
index
This series adds system (complete power down) and runtime (clock gate)
PM hooks to the RSB controller driver. Tested on A64 and H6.
Samuel Holland (4):
bus: sunxi-rsb: Move OF match table
bus: sunxi-rsb: Split out controller init/exit functions
bus: sunxi-rsb: Implement suspend/resume
For some reason, this driver's OF match table was placed above the
probe/remove functions, far away from the platform_driver definition.
Adding device PM ops would move the table even farther away. Let's move
it to the usual place, right before the platform_driver.
Signed-off-by: Samu
Gate the clock to save power while the controller is idle.
Signed-off-by: Samuel Holland
---
drivers/bus/sunxi-rsb.c | 44 +
1 file changed, 44 insertions(+)
diff --git a/drivers/bus/sunxi-rsb.c b/drivers/bus/sunxi-rsb.c
index efd222f36cdc..ba5100dfc413
: Samuel Holland
---
drivers/input/keyboard/sun4i-lradc-keys.c | 22 ++
1 file changed, 18 insertions(+), 4 deletions(-)
diff --git a/drivers/input/keyboard/sun4i-lradc-keys.c
b/drivers/input/keyboard/sun4i-lradc-keys.c
index 4a796bed48ac..4d0e8879a97d 100644
--- a/drivers/input
enough to reset it during every runtime suspend/resume.
Because the bus may be used by wakeup source IRQ threads, it needs to
be functional as soon as IRQs are enabled. Thus, its system PM hooks
need to run in the noirq phase.
Signed-off-by: Samuel Holland
---
drivers/i2c/busses/i2c-mv64xxx.c | 120
difference.
Signed-off-by: Samuel Holland
---
.../interrupt-controller/allwinner,sun6i-a31-r-intc.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git
a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun6i-a31-r-intc.yaml
b/Documentation/devicetree/bindings/interrupt
) from interrupt 0 in the new
binding (SPI 0) by the number of cells.
Signed-off-by: Samuel Holland
---
.../allwinner,sun6i-a31-r-intc.yaml | 64 +++
.../allwinner,sun7i-a20-sc-nmi.yaml | 10 ---
2 files changed, 64 insertions(+), 10 deletions(-)
create mode 100644
-by: Samuel Holland
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 4
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 3 +++
2 files changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index fd4bf90163d5
The binding of R_INTC was updated to allow specifying interrupts other
than the external NMI, since routing those interrupts through the R_INTC
driver allows using them for wakeup.
Update the device trees to use the new binding.
Signed-off-by: Samuel Holland
---
arch/arm64/boot/dts/allwinner
The H3 and H5 SoCs have an additional interrupt controller in the RTC
power domain that can be used to enable wakeup for certain IRQs.
Add a node for it.
Signed-off-by: Samuel Holland
---
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm
-by: Samuel Holland
---
arch/arm/boot/dts/sun6i-a31.dtsi | 4
arch/arm/boot/dts/sun8i-a23-a33.dtsi | 4
arch/arm/boot/dts/sun8i-a83t.dtsi| 3 +++
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 3 +++
4 files changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch
driver mask flags from that one).
- Set IRQCHIP_EOI_THREADED to avoid doubled level interrupts, since the
latch will be set again as long as the trigger is met.
- Replace sun6i_r_intc_domain_translate() with
irq_domain_translate_twocell().
- Use an enum for the device tree binding.
- Update commit
y the three-cell GIC binding; this disambiguates
interrupt 0 in the old binding (the NMI) from interrupt 0 in the new
binding (SPI 0) by the number of cells.
This commit mostly reverts commit 173bda53b340 ("irqchip/sunxi-nmi:
Support sun6i-a31-r-intc compatible").
Signed-off-by: Sa
tion.
Signed-off-by: Samuel Holland
---
arch/arm/boot/dts/sun6i-a31-hummingbird.dts | 2 +-
arch/arm/boot/dts/sun6i-a31-m9.dts | 2 +-
arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts | 2 +-
arch/arm/boot/dts/sun6i-a31.dtsi | 2 +
The binding of R_INTC was updated to allow specifying interrupts other
than the external NMI, since routing those interrupts through the R_INTC
driver allows using them for wakeup.
Update the device trees to use the new binding.
Signed-off-by: Samuel Holland
---
arch/arm/boot/dts/sun6i-a31
ot;).
Signed-off-by: Samuel Holland
---
drivers/irqchip/irq-sun6i-r.c | 90 ++-
1 file changed, 88 insertions(+), 2 deletions(-)
diff --git a/drivers/irqchip/irq-sun6i-r.c b/drivers/irqchip/irq-sun6i-r.c
index 7490ade7b254..70be0fd228c2 100644
--- a/drivers/irqchip
: Samuel Holland
---
.../dts/allwinner/sun50i-h6-beelink-gs1.dts | 38 +--
.../dts/allwinner/sun50i-h6-orangepi-3.dts| 14 +++
.../dts/allwinner/sun50i-h6-orangepi.dtsi | 22 +--
3 files changed, 37 insertions(+), 37 deletions(-)
diff --git a/arch/arm64/boot/dts
ese
pins is actually RSB, and that is indeed the case.
Add the "s_rsb" pin functions so the RSB controller can be used.
Signed-off-by: Samuel Holland
---
drivers/pinctrl/sunxi/pinctrl-sun50i-h6-r.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/pinctrl/sunxi/pinctrl-su
at the end
to maintain the existing DT binding. The code is kept in register order.
Signed-off-by: Samuel Holland
---
drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c | 5 +
drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h | 2 +-
include/dt-bindings/clock/sun50i-h6-r-ccu.h | 2 ++
include/dt-bindings
The H6 SoC contains an undocumented but fully functional RSB controller.
Add support for it. The MMIO register address matches other SoCs of the
same generation, and the IRQ matches a hole in the documented IRQ list.
Signed-off-by: Samuel Holland
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
Put the new values at the end of the DT binding headers
Samuel Holland (4):
clk: sunxi-ng: h6-r: Add R_APB2_RSB clock and reset
pinctrl: sunxi: h6-r: Add s_rsb pin functions
arm64: dts: allwinner: h6: Add RSB controller node
arm64: dts: allwinner: h6: Use RSB for AXP805 PMIC connection
.../
On 12/14/20 8:57 AM, Maxime Ripard wrote:
> Hi Samuel,
>
> On Sun, Dec 13, 2020 at 05:55:03PM -0600, Samuel Holland wrote:
>> While no information about the H6 RSB controller is included in the
>> datasheet or manual, the vendor BSP and power management blob both
>> ref
ese
pins is actually RSB, and that is indeed the case.
Add the "s_rsb" pin functions so the RSB controller can be used.
Signed-off-by: Samuel Holland
---
drivers/pinctrl/sunxi/pinctrl-sun50i-h6-r.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/pinctrl/sunxi/pinctrl-su
The H6 SoC contains an undocumented but fully functional RSB controller.
Add support for it. The MMIO register address matches other SoCs of the
same generation, and the IRQ matches a hole in the documented IRQ list.
Signed-off-by: Samuel Holland
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
at the end
to maintain the existing DT binding. The code is kept in register order.
Signed-off-by: Samuel Holland
---
drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c | 5 +
drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h | 2 +-
include/dt-bindings/clock/sun50i-h6-r-ccu.h | 1 +
include/dt-bindings
reliable than the I2C controller IP in the SoC, switch to
using it where possible.
This was tested on an Orange Pi 3 and a Pine H64 model B. This series
does not switch the Pine H64 to use RSB, as doing so would prevent
accessing the external RTC that shares the I2C bus.
Samuel Holland (4):
clk
: Samuel Holland
---
.../dts/allwinner/sun50i-h6-beelink-gs1.dts | 38 +--
.../dts/allwinner/sun50i-h6-orangepi-3.dts| 14 +++
.../dts/allwinner/sun50i-h6-orangepi.dtsi | 22 +--
3 files changed, 37 insertions(+), 37 deletions(-)
diff --git a/arch/arm64/boot/dts
Andre,
On 12/2/20 7:54 AM, Andre Przywara wrote:
...
> + soc {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0 0x0 0x0 0x4000>;
> +
> + syscon: syscon@300 {
> +
On 12/2/20 10:05 AM, Maxime Ripard wrote:
>> +timer {
>> +compatible = "arm,armv8-timer";
>> +arm,no-tick-in-suspend;
>
> This was tested with crust I assume?
No, there is no AR100 and supposedly no SRAM A2, so there is no place for crust
to run. I assume it was copied
On 12/2/20 12:20 PM, Jernej Škrabec wrote:
>> +};
>> +
>> +static struct clk_hw_onecell_data sun50i_h616_r_hw_clks = {
>> +.hws= {
>> +[CLK_R_AHB] = &r_ahb_clk.hw,
>> +[CLK_R_APB1]= &r_apb1_clk.common.hw,
>> +[CLK_R_APB2]
Maxime,
On 11/20/20 5:30 PM, Icenowy Zheng wrote:
>>> +/ {
>>> + model = "PineTab Developer Sample";
>>> + compatible = "pine64,pinetab-dev", "allwinner,sun50i-a64";
>>> +};
>>
>> Changing the DT and the compatible half-way through it isn't ok. Please
>> add
unxi_egon.c| 136 ++
> 7 files changed, 226 insertions(+), 68 deletions(-)
> create mode 100644 include/sunxi_image.h
> create mode 100644 tools/sunxi_egon.c
>
For the series:
Reviewed-by: Samuel Holland
Tested-by: Samuel Holland
--
You receive
On 11/18/20 11:32 AM, Andre Przywara wrote:
> So far we used the separate mksunxiboot tool for generating a bootable
> image for Allwinner SPLs, probably just for historical reasons.
>
> Use the mkimage framework to generate a so called eGON image the
> Allwinner BROM expects.
> The new image type
ng zero byte. */
> + ((char *)header->string_pool)[51] = 0;
> + } else
> + header->spl_signature[3] = SPL_ENV_HEADER_VERSION;
> +
> + /* Calculate the checksum. Yes, it's that simple. */
> + for (i = 0; i < sbuf->st_size / 4; i++)
&g
Instead of duplicating part of the compatible string in the node name,
use generic names as recommended by (and listed in) section 2.2.2 of the
Devicetree Specification.
Suggested-by: Maxime Ripard
Signed-off-by: Samuel Holland
---
arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi | 6
supply.
Signed-off-by: Samuel Holland
---
arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi | 4
1 file changed, 4 deletions(-)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
index 25150aba749d
external supply.
Signed-off-by: Samuel Holland
---
arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
From: Luca Weiss
All revisions of the PinePhone have an SGM3140 LED flash. The gpios were
swapped on v1.0 of the board, but this was fixed in later revisions.
Signed-off-by: Luca Weiss
Signed-off-by: Samuel Holland
---
.../boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts | 5
From: Ondrej Jirman
The PinePhone has a Realtek rtl8723cs WiFi module.
On mainboard revisions 1.0 and 1.1, the reset input is always pulled
high, so no power sequence is needed. On mainboard revision 1.2, the
reset input is connected to PL2.
Signed-off-by: Ondrej Jirman
Signed-off-by: Samuel
From: Ondrej Jirman
The PinePhone has a Realtek rtl8723cs Bluetooth controller.
Signed-off-by: Ondrej Jirman
Signed-off-by: Samuel Holland
---
.../boot/dts/allwinner/sun50i-a64-pinephone.dtsi| 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner
: pinephone: Add light/proximity sensor
arm64: dts: allwinner: pinephone: Add WiFi support
arm64: dts: allwinner: pinephone: Add Bluetooth support
Samuel Holland (2):
arm64: dts: allwinner: pinephone: Remove AC power supply
arm64: dts: allwinner: pinephone: Set ALDO3 to exactly 3v0
From: Ondrej Jirman
Pinephone has STK3311-X proximity sensor. Add support for it.
Signed-off-by: Ondrej Jirman
Signed-off-by: Samuel Holland
---
.../arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts
On 10/27/20 4:43 PM, Clément Péron wrote:
> Hi Pierre-Louis,
>
> On Tue, 27 Oct 2020 at 19:59, Pierre-Louis Bossart
> wrote:
>>
>>
>>> @@ -452,11 +454,11 @@ static int sun8i_i2s_set_chan_cfg(const struct
>>> sun4i_i2s *i2s,
>>> case SND_SOC_DAIFMT_DSP_B:
>>> case SND_SOC_DAIFMT_LEFT_
Icenowy,
On 10/26/20 7:12 AM, Andrew Lunn wrote:
>> By referring to linux/phy.h, NA means not applicable. This surely
>> do not apply when RGMII is really in use.
>
> It means the PHY driver should not touch the mode, something else has
> set it up. That could be strapping, the bootloader, ACPI f
et_chan_cfg(). This will
>>>> duplicate the same check instead pass the required values
>>>> as params to set_chan_cfg().
>>>>
>>>> This will also avoid a bug when we will enable 20/24bits support,
>>>> i2s->slot_width is not
; i2s->slot_width is not actually used in the lrck_period computation.
>>
>> Suggested-by: Samuel Holland
>> Signed-off-by: Clément Péron
>> ---
>> sound/soc/sunxi/sun4i-i2s.c | 36 ++--
>> 1 file changed, 14 insertio
On 9/29/20 10:40 AM, Mark Rutland wrote:
> Hi,
>
> Please Cc maintainers for drivers -- Marc and I maintain the arch timer
> driver.
>
> On Tue, Sep 29, 2020 at 02:13:47PM +0300, Roman Stratiienko wrote:
>> Fixes linux_kselftest:timers_inconsistency-check_arm_64
>>
>> Test logs without the fix:
>
On 9/20/20 1:07 PM, Clément Péron wrote:
> The FIFO TX reg is volatile and sun8i i2s register
> mapping is different from sun4i.
>
> Even if in this case it's doesn't create an issue,
> Avoid setting some regs that are undefined in sun8i.
>
> Signed-off-by: Clément Péron
> Acked-by: Maxime Ripar
On 9/20/20 1:07 PM, Clément Péron wrote:
> From: Marcus Cooper
>
> Extend the functionality of the driver to include support of 20 and
> 24 bits per sample.
>
> Signed-off-by: Marcus Cooper
> Signed-off-by: Clément Péron
> Acked-by: Maxime Ripard
> ---
> sound/soc/sunxi/sun4i-i2s.c | 11
On 9/20/20 1:07 PM, Clément Péron wrote:
> From: Jernej Skrabec
>
> H6 I2S is very similar to that in H3, except it supports up to 16
> channels.
>
> Signed-off-by: Jernej Skrabec
> Signed-off-by: Marcus Cooper
> Signed-off-by: Clément Péron
> ---
> sound/soc/sunxi/sun4i-i2s.c | 218
Clément,
On 9/3/20 3:30 PM, Clément Péron wrote:
> From: Marcus Cooper
>
> Some codecs such as i2s based HDMI audio and the Pine64 DAC require
> a different amount of bit clocks per frame than what is calculated
> by the sample width. Use the values obtained by the tdm slot bindings
> to adjust
Clément,
On 9/3/20 3:30 PM, Clément Péron wrote:
> From: Jernej Skrabec
>
> H6 I2S is very similar to that in H3, except it supports up to 16
> channels.
>
> Signed-off-by: Jernej Skrabec
> Signed-off-by: Marcus Cooper
> Signed-off-by: Clément Péron
> ---
> sound/soc/sunxi/sun4i-i2s.c | 221
On 9/2/20 1:10 PM, Jernej Škrabec wrote:
> Hi Samuel!
>
> Dne petek, 10. julij 2020 ob 07:44:51 CEST je Samuel Holland napisal(a):
>> On 7/4/20 6:38 AM, Clément Péron wrote:
>>> From: Marcus Cooper
>>>
>>> Extend the functionality of the driver to includ
Clément,
On 7/4/20 6:38 AM, Clément Péron wrote:
> From: Marcus Cooper
>
> Add the new DAI block for I2S2 which is used for HDMI audio.
>
> Signed-off-by: Marcus Cooper
> Signed-off-by: Clément Péron
> ---
> arch/arm/boot/dts/sunxi-h3-h5.dtsi | 13 +
> 1 file changed, 13 insertio
Jernej,
On 7/10/20 2:22 PM, Jernej Škrabec wrote:
>> From the description in the manual, this looks off by one. The number of
>> BCLKs per LRCK is LRCK_PERIOD + 1.
>
> Are you sure? Macro SUN8I_I2S_FMT0_LRCK_PERIOD() is defined as follows:
>
> #define SUN8I_I2S_FMT0_LRCK_PERIOD(period)((peri
On 7/4/20 6:38 AM, Clément Péron wrote:
> From: Marcus Cooper
>
> On the newer SoCs such as the H3 and A64 this is set by default
> to transfer a 0 after each sample in each slot. However the A10
> and A20 SoCs that this driver was developed on had a default
> setting where it padded the audio ga
On 7/4/20 6:38 AM, Clément Péron wrote:
> From: Jernej Skrabec
>
> H6 I2S is very similar to that in H3, except it supports up to 16
> channels.
>
> Signed-off-by: Jernej Skrabec
> Signed-off-by: Marcus Cooper
> Signed-off-by: Clément Péron
> ---
> sound/soc/sunxi/sun4i-i2s.c | 227 +
On 7/4/20 6:38 AM, Clément Péron wrote:
> From: Marcus Cooper
>
> Extend the functionality of the driver to include support of 20 and
> 24 bits per sample.
>
> Signed-off-by: Marcus Cooper
> Signed-off-by: Clément Péron
> ---
> sound/soc/sunxi/sun4i-i2s.c | 11 +--
> 1 file changed, 9
On 7/4/20 6:38 AM, Clément Péron wrote:
> From: Marcus Cooper
>
> Some codecs such as i2s based HDMI audio and the Pine64 DAC require
> a different amount of bit clocks per frame than what is calculated
> by the sample width. Use the values obtained by the tdm slot bindings
> to adjust the LRCLK
On 6/8/20 3:48 AM, Maxime Ripard wrote:
> On Sun, May 24, 2020 at 11:12:54PM -0500, Samuel Holland wrote:
>> The R_INTC in the A31 and newer sun8i/sun50i SoCs is more similar to the
>> original sun4i interrupt controller than the sun7i/sun9i NMI controller.
>> It is used for
On 5/13/20 4:24 PM, Ondrej Jirman wrote:
> From: Icenowy Zheng
>
> Xingbangda XBD599 is a 5.99" 720x1440 MIPI-DSI IPS LCD panel made by
> Xingbangda, which is used on PinePhone final assembled phones.
>
> It is based on Sitronix ST7703 LCD controller.
>
> Add support for it.
>
> Signed-off-by:
All IRQs that can be used to wake up the system must be routed through
r_intc, so they are visible to firmware while the system is suspended.
For the A64, r_intc IRQ numbers are offset by 32 from the GIC IRQ
numbers.
Signed-off-by: Samuel Holland
---
arch/arm64/boot/dts/allwinner/sun50i-a64
This node was indented by two tabs when added instead of one.
Remove the extra tab.
Signed-off-by: Samuel Holland
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 22 ++--
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6
output and the GIC NMI input.
This commit mostly reverts commit 173bda53b340 ("irqchip/sunxi-nmi:
Support sun6i-a31-r-intc compatible").
Signed-off-by: Samuel Holland
---
arch/arm/mach-sunxi/Kconfig | 4 +
arch/arm64/Kconfig.platforms| 2 +
dri
All IRQs that can be used to wake up the system must be routed through
r_intc, so they are visible to firmware while the system is suspended.
For the A83T, r_intc IRQ numbers are offset by 32 from the GIC IRQ
numbers.
Signed-off-by: Samuel Holland
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 9
e trigger is met.
- Replace sun6i_r_intc_domain_translate() with
irq_domain_translate_twocell().
- Use an enum for the device tree binding.
- Update commit messages for accuracy and typos.
Samuel Holland (9):
irqchip/sun6i-r: Use a stacked irqchip driver
irqchip/sun6i-r: Add wakeup support
dt-binding
difference.
Signed-off-by: Samuel Holland
---
.../allwinner,sun7i-a20-sc-nmi.yaml | 12 +---
1 file changed, 5 insertions(+), 7 deletions(-)
diff --git
a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml
b/Documentation/devicetree
The H3 and H5 SoCs have an additional interrupt controller in the RTC
power domain that can be used to enable wakeup for certain IRQs.
Add a node for it.
Signed-off-by: Samuel Holland
---
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm
All IRQs that can be used to wake up the system must be routed through
r_intc, so they are visible to firmware while the system is suspended.
For the H6, r_intc IRQ numbers are offset by 96 from the GIC IRQ
numbers.
Signed-off-by: Samuel Holland
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
All IRQs that can be used to wake up the system must be routed through
r_intc, so they are visible to firmware while the system is suspended.
For the H3/H5, r_intc IRQ numbers are offset by 32 from the GIC IRQ
numbers.
Signed-off-by: Samuel Holland
---
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 11
sources Linux wants
to have enabled. That way, it can avoid turning them off when it shuts
down the remainder of the clock tree. Second, it preconfigures the
coprocessor's interrupt controller, so the firmware's wakeup logic
is as simple as waiting for an interrupt to arrive.
Signed-off-
h edge and level interrupts. I tested both
triggers, albeit with the same source of (level) interrupts connected to the NMI
pin.
On 1/20/20 4:52 AM, Marc Zyngier wrote:
> Hi Samuel,
>
> On 2020-01-13 05:49, Samuel Holland wrote:
>> The R_INTC in the A31 and newer sun8i/sun50i So
() is now placed just before the
codec-specific callback that programs the hardware.
Cc:
Fixes: 50e761516f2b ("media: platform: Add Cedrus VPU decoder driver")
Suggested-by: Jernej Skrabec
Suggested-by: Paul Kocialkowski
Signed-off-by: Samuel Holland
Tested-by: Jernej Skrabec
Reviewed-
From: Jernej Skrabec
This allows the VE clocks and PLL_VE to be disabled most of the time.
A runtime PM reference is held while streaming.
Signed-off-by: Jernej Skrabec
Signed-off-by: Samuel Holland
Tested-by: Jernej Skrabec
Reviewed-by: Ezequiel Garcia
---
v2: moved PM reference to
On 5/5/20 7:53 AM, Ezequiel Garcia wrote:
> On Wed, 22 Apr 2020 at 01:00, Samuel Holland wrote:
>>
>> This allows the VE clocks and PLL_VE to be disabled most of the time.
>> A runtime PM reference is held while streaming.
>>
>> Originally-by: Jernej Škrabec
>
quot;cpvdd". This board's device tree still uses the old name, which fails
to work at runtime, and which causes a warning from `make dtbs_check`.
Resolve both by fixing the name.
Fixes: 674ef1d0a7b2 ("arm64: dts: allwinner: a64: add support for PineTab")
Signed-off-by: Samue
specific functionality, so the sound
card and codec DAI belong in the individual board DTS, not the SoC DTSI.
In fact, no in-tree A64 board DTS enables &spdif, so let's remove the
card and DAI entirely.
This reverts commit 78e071370a86473f25923e03b51cbbadacf8be0f.
Signed-off-by: Samuel Holland
---
Maxime,
On 4/22/20 10:16 AM, Maxime Ripard wrote:
> On Tue, Apr 21, 2020 at 11:15:02PM -0500, Samuel Holland wrote:
>> As of v5.7-rc2, Linux now prints the following message at boot:
>>
>> [ 33.848525] platform sound_spdif: deferred probe pending
>>
>> This i
Signed-off-by: Samuel Holland
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 6f8c30d89b9b..6c233ff031c6 100644
--- a/arch/arm64/boot/d
() is now placed just before the
codec-specific callback that programs the hardware.
Fixes: 50e761516f2b ("media: platform: Add Cedrus VPU decoder driver")
Suggested-by: Jernej Škrabec
Suggested-by: Paul Kocialkowski
Signed-off-by: Samuel Holland
---
v2: added patch
---
drivers/sta
This allows the VE clocks and PLL_VE to be disabled most of the time.
A runtime PM reference is held while streaming.
Originally-by: Jernej Škrabec
Signed-off-by: Samuel Holland
---
v2: moved PM reference to cedrus_{start,stop}_streaming, based on an
earlier patch by Jernej Skrabec
Hello Pascal,
On 3/17/20 10:59 AM, Pascal Roeleven wrote:
> When disabling, ensure the period write is complete before continuing.
> This fixes an issue on some devices when the write isn't complete before
> the panel is turned off but the clock gate is still on.
>
> Signed-off-by: Pascal Roeleve
On 4/8/20 11:01 AM, Jernej Škrabec wrote:
> Hi Samuel!
>
> Dne sreda, 08. april 2020 ob 03:02:32 CEST je Samuel Holland napisal(a):
>> This allows the VE clocks and PLL_VE to be disabled most of the time.
>>
>> Since the device is stateless, each frame gets a separ
This allows the VE clocks and PLL_VE to be disabled most of the time.
Since the device is stateless, each frame gets a separate runtime PM
reference. Enable autosuspend so the PM callbacks are not run before and
after every frame.
Signed-off-by: Samuel Holland
---
I tested this with v4l2
On 2/22/20 10:08 PM, Samuel Holland wrote:
> Samuel Holland (6):
> dt-bindings: mailbox: Add a binding for the sun6i msgbox
> mailbox: sun6i-msgbox: Add a new mailbox driver
These two patches have been applied for 5.7[1], so the DTS changes should be
ready to apply as well.
[
The A83T SoC contains a message box that can be used to send messages
and interrupts back and forth between the ARM application CPUs and the
ARISC coprocessor. Add a device tree node for it.
Tested-by: Ondrej Jirman
Signed-off-by: Samuel Holland
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 10
The H6 SoC contains a message box that can be used to send messages and
interrupts back and forth between the ARM application CPUs and the ARISC
coprocessor. Add a device tree node for it.
Signed-off-by: Samuel Holland
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 10 ++
1 file
The A64 SoC contains a message box that can be used to send messages and
interrupts back and forth between the ARM application CPUs and the ARISC
coprocessor. Add a device tree node for it.
Signed-off-by: Samuel Holland
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 10 ++
1 file
.
Reviewed-by: Philipp Zabel
Signed-off-by: Samuel Holland
---
drivers/mailbox/Kconfig| 9 +
drivers/mailbox/Makefile | 2 +
drivers/mailbox/sun6i-msgbox.c | 326 +
3 files changed, 337 insertions(+)
create mode 100644 drivers/mailbox/sun6i-msgbox.c
diff
This mailbox hardware is present in Allwinner sun6i, sun8i, sun9i, and
sun50i SoCs. Add a device tree binding for it.
Acked-by: Maxime Ripard
Reviewed-by: Rob Herring
Signed-off-by: Samuel Holland
---
.../mailbox/allwinner,sun6i-a31-msgbox.yaml | 80 +++
1 file changed, 80
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