On Mon, Mar 14, 2016 at 12:46:41PM +0100, Maxime Ripard wrote:
> On Fri, Mar 11, 2016 at 04:48:26PM +0530, Vinod Koul wrote:
> > > > But this nees to be property for clients and not driver. Client can then
> > > > program these
> > >
> > > Yes, totally. The question here is how the clients give
On Fri, Mar 11, 2016 at 04:48:26PM +0530, Vinod Koul wrote:
> > > But this nees to be property for clients and not driver. Client can then
> > > program these
> >
> > Yes, totally. The question here is how the clients give that
> > information to the driver.
>
> For this part am not worried. If
On Fri, Mar 11, 2016 at 11:26:31AM +0100, Boris Brezillon wrote:
> On Fri, 11 Mar 2016 15:36:07 +0530
> Vinod Koul wrote:
>
> > On Fri, Mar 11, 2016 at 10:40:55AM +0100, Boris Brezillon wrote:
> > > On Fri, 11 Mar 2016 11:54:52 +0530
> > > Vinod Koul
On Fri, Mar 11, 2016 at 11:55:49AM +0100, Maxime Ripard wrote:
> On Fri, Mar 11, 2016 at 03:39:02PM +0530, Vinod Koul wrote:
> > On Fri, Mar 11, 2016 at 10:45:52AM +0100, Boris Brezillon wrote:
> > > On Fri, 11 Mar 2016 11:56:07 +0530
> > > Vinod Koul wrote:
> > >
> > > >
On Fri, 11 Mar 2016 15:36:07 +0530
Vinod Koul wrote:
> On Fri, Mar 11, 2016 at 10:40:55AM +0100, Boris Brezillon wrote:
> > On Fri, 11 Mar 2016 11:54:52 +0530
> > Vinod Koul wrote:
> >
> > > On Wed, Mar 09, 2016 at 11:14:34AM +0100, Boris Brezillon
On Fri, Mar 11, 2016 at 10:45:52AM +0100, Boris Brezillon wrote:
> On Fri, 11 Mar 2016 11:56:07 +0530
> Vinod Koul wrote:
>
> > On Wed, Mar 09, 2016 at 12:06:27PM +0100, Boris Brezillon wrote:
> > > On Tue, 8 Mar 2016 08:25:47 +0530
> > > Vinod Koul
On Fri, Mar 11, 2016 at 10:40:55AM +0100, Boris Brezillon wrote:
> On Fri, 11 Mar 2016 11:54:52 +0530
> Vinod Koul wrote:
>
> > On Wed, Mar 09, 2016 at 11:14:34AM +0100, Boris Brezillon wrote:
> > > > > > > > + * struct sun4i_dma_chan_config - DMA channel config
> > > > > >
On Fri, 11 Mar 2016 11:56:07 +0530
Vinod Koul wrote:
> On Wed, Mar 09, 2016 at 12:06:27PM +0100, Boris Brezillon wrote:
> > On Tue, 8 Mar 2016 08:25:47 +0530
> > Vinod Koul wrote:
> > >
> > > Why does dmaengine need to wait? Can you explain that
> >
On Fri, 11 Mar 2016 11:54:52 +0530
Vinod Koul wrote:
> On Wed, Mar 09, 2016 at 11:14:34AM +0100, Boris Brezillon wrote:
> > > > > > > + * struct sun4i_dma_chan_config - DMA channel config
> > > > > > > + *
> > > > > > > + * @para: contains information about block size and
On Wed, Mar 09, 2016 at 12:06:27PM +0100, Boris Brezillon wrote:
> On Tue, 8 Mar 2016 08:25:47 +0530
> Vinod Koul wrote:
> >
> > Why does dmaengine need to wait? Can you explain that
>
> I don't have an answer for that one, but when I set WAIT_CYCLES to 1
> for the NAND
On Wed, Mar 09, 2016 at 11:14:34AM +0100, Boris Brezillon wrote:
> > > > > > + * struct sun4i_dma_chan_config - DMA channel config
> > > > > > + *
> > > > > > + * @para: contains information about block size and time before
> > > > > > checking
> > > > > > + * DRQ line. This is device specific
On Tue, 8 Mar 2016 08:25:47 +0530
Vinod Koul wrote:
>
> Why does dmaengine need to wait? Can you explain that
I don't have an answer for that one, but when I set WAIT_CYCLES to 1
for the NAND use case it does not work. So I guess it is somehow
related to how the DRQ line
On Tue, Mar 08, 2016 at 03:35:38PM +0530, Vinod Koul wrote:
> On Tue, Mar 08, 2016 at 09:42:31AM +0100, Hans de Goede wrote:
> >
> >
> > I see 2 possible reasons why waiting till checking for drq can help:
> >
> > 1) A lot of devices have an internal fifo hooked up to a single mmio data
> >
> >
> > It doesn't really makes sense to us, but it does have a significant
> > impact on the throughput.
>
> I wouldn't say significant impact, but tweaking those parameters has
> some impact on the performances, and since it's not that complicated to
> implement, I thought it was worth a try,
>>> Why does dmaengine need to wait? Can you explain that
[...]
> I see 2 possible reasons why waiting till checking for drq can help:
Any chance something similar is causing the "max 50MB/s" limit on SATA
transfers for A10/A20?
Stefan
--
You received this message because you are
On Tue, Mar 08, 2016 at 09:42:31AM +0100, Hans de Goede wrote:
>
>
> I see 2 possible reasons why waiting till checking for drq can help:
>
> 1) A lot of devices have an internal fifo hooked up to a single mmio data
> register which gets read using the general purpose dma-engine, it allows
>
On Tue, Mar 08, 2016 at 09:46:25AM +0100, Boris Brezillon wrote:
> On Tue, 8 Mar 2016 08:51:31 +0100
> Maxime Ripard wrote:
>
> > On Tue, Mar 08, 2016 at 08:25:47AM +0530, Vinod Koul wrote:
> > > On Mon, Mar 07, 2016 at 09:30:24PM +0100, Maxime Ripard wrote:
> >
On Tue, Mar 08, 2016 at 08:51:31AM +0100, Maxime Ripard wrote:
> > > > > > + * struct sun4i_dma_chan_config - DMA channel config
> > > > > > + *
> > > > > > + * @para: contains information about block size and time before
> > > > > > checking
> > > > > > + * DRQ line. This is device specific
On Tue, 2016-03-08 at 09:46 +0100, Boris Brezillon wrote:
> On Tue, 8 Mar 2016 08:51:31 +0100
> Maxime Ripard wrote:
>
> > On Tue, Mar 08, 2016 at 08:25:47AM +0530, Vinod Koul wrote:
> > > On Mon, Mar 07, 2016 at 09:30:24PM +0100, Maxime Ripard wrote:
> > > > On
On Tue, 8 Mar 2016 08:51:31 +0100
Maxime Ripard wrote:
> On Tue, Mar 08, 2016 at 08:25:47AM +0530, Vinod Koul wrote:
> > On Mon, Mar 07, 2016 at 09:30:24PM +0100, Maxime Ripard wrote:
> > > On Mon, Mar 07, 2016 at 04:08:57PM +0100, Boris Brezillon wrote:
> > > >
Hi,
On 08-03-16 08:51, Maxime Ripard wrote:
On Tue, Mar 08, 2016 at 08:25:47AM +0530, Vinod Koul wrote:
On Mon, Mar 07, 2016 at 09:30:24PM +0100, Maxime Ripard wrote:
On Mon, Mar 07, 2016 at 04:08:57PM +0100, Boris Brezillon wrote:
Hi Vinod,
On Mon, 7 Mar 2016 20:24:29 +0530
Vinod Koul
On Tue, Mar 08, 2016 at 08:25:47AM +0530, Vinod Koul wrote:
> On Mon, Mar 07, 2016 at 09:30:24PM +0100, Maxime Ripard wrote:
> > On Mon, Mar 07, 2016 at 04:08:57PM +0100, Boris Brezillon wrote:
Also just noticed the subsystem name on this is not correct, pls fix that in
subsequent posting
--
On Mon, Mar 07, 2016 at 09:30:24PM +0100, Maxime Ripard wrote:
> On Mon, Mar 07, 2016 at 04:08:57PM +0100, Boris Brezillon wrote:
> > Hi Vinod,
> >
> > On Mon, 7 Mar 2016 20:24:29 +0530
> > Vinod Koul wrote:
> >
> > > On Mon, Mar 07, 2016 at 10:59:31AM +0100, Boris
On Mon, Mar 07, 2016 at 04:08:57PM +0100, Boris Brezillon wrote:
> Hi Vinod,
>
> On Mon, 7 Mar 2016 20:24:29 +0530
> Vinod Koul wrote:
>
> > On Mon, Mar 07, 2016 at 10:59:31AM +0100, Boris Brezillon wrote:
> > > +/* Dedicated DMA parameter register layout */
> > > +#define
Hi Vinod,
On Mon, 7 Mar 2016 20:24:29 +0530
Vinod Koul wrote:
> On Mon, Mar 07, 2016 at 10:59:31AM +0100, Boris Brezillon wrote:
> > +/* Dedicated DMA parameter register layout */
> > +#define SUN4I_DDMA_PARA_DST_DATA_BLK_SIZE(n) (((n) - 1) << 24)
> > +#define
On Mon, Mar 07, 2016 at 10:59:31AM +0100, Boris Brezillon wrote:
> +/* Dedicated DMA parameter register layout */
> +#define SUN4I_DDMA_PARA_DST_DATA_BLK_SIZE(n) (((n) - 1) << 24)
> +#define SUN4I_DDMA_PARA_DST_WAIT_CYCLES(n) (((n) - 1) << 16)
> +#define SUN4I_DDMA_PARA_SRC_DATA_BLK_SIZE(n)
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