[linux-sunxi] Re: [PATCH RFC 09/15] ARM: dts: sun6i: sina31s: Switch to mmc3 for onboard eMMC

Hi, On 21-01-16 06:26, Chen-Yu Tsai wrote: According to Allwinner, only mmc3 supports 8 bit DDR transfers for eMMC. Switch to mmc3 for the onboard eMMC, and also assign vqmmc for signal voltage sensing/switching, and "cap-mmc-hw-reset" to denote this instance can use eMMC hardware reset. This

[linux-sunxi] Re: [PATCH RFC 09/15] ARM: dts: sun6i: sina31s: Switch to mmc3 for onboard eMMC

Hi, On 21-01-16 13:28, Chen-Yu Tsai wrote: On Thu, Jan 21, 2016 at 8:25 PM, Hans de Goede wrote: Hi, On 21-01-16 13:23, Chen-Yu Tsai wrote: On Thu, Jan 21, 2016 at 7:16 PM, Hans de Goede wrote: Hi, On 21-01-16 06:26, Chen-Yu Tsai wrote:

[linux-sunxi] Re: [PATCH RFC 05/15] mmc: sunxi: Support MMC_DDR52 timing modes

Hi, On 21-01-16 06:26, Chen-Yu Tsai wrote: DDR transfer modes include UHS-1 DDR50 and MMC HS-DDR (or MMC_DDR52). Consider MMC_DDR52 when setting clock delays. Signed-off-by: Chen-Yu Tsai --- drivers/mmc/host/sunxi-mmc.c | 6 -- 1 file changed, 4 insertions(+), 2

[linux-sunxi] Re: [PATCH RFC 05/15] mmc: sunxi: Support MMC_DDR52 timing modes

Hi, On 21-01-16 12:55, Chen-Yu Tsai wrote: On Thu, Jan 21, 2016 at 7:14 PM, Hans de Goede wrote: Hi, On 21-01-16 06:26, Chen-Yu Tsai wrote: DDR transfer modes include UHS-1 DDR50 and MMC HS-DDR (or MMC_DDR52). Consider MMC_DDR52 when setting clock delays.

[linux-sunxi] Re: [PATCH RFC 00/15] mmc: sunxi: Support vqmmc regulator and eMMC DDR modes

Hi, On 21-01-16 06:26, Chen-Yu Tsai wrote: Hi everyone, This series adds support for vqmmc regulator and eMMC DDR modes for sunxi-mmc. Allwinner's MMC controller supports eMMC 4.41 on earlier SoCs, and up to 5.0 on latest ones. UHS-1 modes are also supported by the hardware, but these are not

[linux-sunxi] Re: [PATCH RFC 09/15] ARM: dts: sun6i: sina31s: Switch to mmc3 for onboard eMMC

Hi, On 21-01-16 13:23, Chen-Yu Tsai wrote: On Thu, Jan 21, 2016 at 7:16 PM, Hans de Goede wrote: Hi, On 21-01-16 06:26, Chen-Yu Tsai wrote: According to Allwinner, only mmc3 supports 8 bit DDR transfers for eMMC. Switch to mmc3 for the onboard eMMC, and also assign

[linux-sunxi] Re: [PATCH RFC 09/15] ARM: dts: sun6i: sina31s: Switch to mmc3 for onboard eMMC

On Thu, Jan 21, 2016 at 7:16 PM, Hans de Goede wrote: > Hi, > > On 21-01-16 06:26, Chen-Yu Tsai wrote: >> >> According to Allwinner, only mmc3 supports 8 bit DDR transfers for eMMC. >> Switch to mmc3 for the onboard eMMC, and also assign vqmmc for signal >> voltage

[linux-sunxi] Re: [PATCH RFC 09/15] ARM: dts: sun6i: sina31s: Switch to mmc3 for onboard eMMC

On Thu, Jan 21, 2016 at 8:25 PM, Hans de Goede wrote: > Hi, > > On 21-01-16 13:23, Chen-Yu Tsai wrote: >> >> On Thu, Jan 21, 2016 at 7:16 PM, Hans de Goede >> wrote: >>> >>> Hi, >>> >>> On 21-01-16 06:26, Chen-Yu Tsai wrote: According to

Re: [linux-sunxi] Anyone tested BPi IR receiver under 4.4?

Hi, On 21-01-16 00:43, Dan MacDonald wrote: Hi Hans Thanks for your reply but I've not got much further. I don't have a /sys/class/ir but I do have /sys/class/lirc so maybe thats it? No I believe that that is wrong. > However, nowhere within there can I find a file containing protocol

[linux-sunxi] [PATCH RFC 15/15] ARM: dts: sun9i: cubieboard4: Enable hardware reset and HS-DDR for eMMC

mmc2 has a special pin for eMMC hardware reset, which is controllable from the controller. Add the "mmc-cap-hw-reset" property to denote that this controller supports this function, and the pins are actually used. Also increase the signal drive strength for mmc2 pins, for HS-DDR mode support.

[linux-sunxi] [PATCH RFC 14/15] ARM: dts: sun9i: a80-optimus: Enable hardware reset and HS-DDR for eMMC

mmc2 has a special pin for eMMC hardware reset, which is controllable from the controller. Add the "mmc-cap-hw-reset" property to denote that this controller supports this function, and the pins are actually used. Also increase the signal drive strength for mmc2 pins, for HS-DDR mode support.

[linux-sunxi] basic Pine64 Linux 4.4 image

Hi, I used the existing Android image for the Pine64 to hack the crippled U-Boot to boot my own kernels (and DTs and rootfs'). Kindly find the first result here: https://github.com/apritzel/pine64 It is still a giant hack, but a better start than the existing images for people who want to

[linux-sunxi] [PATCH RFC 02/15] mmc: sunxi: Return error on mmc_regulator_set_ocr() fail in .set_ios op

Let .set_ios() fail if mmc_regulator_set_ocr() fails to enable and set a proper voltage for vmmc. Signed-off-by: Chen-Yu Tsai --- drivers/mmc/host/sunxi-mmc.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sunxi-mmc.c

[linux-sunxi] [PATCH RFC 11/15] ARM: dts: sun8i: sina33: Enable hardware reset and HS-DDR for eMMC

mmc2 has a special pin for eMMC hardware reset, which is controllable from the controller. Add the "mmc-cap-hw-reset" property to denote that this controller supports this function, and the pins are actually used. Also increase the signal drive strength for mmc2 pins, for HS-DDR mode support.

[linux-sunxi] [PATCH RFC 00/15] mmc: sunxi: Support vqmmc regulator and eMMC DDR modes

Hi everyone, This series adds support for vqmmc regulator and eMMC DDR modes for sunxi-mmc. Allwinner's MMC controller supports eMMC 4.41 on earlier SoCs, and up to 5.0 on latest ones. UHS-1 modes are also supported by the hardware, but these are not covered in this series, as no boards have

[linux-sunxi] [PATCH RFC 07/15] mmc: sunxi: Enable eMMC HS-DDR (MMC_CAP_1_8V_DDR) support

Now that clock delay settings for 8 bit DDR are correct, and vqmmc support is available, we can enable MMC_CAP_1_8V_DDR support. This enables MMC HS-DDR at up to 52 MHz, even if signal voltage switching is not available. Signed-off-by: Chen-Yu Tsai ---

[linux-sunxi] [PATCH RFC 12/15] ARM: dts: sun9i: Use sun9i specific mmc compatible

sun9i/A80 MMC controllers have a larger FIFO, and the FIFO DMA trigger levels can be increased. Also, the mmc module clock parent has a higher clock rate, and the sample and output delay phases are different. Signed-off-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun9i-a80.dtsi | 8

[linux-sunxi] [PATCH RFC 03/15] mmc: sunxi: Block signal voltage switching (CMD11)

Allwinner's mmc controller supports signal voltage switching. This is supported in code in Allwinner's kernel. However, publicly available boards all tie it to a fixed 3.0/3.3V regulator, with options to tie it to 1.8V for eMMC on some. Since Allwinner's kernel is an ancient 3.4, it is hard to

[linux-sunxi] [PATCH RFC 01/15] mmc: sunxi: Document host init sequence

sunxi_mmc_init_host() originated from Allwinner kernel sources. The magic numbers written to various registers was never documented. Add comments for values found in Allwinner user manuals. Signed-off-by: Chen-Yu Tsai --- drivers/mmc/host/sunxi-mmc.c | 12 1 file

[linux-sunxi] [PATCH RFC 10/15] ARM: dts: sun8i: Include SDC2_RST pin in mmc2_8bit_pins

mmc2_8bit_pins is used with eMMC chips, which also have a reset pin. The MMC controller also has a reset output that is supported. Signed-off-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun8i-a23-a33.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

[linux-sunxi] [PATCH RFC 06/15] mmc: sunxi: Support 8 bit eMMC DDR transfer modes

Allwinner's MMC controller needs to run at double the card clock rate for 8 bit DDR transfer modes. Interestingly, this is not needed for 4 bit DDR transfers. Different clock delays are needed for 8 bit eMMC DDR, due to the increased module clock rate. For the A80 though, the same values for 4

[linux-sunxi] [PATCH RFC 08/15] ARM: dts: sun6i: Add mmc3 pins for 8 bit emmc

mmc2 and mmc3 are available on the same pins, with different mux values. However, only mmc3 supports 8 bit DDR transfer modes. Since preference for mmc3 over mmc2 is due to DDR transfer modes, just set the drive strength to 40mA, which is needed for DDR. This pinmux setting also includes the

[linux-sunxi] [PATCH RFC 13/15] ARM: dts: sun9i: Include SDC2_RST pin in mmc2_8bit_pins

mmc2_8bit_pins is used with eMMC chips, which also have a reset pin. The MMC controller also has a reset output that is supported. Signed-off-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun9i-a80.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git

[linux-sunxi] Re: [PATCH 1/4] sunxi: Support Secure Memory Touch Arbiter (SMTA) in sun8i H3

Hi, On 01/06/2016 08:13 AM, Chen-Yu Tsai wrote: Secure Memory Touch Arbiter is the same thing as the TrustZone Protection Controller found on A31/A31s. Access to many peripherals on the H3 can be controlled by the SMTA, and the settings default to secure access only. This patch supports the

[linux-sunxi] Re: [PATCH 0/4] sunxi: PSCI support for H3

Hi, On 01/06/2016 08:13 AM, Chen-Yu Tsai wrote: Hi everyone, This series enables PSCI support for the H3. Like other Allwinner SoCs, the implementation only supports PSCI 0.1, specifically only secondary CPU boot/hotplug. Patch 1 supports the SMTA (previously called TZPC) TrustZone hardware

Re: [linux-sunxi] Anyone tested BPi IR receiver under 4.4?

Thanks for explaining that Code Kipper! With your help I have been able to get IR (mostly) working under 4.4.0 so I have updated my 'Remote controlled BananaPi music alarm clock' guide here with the details on how I bring up IR at boot under Arch:

Re: [linux-sunxi] A64, arisc, SCPI and regulator handling

Hi, On Fri, Jan 22, 2016 at 9:23 AM, Siarhei Siamashka wrote: > On Thu, 21 Jan 2016 21:38:39 +0100 > Karsten Merker wrote: > >> Hello everybody, >> >> I have read today's IRC discussion about handling the regulator >> control on the A64 via the

Re: [linux-sunxi] A64, arisc, SCPI and regulator handling

On Thu, 21 Jan 2016 21:38:39 +0100 Karsten Merker wrote: > Hello everybody, > > I have read today's IRC discussion about handling the regulator > control on the A64 via the SCPI protocol implemented by a > firmware running on the "arisc"/AR100 (OpenRisc Core) embedded in >