Re: [linux-sunxi] [PATCH 1/2] sunxi: add PRCM secure switch register definition

[icenowy]

在 2017-08-09 11:46，Chen-Yu Tsai 写道：

On Tue, Aug 8, 2017 at 2:46 PM,   wrote:

在 2017-08-08 12:13，Chen-Yu Tsai 写道：


On Thu, Jul 20, 2017 at 2:00 PM, Icenowy Zheng  
wrote:


Some new Allwinner SoCs' PRCM has a secure switch register, which
controls the access to some clock and power registers in PRCM block.

Add the definition of this register and its bits in the PRCM header
file.

Signed-off-by: Icenowy Zheng 



Could you provide a reference as to where or how you found out
about this?



https://github.com/tinalinux/brandy/blob/r18-v0.9/arm-trusted-firmware-1.0/plat/sun50iw1p1/sunxi_security.c#L105


I assume you've mapped out what each bit means by testing it?


Yes.

Toggling bit 0 will make at least 0x0 (CPUS_CFG_REG) inaccessible.
Toggling bit 1 will make at least 0x40 and 0x44 (PLL_CTRL_REG{0,1})
inaccessible.
Toggling bit 2 will make at least 0x120 (VDD_SYS_PWR_RST)
inaccessible.

(The register names are from http://linux-sunxi.org/PRCM )



Tested-by: Chen-Yu Tsai 


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[linux-sunxi] Re: [PATCH 2/2] sunxi: switch PRCM to non-secure on H3/H5 SoCs

[Chen-Yu Tsai]

On Thu, Jul 27, 2017 at 3:31 AM, Maxime Ripard
 wrote:
> On Wed, Jul 26, 2017 at 07:55:24PM +0800, icen...@aosc.io wrote:
>> 在 2017-07-20 14:00，Icenowy Zheng 写道：
>> > The PRCM of H3/H5 SoCs have a secure/non-secure switch, which controls
>> > the access to some clock/power related registers in PRCM.
>> >
>> > Current Linux kernel will access the CPUS (AR100) clock in the PRCM
>> > block, so the PRCM should be switched to non-secure.
>> >
>> > Add code to switch the PRCM to non-secure.
>>
>> Ping.
>>
>> Maxime and Jagan, can you merge this patchset?
>>
>> This is necessary for R_CCU to work properly on H3.
>
> Acked-by: Maxime Ripard 

Tested-by: Chen-Yu Tsai 

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[linux-sunxi] Re: [PATCH 1/8] dt-bindings: phy: sun4i-usb-phy: Add property descriptions for H3

['Kishon Vijay Abraham I' via linux-sunxi]

On Thursday 03 August 2017 01:44 PM, Chen-Yu Tsai wrote:
> The Allwinner H3 SoC has 4 USB PHYs, so it needs four sets of pmu
> regions, clocks, resets, and optional vbus properties. These were
> not described when the H3 compatible string was added.
> 
> Fixes: 626a630e003c ("phy-sun4i-usb: Add support for the host usb-phys
> found on the H3 SoC")
> Signed-off-by: Chen-Yu Tsai 

Rob, can you give your Acked-by for this patch?

Thanks
Kishon
> ---
>  Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt | 8 ++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt 
> b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
> index 005bc22938ff..893dd01dfe64 100644
> --- a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
> +++ b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
> @@ -17,18 +17,21 @@ Required properties:
>* "phy_ctrl"
>* "pmu0" for H3, V3s and A64
>* "pmu1"
> -  * "pmu2" for sun4i, sun6i or sun7i
> +  * "pmu2" for sun4i, sun6i, sun7i or sun8i-h3
> +  * "pmu3" for sun8i-h3
>  - #phy-cells : from the generic phy bindings, must be 1
>  - clocks : phandle + clock specifier for the phy clocks
>  - clock-names :
>* "usb_phy" for sun4i, sun5i or sun7i
>* "usb0_phy", "usb1_phy" and "usb2_phy" for sun6i
>* "usb0_phy", "usb1_phy" for sun8i
> +  * "usb0_phy", "usb1_phy", "usb2_phy" and "usb3_phy" for sun8i-h3
>  - resets : a list of phandle + reset specifier pairs
>  - reset-names :
>* "usb0_reset"
>* "usb1_reset"
> -  * "usb2_reset" for sun4i, sun6i or sun7i
> +  * "usb2_reset" for sun4i, sun6i, sun7i or sun8i-h3
> +  * "usb3_reset" for sun8i-h3
>  
>  Optional properties:
>  - usb0_id_det-gpios : gpio phandle for reading the otg id pin value
> @@ -37,6 +40,7 @@ Optional properties:
>  - usb0_vbus-supply : regulator phandle for controller usb0 vbus
>  - usb1_vbus-supply : regulator phandle for controller usb1 vbus
>  - usb2_vbus-supply : regulator phandle for controller usb2 vbus
> +- usb3_vbus-supply : regulator phandle for controller usb3 vbus
>  
>  Example:
>   usbphy: phy@0x01c13400 {
> 

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[linux-sunxi] Re: [PATCH v3 1/5] dt-bindings: update the Allwinner GPADC device tree binding for H3

[Lee Jones]

On Sun, 23 Jul 2017, Icenowy Zheng wrote:

> Allwinner H3 features a thermal sensor like the one in A33, but has its
> register re-arranged, the clock divider moved to CCU (originally the
> clock divider is in ADC) and added a pair of bus clock and reset.
> 
> Update the binding document to cover H3.
> 
> Signed-off-by: Icenowy Zheng 
> ---
> Changes in v3:
> - Clock name changes.
> - Example node name changes.
> - Add interupts (not yet used by the driver).
> 
>  .../devicetree/bindings/mfd/sun4i-gpadc.txt| 25 
> --
>  1 file changed, 23 insertions(+), 2 deletions(-)

For my own reference:
  Acked-for-MFD-by: Lee Jones 

-- 
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Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog

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[linux-sunxi] Re: [PATCH v2] mmc: sunxi: fix support for new timings mode only SoCs

[Ulf Hansson]

On 8 August 2017 at 09:09, Icenowy Zheng  wrote:
> The A83T MMC support code introduces the timings mode switch, however
> such a switch doesn't exist on new SoCs with only new timings mode.
>
> Only execute the switch if the SoC really have the timings mode switch,
> to fix the regression shown on new timings mode only SoCs (A64, H5,
> etc).
>
> Fixes: b0600daebf31 ("mmc: sunxi: Support controllers that can use
>   both old and new timings")
> Signed-off-by: Icenowy Zheng 
> Reviewed-by: Chen-Yu Tsai 

Thanks, applied for next!

Kind regards
Uffe

> ---
> Changes in v2:
> - Slightly adjusted the format of the Fixes: line/
> - Added review tag from Chen-Yu.
>
>  drivers/mmc/host/sunxi-mmc.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
> index 020547e5fa45..7447d41833ee 100644
> --- a/drivers/mmc/host/sunxi-mmc.c
> +++ b/drivers/mmc/host/sunxi-mmc.c
> @@ -789,7 +789,7 @@ static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host 
> *host,
> clock <<= 1;
> }
>
> -   if (host->use_new_timings) {
> +   if (host->use_new_timings && host->cfg->has_timings_switch) {
> ret = sunxi_ccu_set_mmc_timing_mode(host->clk_mmc, true);
> if (ret) {
> dev_err(mmc_dev(mmc),
> --
> 2.13.0
>

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[linux-sunxi] Re: [PATCH v2] mmc: sunxi: Fix NULL pointer reference on clk_delays

[Ulf Hansson]

On 8 August 2017 at 09:02, Chen-Yu Tsai  wrote:
> Some SoCs do not support clk delays for MMC in the clock control unit.
> These include the old controllers in A10/A10s/A13/R8, and the new eMMC
> controller in A64. The config structure for these controllers do not
> specify clk_delays, but the check for this was replaced in commit
> b0600daebf31 ("mmc: sunxi: Support controllers that can use both old
> and new timings").
>
> This patch adds back the check for clk_delays, and also adds comments
> for both checks in sunxi_mmc_clk_set_phase().
>
> Fixes: b0600daebf31 ("mmc: sunxi: Support controllers that can use
>   both old and new timings")
> Signed-off-by: Chen-Yu Tsai 

Thanks, applied for next!

Kind regards
Uffe

> ---
> This fixes an mmc regression on A10/A10s/A13/R8 and A64 introduced
> by the A83T mmc patches.
>
> v1 was inlined in a reply to "mmc: sunxi: fix new timings mode on A64
> EMMC (MMC2) controller"
>
> Changes since v1:
>
>   - Polished comments
>
> I've tested this on my A10 Cubieboard and A20 Cubieboard2.
> ---
>  drivers/mmc/host/sunxi-mmc.c | 5 +
>  1 file changed, 5 insertions(+)
>
> diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
> index 3777517982dd..9dc6d726ec49 100644
> --- a/drivers/mmc/host/sunxi-mmc.c
> +++ b/drivers/mmc/host/sunxi-mmc.c
> @@ -722,9 +722,14 @@ static int sunxi_mmc_clk_set_phase(struct sunxi_mmc_host 
> *host,
>  {
> int index;
>
> +   /* clk controller delays not used under new timings mode */
> if (host->use_new_timings)
> return 0;
>
> +   /* some old controllers don't support delays */
> +   if (!host->cfg->clk_delays)
> +   return 0;
> +
> /* determine delays */
> if (rate <= 40) {
> index = SDXC_CLK_400K;
> --
> 2.13.3
>

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Re: [linux-sunxi] Re: [PATCH v2] mmc: sunxi: Fix NULL pointer reference on clk_delays

[icenowy]

在 2017-08-08 15:10，Chen-Yu Tsai 写道：

On Tue, Aug 8, 2017 at 3:07 PM,   wrote:

在 2017-08-08 15:02，Chen-Yu Tsai 写道：


Some SoCs do not support clk delays for MMC in the clock control 
unit.
These include the old controllers in A10/A10s/A13/R8, and the new 
eMMC

controller in A64. The config structure for these controllers do not
specify clk_delays, but the check for this was replaced in commit
b0600daebf31 ("mmc: sunxi: Support controllers that can use both old
and new timings").

This patch adds back the check for clk_delays, and also adds comments
for both checks in sunxi_mmc_clk_set_phase().

Fixes: b0600daebf31 ("mmc: sunxi: Support controllers that can use
  both old and new timings")
Signed-off-by: Chen-Yu Tsai 



Should I add a Tested-by here?


If you tested it, then yes. :)


I tested it on A64 MMC2.

So:

Tested-by: Icenowy Zheng 



ChenYu


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Re: [linux-sunxi] Re: [PATCH v2] mmc: sunxi: Fix NULL pointer reference on clk_delays

[Chen-Yu Tsai]

On Tue, Aug 8, 2017 at 3:07 PM,   wrote:
> 在 2017-08-08 15:02，Chen-Yu Tsai 写道：
>>
>> Some SoCs do not support clk delays for MMC in the clock control unit.
>> These include the old controllers in A10/A10s/A13/R8, and the new eMMC
>> controller in A64. The config structure for these controllers do not
>> specify clk_delays, but the check for this was replaced in commit
>> b0600daebf31 ("mmc: sunxi: Support controllers that can use both old
>> and new timings").
>>
>> This patch adds back the check for clk_delays, and also adds comments
>> for both checks in sunxi_mmc_clk_set_phase().
>>
>> Fixes: b0600daebf31 ("mmc: sunxi: Support controllers that can use
>>   both old and new timings")
>> Signed-off-by: Chen-Yu Tsai 
>
>
> Should I add a Tested-by here?

If you tested it, then yes. :)

ChenYu

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[linux-sunxi] [PATCH v2] mmc: sunxi: fix support for new timings mode only SoCs

[Icenowy Zheng]

The A83T MMC support code introduces the timings mode switch, however
such a switch doesn't exist on new SoCs with only new timings mode.

Only execute the switch if the SoC really have the timings mode switch,
to fix the regression shown on new timings mode only SoCs (A64, H5,
etc).

Fixes: b0600daebf31 ("mmc: sunxi: Support controllers that can use
  both old and new timings")
Signed-off-by: Icenowy Zheng 
Reviewed-by: Chen-Yu Tsai 
---
Changes in v2:
- Slightly adjusted the format of the Fixes: line/
- Added review tag from Chen-Yu.

 drivers/mmc/host/sunxi-mmc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
index 020547e5fa45..7447d41833ee 100644
--- a/drivers/mmc/host/sunxi-mmc.c
+++ b/drivers/mmc/host/sunxi-mmc.c
@@ -789,7 +789,7 @@ static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host 
*host,
clock <<= 1;
}
 
-   if (host->use_new_timings) {
+   if (host->use_new_timings && host->cfg->has_timings_switch) {
ret = sunxi_ccu_set_mmc_timing_mode(host->clk_mmc, true);
if (ret) {
dev_err(mmc_dev(mmc),
-- 
2.13.0

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[linux-sunxi] Re: [PATCH v2] mmc: sunxi: Fix NULL pointer reference on clk_delays

[icenowy]

在 2017-08-08 15:02，Chen-Yu Tsai 写道：

Some SoCs do not support clk delays for MMC in the clock control unit.
These include the old controllers in A10/A10s/A13/R8, and the new eMMC
controller in A64. The config structure for these controllers do not
specify clk_delays, but the check for this was replaced in commit
b0600daebf31 ("mmc: sunxi: Support controllers that can use both old
and new timings").

This patch adds back the check for clk_delays, and also adds comments
for both checks in sunxi_mmc_clk_set_phase().

Fixes: b0600daebf31 ("mmc: sunxi: Support controllers that can use
  both old and new timings")
Signed-off-by: Chen-Yu Tsai 


Should I add a Tested-by here?


---
This fixes an mmc regression on A10/A10s/A13/R8 and A64 introduced
by the A83T mmc patches.

v1 was inlined in a reply to "mmc: sunxi: fix new timings mode on A64
EMMC (MMC2) controller"

Changes since v1:

  - Polished comments

I've tested this on my A10 Cubieboard and A20 Cubieboard2.
---
 drivers/mmc/host/sunxi-mmc.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/mmc/host/sunxi-mmc.c 
b/drivers/mmc/host/sunxi-mmc.c

index 3777517982dd..9dc6d726ec49 100644
--- a/drivers/mmc/host/sunxi-mmc.c
+++ b/drivers/mmc/host/sunxi-mmc.c
@@ -722,9 +722,14 @@ static int sunxi_mmc_clk_set_phase(struct
sunxi_mmc_host *host,
 {
int index;

+   /* clk controller delays not used under new timings mode */
if (host->use_new_timings)
return 0;

+   /* some old controllers don't support delays */
+   if (!host->cfg->clk_delays)
+   return 0;
+
/* determine delays */
if (rate <= 40) {
index = SDXC_CLK_400K;


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[linux-sunxi] [PATCH v2] mmc: sunxi: Fix NULL pointer reference on clk_delays

[Chen-Yu Tsai]

Some SoCs do not support clk delays for MMC in the clock control unit.
These include the old controllers in A10/A10s/A13/R8, and the new eMMC
controller in A64. The config structure for these controllers do not
specify clk_delays, but the check for this was replaced in commit
b0600daebf31 ("mmc: sunxi: Support controllers that can use both old
and new timings").

This patch adds back the check for clk_delays, and also adds comments
for both checks in sunxi_mmc_clk_set_phase().

Fixes: b0600daebf31 ("mmc: sunxi: Support controllers that can use
  both old and new timings")
Signed-off-by: Chen-Yu Tsai 
---
This fixes an mmc regression on A10/A10s/A13/R8 and A64 introduced
by the A83T mmc patches.

v1 was inlined in a reply to "mmc: sunxi: fix new timings mode on A64
EMMC (MMC2) controller"

Changes since v1:

  - Polished comments 

I've tested this on my A10 Cubieboard and A20 Cubieboard2.
---
 drivers/mmc/host/sunxi-mmc.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
index 3777517982dd..9dc6d726ec49 100644
--- a/drivers/mmc/host/sunxi-mmc.c
+++ b/drivers/mmc/host/sunxi-mmc.c
@@ -722,9 +722,14 @@ static int sunxi_mmc_clk_set_phase(struct sunxi_mmc_host 
*host,
 {
int index;
 
+   /* clk controller delays not used under new timings mode */
if (host->use_new_timings)
return 0;
 
+   /* some old controllers don't support delays */
+   if (!host->cfg->clk_delays)
+   return 0;
+
/* determine delays */
if (rate <= 40) {
index = SDXC_CLK_400K;
-- 
2.13.3

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Re: [linux-sunxi] [PATCH 1/2] sunxi: add PRCM secure switch register definition

[icenowy]

在 2017-08-08 12:13，Chen-Yu Tsai 写道：

On Thu, Jul 20, 2017 at 2:00 PM, Icenowy Zheng  wrote:

Some new Allwinner SoCs' PRCM has a secure switch register, which
controls the access to some clock and power registers in PRCM block.

Add the definition of this register and its bits in the PRCM header
file.

Signed-off-by: Icenowy Zheng 


Could you provide a reference as to where or how you found out
about this?


https://github.com/tinalinux/brandy/blob/r18-v0.9/arm-trusted-firmware-1.0/plat/sun50iw1p1/sunxi_security.c#L105



Thanks
ChenYu


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