Hi All,
I am working on one of our product in which All winner A20 chip and Android
Platform 4.4 with Linux Kernel 3.4 are used.
We are streaming video over Ethernet with 100 Mbps speed on A20 as client
and server running on some other device.
I am getting appropriate video stream without any
Quoting Maxime Ripard (2016-06-28 13:45:02)
> What's the point of this, if we're not using (or exposing for that
> matter) any of it?
>
> I'm sorry, but the whole point of the initial serie was to rework and
> simplify things, precisely because dealing with the clk_factors code
> was just too diff
On Sat, Jun 25, 2016 at 05:45:00AM +0200, meg...@megous.com wrote:
> From: Ondrej Jirman
>
> This patch adds the binding documentation for the
> sun8i_ths driver. This is a driver for thermal sensor
> found in Allwinner H3 SoC.
>
> Signed-off-by: Ondřej Jirman
> ---
> .../devicetree/bindings/t
On Tue, Jun 28, 2016 at 05:37:35PM +0200, Jean-Francois Moine wrote:
> +/* --- prepare / enable --- */
> +int ccu_prepare(struct clk_hw *hw)
> +{
> + struct ccu *ccu = hw2ccu(hw);
> +
> + if (!ccu->reset_reg && !ccu->bus_reg)
> + return 0;
> +
> +#if CCU_DEBUG
> + pr_info("*
On 28.6.2016 17:37, Jean-Francois Moine wrote:
> Most of the clocks in the Allwinner's SoCs are configured in the CCU
> (Clock Configuration Unit).
>
> The PLL clocks are driven from the main clock. Their rates are controlled
> by a set of multiply and divide factors, named from the Allwinner's
>
Change the clock definition using the CCU.
Signed-off-by: Jean-Francois Moine
---
Documentation/devicetree/bindings/clock/sunxi.txt | 7 ---
arch/arm/boot/dts/sun8i-a83t.dtsi | 16
2 files changed, 16 insertions(+), 7 deletions(-)
diff --git a/Documentation
Most of the clocks in the Allwinner's SoCs are configured in the CCU
(Clock Configuration Unit).
The PLL clocks are driven from the main clock. Their rates are controlled
by a set of multiply and divide factors, named from the Allwinner's
documentation:
- multipliers: 'n' and 'k'
- dividers: 'd1',
Define the CCU clocks of the Allwinner's A83T Soc.
Signed-off-by: Jean-Francois Moine
---
drivers/clk/sunxi/Makefile | 1 +
drivers/clk/sunxi/ccu-sun8i-a83t.c | 858 +
include/dt-bindings/clock/sun8i-a83t.h | 97
include/dt-bindings/reset/s
The 'sunxi-ng' proposal from Maxime Ripard did a great advance in
handling the clocks of Allwinner's SoCs, but it appeared that it
was not easy to extend its functions and handle some other SoCs as
the A83T.
This patch series proposes a more flexible and simpler structure.
The basic idea is to hav
Hi,
if anyone wants to play with the OTG port support on Orange Pi PC, you
can try these patches:
https://files.megous.com/orange-pi-dvfs/linux-4.7-OrangePI/usb-otg/
I don't have much time to test it extensively, but it seems to work.
I'm not yet submitting them "formally". This is just a heads
On 27.6.2016 16:54, Mark Brown wrote:
> On Sun, Jun 26, 2016 at 05:07:16PM +0200, Ondřej Jirman wrote:
>> On 26.6.2016 13:26, Mark Brown wrote:
>
>>> I'm missing almost all of this series, I've just got this and another
>>> patch which look like a standalone driver so it's hard to see any
>>> depe
Hi,
On Sat, Jun 25, 2016 at 05:23:12PM +0200, Ondřej Jirman wrote:
> Hi Maxime,
>
> I try to base everything on the torvalds's kernel.
>
> I did notice the patches. Is there some main git tree/branch where this
> work is tracked in? I'd gladly use it.
I just pushed it, branch sunxi/pen/clk-rewo
On Sat, Jun 25, 2016 at 05:12:41PM +0200, Ondřej Jirman wrote:
> >> + data->calreg = devm_ioremap_resource(&pdev->dev, res);
> >> + if (IS_ERR(data->calreg)) {
> >> + ret = PTR_ERR(data->calreg);
> >> + dev_err(&pdev->dev, "failed to ioremap THS registers: %d\n",
> >> ret);
> >
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