Re: [linux-sunxi] [PATCH 1/2] sunxi: add PRCM secure switch register definition

在 2017-08-09 11:46，Chen-Yu Tsai 写道： On Tue, Aug 8, 2017 at 2:46 PM, wrote: 在 2017-08-08 12:13，Chen-Yu Tsai 写道： On Thu, Jul 20, 2017 at 2:00 PM, Icenowy Zheng wrote: Some new Allwinner SoCs' PRCM has a secure switch register, which controls the access to

[linux-sunxi] Re: [PATCH 2/2] sunxi: switch PRCM to non-secure on H3/H5 SoCs

On Thu, Jul 27, 2017 at 3:31 AM, Maxime Ripard wrote: > On Wed, Jul 26, 2017 at 07:55:24PM +0800, icen...@aosc.io wrote: >> 在 2017-07-20 14:00，Icenowy Zheng 写道： >> > The PRCM of H3/H5 SoCs have a secure/non-secure switch, which controls >> > the access to some

[linux-sunxi] Re: [PATCH 1/8] dt-bindings: phy: sun4i-usb-phy: Add property descriptions for H3

On Thursday 03 August 2017 01:44 PM, Chen-Yu Tsai wrote: > The Allwinner H3 SoC has 4 USB PHYs, so it needs four sets of pmu > regions, clocks, resets, and optional vbus properties. These were > not described when the H3 compatible string was added. > > Fixes: 626a630e003c ("phy-sun4i-usb: Add

[linux-sunxi] Re: [PATCH v3 1/5] dt-bindings: update the Allwinner GPADC device tree binding for H3

On Sun, 23 Jul 2017, Icenowy Zheng wrote: > Allwinner H3 features a thermal sensor like the one in A33, but has its > register re-arranged, the clock divider moved to CCU (originally the > clock divider is in ADC) and added a pair of bus clock and reset. > > Update the binding document to cover

[linux-sunxi] Re: [PATCH v2] mmc: sunxi: fix support for new timings mode only SoCs

On 8 August 2017 at 09:09, Icenowy Zheng wrote: > The A83T MMC support code introduces the timings mode switch, however > such a switch doesn't exist on new SoCs with only new timings mode. > > Only execute the switch if the SoC really have the timings mode switch, > to fix the

[linux-sunxi] Re: [PATCH v2] mmc: sunxi: Fix NULL pointer reference on clk_delays

On 8 August 2017 at 09:02, Chen-Yu Tsai wrote: > Some SoCs do not support clk delays for MMC in the clock control unit. > These include the old controllers in A10/A10s/A13/R8, and the new eMMC > controller in A64. The config structure for these controllers do not > specify

Re: [linux-sunxi] Re: [PATCH v2] mmc: sunxi: Fix NULL pointer reference on clk_delays

在 2017-08-08 15:10，Chen-Yu Tsai 写道： On Tue, Aug 8, 2017 at 3:07 PM, wrote: 在 2017-08-08 15:02，Chen-Yu Tsai 写道： Some SoCs do not support clk delays for MMC in the clock control unit. These include the old controllers in A10/A10s/A13/R8, and the new eMMC controller in A64.

Re: [linux-sunxi] Re: [PATCH v2] mmc: sunxi: Fix NULL pointer reference on clk_delays

On Tue, Aug 8, 2017 at 3:07 PM, wrote: > 在 2017-08-08 15:02，Chen-Yu Tsai 写道： >> >> Some SoCs do not support clk delays for MMC in the clock control unit. >> These include the old controllers in A10/A10s/A13/R8, and the new eMMC >> controller in A64. The config structure for

[linux-sunxi] [PATCH v2] mmc: sunxi: fix support for new timings mode only SoCs

The A83T MMC support code introduces the timings mode switch, however such a switch doesn't exist on new SoCs with only new timings mode. Only execute the switch if the SoC really have the timings mode switch, to fix the regression shown on new timings mode only SoCs (A64, H5, etc). Fixes:

[linux-sunxi] Re: [PATCH v2] mmc: sunxi: Fix NULL pointer reference on clk_delays

在 2017-08-08 15:02，Chen-Yu Tsai 写道： Some SoCs do not support clk delays for MMC in the clock control unit. These include the old controllers in A10/A10s/A13/R8, and the new eMMC controller in A64. The config structure for these controllers do not specify clk_delays, but the check for this was

[linux-sunxi] [PATCH v2] mmc: sunxi: Fix NULL pointer reference on clk_delays

Some SoCs do not support clk delays for MMC in the clock control unit. These include the old controllers in A10/A10s/A13/R8, and the new eMMC controller in A64. The config structure for these controllers do not specify clk_delays, but the check for this was replaced in commit b0600daebf31 ("mmc:

Re: [linux-sunxi] [PATCH 1/2] sunxi: add PRCM secure switch register definition

在 2017-08-08 12:13，Chen-Yu Tsai 写道： On Thu, Jul 20, 2017 at 2:00 PM, Icenowy Zheng wrote: Some new Allwinner SoCs' PRCM has a secure switch register, which controls the access to some clock and power registers in PRCM block. Add the definition of this register and its bits in