[linux-sunxi] SID write

2018-02-13 Thread Petr Malanik 
Hi,
I need to write some data into SID on a83t. I managed to successfully write 
data.
Now I'm using OEM_PROGRAM or DEBUG [1].

But have you any suggestion which parts of SID I could use without any future 
problems?
Regards,
Petr

[1] http://linux-sunxi.org/SID_Register_Guide#SID_RDKEY

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[linux-sunxi] Re: [PATCH v4 06/12] dt-bindings: display: sun4i-drm: Add A83T HDMI pipeline

2018-02-13 Thread Rob Herring 
On Wed, Feb 07, 2018 at 10:17:07PM +0100, Jernej Skrabec wrote:
> This commit adds all necessary compatibles and descriptions needed to
> implement A83T HDMI pipeline.
> 
> Mixer is already properly described, so only compatible is added.
> 
> However, A83T TV TCON, which is connected to HDMI, doesn't have channel 0,
> contrary to all TCONs currently described. Because of that, TCON
> documentation is extended.
> 
> A83T features Synopsys DW HDMI controller with a custom PHY which looks
> like Synopsys Gen2 PHY with few additions. Since there is no
> documentation, needed properties were found out through experimentation
> and reading BSP code.
> 
> At the end, example is added for newer SoCs, which feature DE2 and DW
> HDMI.
> 
> Signed-off-by: Jernej Skrabec 
> ---
>  .../bindings/display/sunxi/sun4i-drm.txt   | 195 
> -
>  1 file changed, 188 insertions(+), 7 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt 
> b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
> index cd626ee1147a..db3d3adb1059 100644
> --- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
> +++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
> @@ -64,6 +64,52 @@ Required properties:
>  first port should be the input endpoint. The second should be the
>  output, usually to an HDMI connector.
>  
> +DWC HDMI TX Encoder
> +---
> +
> +The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
> +with Allwinner's own PHY IP. It supports audio and video outputs and CEC.
> +
> +These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
> +Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the
> +following device-specific properties.
> +
> +Required properties:
> +
> +  - compatible: value must be one of:
> +* "allwinner,sun8i-a83t-dw-hdmi"
> +  - reg: base address and size of memory-mapped region
> +  - reg-io-width: See dw_hdmi.txt. Shall be 1.
> +  - interrupts: HDMI interrupt number
> +  - clocks: phandles to the clocks feeding the HDMI encoder
> +* iahb: the HDMI bus clock
> +* isfr: the HDMI register clock
> +* tmds: TMDS clock
> +  - clock-names: the clock names mentioned above
> +  - resets: phandle to the reset controller
> +  - reset-names: must be "ctrl"
> +  - phys: phandle to the DWC HDMI PHY
> +  - phy-names: must be "phy"
> +
> +  - ports: A ports node with endpoint definitions as defined in
> +Documentation/devicetree/bindings/media/video-interfaces.txt. The
> +first port should be the input endpoint. The second should be the
> +output, usually to an HDMI connector.
> +
> +DWC HDMI PHY
> +
> +
> +Required properties:
> +  - compatible: value must be one of:
> +* allwinner,sun8i-a83t-hdmi-phy
> +  - reg: base address and size of memory-mapped region
> +  - clocks: phandles to the clocks feeding the HDMI PHY
> +* bus: the HDMI PHY interface clock
> +* mod: the HDMI PHY module clock
> +  - clock-names: the clock names mentioned above
> +  - resets: phandle to the reset controller driving the PHY
> +  - reset-names: must be "phy"
> +
>  TV Encoder
>  --
>  
> @@ -94,24 +140,26 @@ Required properties:
> * allwinner,sun7i-a20-tcon
> * allwinner,sun8i-a33-tcon
> * allwinner,sun8i-a83t-tcon-lcd
> +   * allwinner,sun8i-a83t-tcon-tv
> * allwinner,sun8i-v3s-tcon
>   - reg: base address and size of memory-mapped region
>   - interrupts: interrupt associated to this IP
> - - clocks: phandles to the clocks feeding the TCON. Three are needed:
> + - clocks: phandles to the clocks feeding the TCON.
> - 'ahb': the interface clocks
> -   - 'tcon-ch0': The clock driving the TCON channel 0
> +   - 'tcon-ch0': The clock driving the TCON channel 0, except for A83T TV 
> TCON
>   - resets: phandles to the reset controllers driving the encoder
> - "lcd": the reset line for the TCON channel 0
>  
>   - clock-names: the clock names mentioned above
>   - reset-names: the reset names mentioned above
> - - clock-output-names: Name of the pixel clock created
> + - clock-output-names: Name of the pixel clock created, if TCON supports
> +   channel 0.
>  
>  - ports: A ports node with endpoint definitions as defined in
>Documentation/devicetree/bindings/media/video-interfaces.txt. The
>first port should be the input endpoint, the second one the output
>  
> -  The output may have multiple endpoints. The TCON has two channels,
> +  The output may have multiple endpoints. TCON can have 1 or 2 channels,
>usually with the first channel being used for the panels interfaces
>(RGB, LVDS, etc.), and the second being used for the outputs that
>require another controller (TV Encoder, HDMI, etc.). The endpoints
> @@ -122,8 +170,8 @@ Required properties:
>  On SoCs other than the A33 and V3s, there is one more clock required:
> - 'tcon-ch1': The clock driving the

Re: [linux-sunxi] [PATCH v2] rtc: ac100: Fix ac100 determine rate bug

2018-02-13 Thread Philipp Rossak 



On 13.02.2018 14:44, Chen-Yu Tsai wrote:

On Tue, Feb 13, 2018 at 9:32 PM, Maxime Ripard
 wrote:

On Tue, Feb 13, 2018 at 01:14:14PM +0100, Philipp Rossak wrote:

This patch fixes a bug, that prevents the Allwinner A83T and the A80
from a successful boot. You can find the shortend trace below:


Since when is it there?

The bug is there since v4.16-rc1 and appeared after the clk branch was 
merged.


^^ Should I add this info also in the commit message?


Unable to handle kernel NULL pointer dereference at virtual address

pgd = (ptrval)
[] *pgd=
Internal error: Oops: 5 [#1] SMP ARM
Modules linked in:
CPU: 0 PID: 49 Comm: kworker/0:1 Not tainted 4.15.0-10190-gb89e32ccd1be #2
Hardware name: Allwinner sun8i Family
Workqueue: events deferred_probe_work_func
PC is at clk_hw_get_rate+0x0/0x34
LR is at ac100_clkout_determine_rate+0x48/0x19c

[ ... ]

(clk_hw_get_rate) from (ac100_clkout_determine_rate+0x48/0x19c)
(ac100_clkout_determine_rate) from  (clk_core_set_rate_nolock+0x3c/0x1a0)
(clk_core_set_rate_nolock) from (clk_set_rate+0x30/0x88)
(clk_set_rate) from (of_clk_set_defaults+0x200/0x364)
(of_clk_set_defaults) from (platform_drv_probe+0x18/0xb0)

To fix that bug, we first check if the return of the
clk_hw_get_parent_by_index is non zero. If it is zero we skip that
clock parent.

The BUG report could be found here: https://lkml.org/lkml/2018/2/10/198

Fixes: 04940631b8d2 ("rtc: ac100: Add clk output support")


Should it be sent to stable?


Signed-off-by: Philipp Rossak 
---

Changes in v2:
   * add tag Fixes: ... to commit message
   * add comment to if statement why we are doing this check

  drivers/rtc/rtc-ac100.c | 12 +++-
  1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/rtc/rtc-ac100.c b/drivers/rtc/rtc-ac100.c
index 8ff9dc3fe5bf..ba73201d8cc1 100644
--- a/drivers/rtc/rtc-ac100.c
+++ b/drivers/rtc/rtc-ac100.c
@@ -183,7 +183,17 @@ static int ac100_clkout_determine_rate(struct clk_hw *hw,

   for (i = 0; i < num_parents; i++) {
   struct clk_hw *parent = clk_hw_get_parent_by_index(hw, i);
- unsigned long tmp, prate = clk_hw_get_rate(parent);
+ unsigned long tmp, prate;
+
+ /*
+  * We purposefully left open the possibility to use the clock
+  * from the codec side but it is not implemented right now.
+  * Thus we need to check if the parent exists.
+  */
+ if (!parent)
+ continue;
+
+ prate = clk_hw_get_rate(parent);


clk_hw_get_num_parents should return the exact number of parents,
which is going to be 1 if you only have one parent, like all DTS seems
to have.

If not, then it should be explained in the comment and / or fixed
properly.


The clock has two parents. One is a fixed clock internally registered
by the driver. This is actually an external crystal, and we should
probably add a device node and the works for it. The other parent
is a clock from the codec side, which we properly declare and
reference in the device tree. This clock, though defined, is not
implemented in any driver (because we don't have any ATM).

This second missing clock is what's causing issues here. The clk core
looks for the parent by name, can't find one that is registered, and
returns NULL.

I guess the comment above is still not clear enough?


I can get more detailed in the comment. I thought about this:

The clock has two parents, one is a fixed clock which is internally 
registered by the ac100 driver. The other parent is a clock from the 
codec side of the chip, which we properly declare and reference in the 
devicetree and is not implemented in any driver right now.
If the clock core looks for the parent of that second missing clock, it 
can't one that is registered and returns NULL.

Thus we need to check if the parent exists before we get the parent rate.

Is that ok for you?

Philipp



ChenYu


Maxime

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Embedded Linux and Kernel engineering
http://bootlin.com


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Re: [linux-sunxi] [PATCH v2] rtc: ac100: Fix ac100 determine rate bug

2018-02-13 Thread Chen-Yu Tsai 
On Tue, Feb 13, 2018 at 9:32 PM, Maxime Ripard
 wrote:
> On Tue, Feb 13, 2018 at 01:14:14PM +0100, Philipp Rossak wrote:
>> This patch fixes a bug, that prevents the Allwinner A83T and the A80
>> from a successful boot. You can find the shortend trace below:
>
> Since when is it there?
>
>> Unable to handle kernel NULL pointer dereference at virtual address
>> 
>> pgd = (ptrval)
>> [] *pgd=
>> Internal error: Oops: 5 [#1] SMP ARM
>> Modules linked in:
>> CPU: 0 PID: 49 Comm: kworker/0:1 Not tainted 4.15.0-10190-gb89e32ccd1be #2
>> Hardware name: Allwinner sun8i Family
>> Workqueue: events deferred_probe_work_func
>> PC is at clk_hw_get_rate+0x0/0x34
>> LR is at ac100_clkout_determine_rate+0x48/0x19c
>>
>> [ ... ]
>>
>> (clk_hw_get_rate) from (ac100_clkout_determine_rate+0x48/0x19c)
>> (ac100_clkout_determine_rate) from  (clk_core_set_rate_nolock+0x3c/0x1a0)
>> (clk_core_set_rate_nolock) from (clk_set_rate+0x30/0x88)
>> (clk_set_rate) from (of_clk_set_defaults+0x200/0x364)
>> (of_clk_set_defaults) from (platform_drv_probe+0x18/0xb0)
>>
>> To fix that bug, we first check if the return of the
>> clk_hw_get_parent_by_index is non zero. If it is zero we skip that
>> clock parent.
>>
>> The BUG report could be found here: https://lkml.org/lkml/2018/2/10/198
>>
>> Fixes: 04940631b8d2 ("rtc: ac100: Add clk output support")
>
> Should it be sent to stable?
>
>> Signed-off-by: Philipp Rossak 
>> ---
>>
>> Changes in v2:
>>   * add tag Fixes: ... to commit message
>>   * add comment to if statement why we are doing this check
>>
>>  drivers/rtc/rtc-ac100.c | 12 +++-
>>  1 file changed, 11 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/rtc/rtc-ac100.c b/drivers/rtc/rtc-ac100.c
>> index 8ff9dc3fe5bf..ba73201d8cc1 100644
>> --- a/drivers/rtc/rtc-ac100.c
>> +++ b/drivers/rtc/rtc-ac100.c
>> @@ -183,7 +183,17 @@ static int ac100_clkout_determine_rate(struct clk_hw 
>> *hw,
>>
>>   for (i = 0; i < num_parents; i++) {
>>   struct clk_hw *parent = clk_hw_get_parent_by_index(hw, i);
>> - unsigned long tmp, prate = clk_hw_get_rate(parent);
>> + unsigned long tmp, prate;
>> +
>> + /*
>> +  * We purposefully left open the possibility to use the clock
>> +  * from the codec side but it is not implemented right now.
>> +  * Thus we need to check if the parent exists.
>> +  */
>> + if (!parent)
>> + continue;
>> +
>> + prate = clk_hw_get_rate(parent);
>
> clk_hw_get_num_parents should return the exact number of parents,
> which is going to be 1 if you only have one parent, like all DTS seems
> to have.
>
> If not, then it should be explained in the comment and / or fixed
> properly.

The clock has two parents. One is a fixed clock internally registered
by the driver. This is actually an external crystal, and we should
probably add a device node and the works for it. The other parent
is a clock from the codec side, which we properly declare and
reference in the device tree. This clock, though defined, is not
implemented in any driver (because we don't have any ATM).

This second missing clock is what's causing issues here. The clk core
looks for the parent by name, can't find one that is registered, and
returns NULL.

I guess the comment above is still not clear enough?

ChenYu

> Maxime
>
> --
> Maxime Ripard, Bootlin (formerly Free Electrons)
> Embedded Linux and Kernel engineering
> http://bootlin.com

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[linux-sunxi] [RESEND PATCH v5 4/6] arm: dts: sun8i: a83t: Add support for the cir interface

2018-02-13 Thread Philipp Rossak 
The cir interface is like on the H3 located at 0x01f02000 and is exactly
the same. This patch adds support for the ir interface on the A83T.

Signed-off-by: Philipp Rossak 
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 13 +
 1 file changed, 13 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index f7f78a27e21d..1e04a5cfd32d 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -704,6 +704,19 @@
#reset-cells = <1>;
};
 
+   r_cir: ir@1f02000 {
+   compatible = "allwinner,sun8i-a83t-ir",
+"allwinner,sun5i-a13-ir";
+   clocks = <_ccu CLK_APB0_IR>, <_ccu CLK_IR>;
+   clock-names = "apb", "ir";
+   resets = <_ccu RST_APB0_IR>;
+   interrupts = ;
+   reg = <0x01f02000 0x400>;
+   pinctrl-names = "default";
+   pinctrl-0 = <_cir_pin>;
+   status = "disabled";
+   };
+
r_pio: pinctrl@1f02c00 {
compatible = "allwinner,sun8i-a83t-r-pinctrl";
reg = <0x01f02c00 0x400>;
-- 
2.11.0

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[linux-sunxi] [RESEND PATCH v5 2/6] media: dt: bindings: Update binding documentation for sunxi IR controller

2018-02-13 Thread Philipp Rossak 
This patch updates documentation for Device-Tree bindings for sunxi IR
controller and adds the new optional property for the base clock
frequency.

Signed-off-by: Philipp Rossak 
Acked-by: Maxime Ripard 
Reviewed-by: Rob Herring 
---
 Documentation/devicetree/bindings/media/sunxi-ir.txt | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/media/sunxi-ir.txt 
b/Documentation/devicetree/bindings/media/sunxi-ir.txt
index 91648c569b1e..278098987edb 100644
--- a/Documentation/devicetree/bindings/media/sunxi-ir.txt
+++ b/Documentation/devicetree/bindings/media/sunxi-ir.txt
@@ -11,6 +11,8 @@ Required properties:
 Optional properties:
 - linux,rc-map-name: see rc.txt file in the same directory.
 - resets : phandle + reset specifier pair
+- clock-frequency  : IR Receiver clock frequency, in Hertz. Defaults to 8 MHz
+if missing.
 
 Example:
 
@@ -18,6 +20,7 @@ ir0: ir@1c21800 {
compatible = "allwinner,sun4i-a10-ir";
clocks = <_gates 6>, <_clk>;
clock-names = "apb", "ir";
+   clock-frequency = <300>;
resets = <_rst 1>;
interrupts = <0 5 1>;
reg = <0x01C21800 0x40>;
-- 
2.11.0

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[linux-sunxi] [RESEND PATCH v5 1/6] media: rc: update sunxi-ir driver to get base clock frequency from devicetree

2018-02-13 Thread Philipp Rossak 
This patch updates the sunxi-ir driver to set the base clock frequency from
devicetree.

This is necessary since there are different ir receivers on the
market, that operate with different frequencies. So this value could be
set if the attached ir receiver needs a different base clock frequency,
than the default 8 MHz.

Signed-off-by: Philipp Rossak 
Reviewed-by: Andi Shyti 
Acked-by: Sean Young 
---
 drivers/media/rc/sunxi-cir.c | 19 +++
 1 file changed, 11 insertions(+), 8 deletions(-)

diff --git a/drivers/media/rc/sunxi-cir.c b/drivers/media/rc/sunxi-cir.c
index 97f367b446c4..f500cea228a9 100644
--- a/drivers/media/rc/sunxi-cir.c
+++ b/drivers/media/rc/sunxi-cir.c
@@ -72,12 +72,8 @@
 /* CIR_REG register idle threshold */
 #define REG_CIR_ITHR(val)(((val) << 8) & (GENMASK(15, 8)))
 
-/* Required frequency for IR0 or IR1 clock in CIR mode */
+/* Required frequency for IR0 or IR1 clock in CIR mode (default) */
 #define SUNXI_IR_BASE_CLK 800
-/* Frequency after IR internal divider  */
-#define SUNXI_IR_CLK  (SUNXI_IR_BASE_CLK / 64)
-/* Sample period in ns */
-#define SUNXI_IR_SAMPLE   (10ul / SUNXI_IR_CLK)
 /* Noise threshold in samples  */
 #define SUNXI_IR_RXNOISE  1
 /* Idle Threshold in samples */
@@ -122,7 +118,8 @@ static irqreturn_t sunxi_ir_irq(int irqno, void *dev_id)
/* for each bit in fifo */
dt = readb(ir->base + SUNXI_IR_RXFIFO_REG);
rawir.pulse = (dt & 0x80) != 0;
-   rawir.duration = ((dt & 0x7f) + 1) * SUNXI_IR_SAMPLE;
+   rawir.duration = ((dt & 0x7f) + 1) *
+ir->rc->rx_resolution;
ir_raw_event_store_with_filter(ir->rc, );
}
}
@@ -148,6 +145,7 @@ static int sunxi_ir_probe(struct platform_device *pdev)
struct device_node *dn = dev->of_node;
struct resource *res;
struct sunxi_ir *ir;
+   u32 b_clk_freq = SUNXI_IR_BASE_CLK;
 
ir = devm_kzalloc(dev, sizeof(struct sunxi_ir), GFP_KERNEL);
if (!ir)
@@ -172,6 +170,9 @@ static int sunxi_ir_probe(struct platform_device *pdev)
return PTR_ERR(ir->clk);
}
 
+   /* Base clock frequency (optional) */
+   of_property_read_u32(dn, "clock-frequency", _clk_freq);
+
/* Reset (optional) */
ir->rst = devm_reset_control_get_optional_exclusive(dev, NULL);
if (IS_ERR(ir->rst))
@@ -180,11 +181,12 @@ static int sunxi_ir_probe(struct platform_device *pdev)
if (ret)
return ret;
 
-   ret = clk_set_rate(ir->clk, SUNXI_IR_BASE_CLK);
+   ret = clk_set_rate(ir->clk, b_clk_freq);
if (ret) {
dev_err(dev, "set ir base clock failed!\n");
goto exit_reset_assert;
}
+   dev_dbg(dev, "set base clock frequency to %d Hz.\n", b_clk_freq);
 
if (clk_prepare_enable(ir->apb_clk)) {
dev_err(dev, "try to enable apb_ir_clk failed\n");
@@ -225,7 +227,8 @@ static int sunxi_ir_probe(struct platform_device *pdev)
ir->rc->map_name = ir->map_name ?: RC_MAP_EMPTY;
ir->rc->dev.parent = dev;
ir->rc->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;
-   ir->rc->rx_resolution = SUNXI_IR_SAMPLE;
+   /* Frequency after IR internal divider with sample period in ns */
+   ir->rc->rx_resolution = (10ul / (b_clk_freq / 64));
ir->rc->timeout = MS_TO_NS(SUNXI_IR_TIMEOUT);
ir->rc->driver_name = SUNXI_IR_DEV;
 
-- 
2.11.0

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[linux-sunxi] [RESEND PATCH v5 3/6] arm: dts: sun8i: a83t: Add the cir pin for the A83T

2018-02-13 Thread Philipp Rossak 
The CIR Pin of the A83T is located at PL12.

Signed-off-by: Philipp Rossak 
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 7f4955a5fab7..f7f78a27e21d 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -716,6 +716,11 @@
interrupt-controller;
#interrupt-cells = <3>;
 
+   r_cir_pin: r-cir-pin {
+   pins = "PL12";
+   function = "s_cir_rx";
+   };
+
r_rsb_pins: r-rsb-pins {
pins = "PL0", "PL1";
function = "s_rsb";
-- 
2.11.0

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[linux-sunxi] [RESEND PATCH v5 5/6] arm: dts: sun8i: a83t: bananapi-m3: Enable IR controller

2018-02-13 Thread Philipp Rossak 
The Bananapi M3 has an onboard IR receiver.
This enables the onboard IR receiver subnode.
Unlike the other IR receivers this one needs a base clock frequency
of 300 Hz (3 MHz), to be able to work.

Signed-off-by: Philipp Rossak 
Acked-by: Chen-Yu Tsai 
---
 arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts 
b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
index 6550bf0e594b..26c015fd4f4d 100644
--- a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
@@ -145,6 +145,11 @@
status = "okay";
 };
 
+_cir {
+   clock-frequency = <300>;
+   status = "okay";
+};
+
 _rsb {
status = "okay";
 
-- 
2.11.0

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[linux-sunxi] [RESEND PATCH v5 6/6] arm: dts: sun8i: h3-h5: ir register size should be the whole memory block

2018-02-13 Thread Philipp Rossak 
The size of the register should be the size of the whole memory block,
not just the registers, that are needed.

Signed-off-by: Philipp Rossak 
---
 arch/arm/boot/dts/sunxi-h3-h5.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi 
b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index 7a83b15225c7..22f6e126b8df 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -712,7 +712,7 @@
clock-names = "apb", "ir";
resets = <_ccu RST_APB0_IR>;
interrupts = ;
-   reg = <0x01f02000 0x40>;
+   reg = <0x01f02000 0x400>;
status = "disabled";
};
 
-- 
2.11.0

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[linux-sunxi] [RESEND PATCH v5 0/6] IR support for A83T

2018-02-13 Thread Philipp Rossak 
This patch series adds support for the sunxi A83T ir module and enhances 
the sunxi-ir driver. Right now the base clock frequency for the ir driver
is a hard coded define and is set to 8 MHz.
This works for the most common ir receivers. On the Sinovoip Bananapi M3 
the ir receiver needs, a 3 MHz base clock frequency to work without
problems with this driver.

This patch series adds support for an optinal property that makes it able
to override the default base clock frequency and enables the ir interface 
on the a83t and the Bananapi M3.

changes since v4:
* rename cir pin from cir_pins to r_cir_pin
* drop unit-adress from r_cir_pin
* add a83t compatible to the cir node
* move muxing options to dtsi
* rename cir label and reorder it in the bananpim3.dts file

changes since v3:
* collecting all acks & reviewd by
* fixed typos

changes since v2:
* reorder cir pin (alphabetical)
* fix typo in documentation

changes since v1:
* fix typos, reword Documentation
* initialize 'b_clk_freq' to 'SUNXI_IR_BASE_CLK' & remove if statement
* change dev_info() to dev_dbg()
* change naming to cir* in dts/dtsi
* Added acked Ackedi-by to related patch
* use whole memory block instead of registers needed + fix for h3/h5

changes since rfc:
* The property is now optinal. If the property is not available in 
  the dtb the driver uses the default base clock frequency.
* the driver prints out the the selected base clock frequency.
* changed devicetree property from base-clk-frequency to clock-frequency

Regards,
Philipp

Philipp Rossak (6):
  media: rc: update sunxi-ir driver to get base clock frequency from
devicetree
  media: dt: bindings: Update binding documentation for sunxi IR
controller
  arm: dts: sun8i: a83t: Add the cir pin for the A83T
  arm: dts: sun8i: a83t: Add support for the cir interface
  arm: dts: sun8i: a83t: bananapi-m3: Enable IR controller
  arm: dts: sun8i: h3-h5: ir register size should be the whole memory
block

 Documentation/devicetree/bindings/media/sunxi-ir.txt |  3 +++
 arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts |  5 +
 arch/arm/boot/dts/sun8i-a83t.dtsi| 18 ++
 arch/arm/boot/dts/sunxi-h3-h5.dtsi   |  2 +-
 drivers/media/rc/sunxi-cir.c | 19 +++
 5 files changed, 38 insertions(+), 9 deletions(-)

-- 
2.11.0

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[linux-sunxi] [PATCH v2] rtc: ac100: Fix ac100 determine rate bug

2018-02-13 Thread Philipp Rossak 
This patch fixes a bug, that prevents the Allwinner A83T and the A80
from a successful boot. You can find the shortend trace below:

Unable to handle kernel NULL pointer dereference at virtual address

pgd = (ptrval)
[] *pgd=
Internal error: Oops: 5 [#1] SMP ARM
Modules linked in:
CPU: 0 PID: 49 Comm: kworker/0:1 Not tainted 4.15.0-10190-gb89e32ccd1be #2
Hardware name: Allwinner sun8i Family
Workqueue: events deferred_probe_work_func
PC is at clk_hw_get_rate+0x0/0x34
LR is at ac100_clkout_determine_rate+0x48/0x19c

[ ... ]

(clk_hw_get_rate) from (ac100_clkout_determine_rate+0x48/0x19c)
(ac100_clkout_determine_rate) from  (clk_core_set_rate_nolock+0x3c/0x1a0)
(clk_core_set_rate_nolock) from (clk_set_rate+0x30/0x88)
(clk_set_rate) from (of_clk_set_defaults+0x200/0x364)
(of_clk_set_defaults) from (platform_drv_probe+0x18/0xb0)

To fix that bug, we first check if the return of the
clk_hw_get_parent_by_index is non zero. If it is zero we skip that
clock parent.

The BUG report could be found here: https://lkml.org/lkml/2018/2/10/198

Fixes: 04940631b8d2 ("rtc: ac100: Add clk output support")

Signed-off-by: Philipp Rossak 
---

Changes in v2:
* add tag Fixes: ... to commit message
* add comment to if statement why we are doing this check

 drivers/rtc/rtc-ac100.c | 12 +++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/rtc/rtc-ac100.c b/drivers/rtc/rtc-ac100.c
index 8ff9dc3fe5bf..ba73201d8cc1 100644
--- a/drivers/rtc/rtc-ac100.c
+++ b/drivers/rtc/rtc-ac100.c
@@ -183,7 +183,17 @@ static int ac100_clkout_determine_rate(struct clk_hw *hw,
 
for (i = 0; i < num_parents; i++) {
struct clk_hw *parent = clk_hw_get_parent_by_index(hw, i);
-   unsigned long tmp, prate = clk_hw_get_rate(parent);
+   unsigned long tmp, prate;
+
+   /*
+* We purposefully left open the possibility to use the clock
+* from the codec side but it is not implemented right now.
+* Thus we need to check if the parent exists.
+*/
+   if (!parent)
+   continue;
+
+   prate = clk_hw_get_rate(parent);
 
tmp = ac100_clkout_round_rate(hw, req->rate, prate);
 
-- 
2.11.0

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[linux-sunxi] Re: BUG: A31s Not booting anymore

2018-02-13 Thread Chen-Yu Tsai 
On Tue, Feb 13, 2018 at 7:32 PM, Philipp Rossak  wrote:
>
>
> On 13.02.2018 03:59, Chen-Yu Tsai wrote:
>>
>> On Tue, Feb 13, 2018 at 9:25 AM, Philipp Rossak  wrote:
>>>
>>>
>>>
>>> On 12.02.2018 19:21, Philipp Rossak wrote:


 Hey,

 When I try to boot my A31s (Bananapi M2) u-boot is showing only Starting
 kernel ... . After enabling the earlyprintk I could capture this log:
 [1].

 After reverting those 5 commits from Chen-Yu I was able to boot again:


 clk: sunxi-ng: Support fixed post-dividers on NM style clocks
 7d333ef1cc1b8c8951f3a2c41f6406e2295d8be9

 clk: sunxi-ng: sun8i: a83t: Add /2 fixed post divider to audio PLL
 10e6eb4f2c5b35ae71c9bc0db83d74238719b453

 clk: sunxi-ng: sun8i: a83t: Use sigma-delta modulation for audio PLL
 e952ca3c6b2ffdfbf9618e4bd3e9aad1ff3f5eb4

 clk: sunxi-ng: Support fixed post-dividers on MP style clocks
 946797aa3f08e2f6f5992f3ec2be44791e9b9260

 clk: sunxi-ng: sun50i: a64: Add 2x fixed post-divider to MMC module
 clocks
 83fe3be4d1974f5f50c5e2039a1609f4960e8579


 I allready tried to fix it with making them save against zero:

 if (cmp->common.features & CCU_FEATURE_FIXED_POSTDIV && \
   cmp->fixed_post_div with)
  rate *= cmp->fixed_post_div;

 But that didn't help.

 Any ideas?

 Regards,
 Philipp

 [1]: https://pastebin.com/64Fzzqvg
>>>
>>>
>>>
>>> It took me some time, but I have now a few more infos:
>>>
>>> Right now the code breaks at this point here [1], with this clock [2].
>>> If we have a look now at the clock config [3], we see here a table which
>>> is
>>> an u8 array and also a fixed_predivs struct.
>>
>>
>> The u8 array is for mapping the parents from the index in the parents
>> array to the actual register value you listed below.
>>
>> How are you figuring out which clock is triggering this? Because that
>> is not even the right type of clock. The backtrace you posted shows
>> the error occurring in a DIV or M type clock, not the MP type you
>> are pointing to.
>>
>> Could you add some noisy printk calls to the sunxi_ccu_probe()
>> function in drivers/clk/sunxi-ng/ccu_common.c so it's much clearer
>> which clock is failing?
>
>
> Thats what I basically did to find out which clock is failing. This here are
> the changes I'm doing [1]  and thats the dirty log [2]. It fails at clock NR
> 155 which is this one [3] mentioned before.
>
>>
>>
>>>
>>> If we have a look at the function call where it breaks [4], shouldn't the
>>> table be a clk_div_table struct instead of an u8?
>>
>>
>> The table argument is an option. Did you go through how the sunxi-ng
>> driver
>> calls this function? As mentioned above, you are looking at the wrong
>> thing.
>>
>> Thanks
>> ChenYu
>
>
> I followed the failing call to this function (through the clock driver). As
> you can see I added an additional printk statement to see where it fails.

I found the problem... wrong ops for the clock type. Likely a copy-paste
error on my part. I'll send a patch later.

Sorry for being so harsh on you.

ChenYu

> Regards,
> Philipp
>
>>
>>>
>>> The a31s is the only board where we have this combination of a
>>> fixed_predivs
>>> and a table.
>>>
>>> Philipp
>>>
>>>
>>> Related Clock source register A31s:
>>>
>>> : OSC24MHz/750=32KHz
>>> 0001: LOSC
>>> 0010: OSC24MHz
>>> 0011: /
>>> 0100: /
>>> 0101: /
>>> 0110: /
>>> 0111: /
>>> 1000: /
>>> 1001: /
>>> 1010: /
>>> 1011: AXICLK/4
>>> 1100: /
>>> 1101: AHB1CLK/4
>>> 1110: /
>>> : /
>>>
>>>
>>> [1]:
>>>
>>> http://lxr.bootlin.com/linux/v4.16-rc1/source/drivers/clk/clk-divider.c#L89
>>>
>>> [2]:
>>>
>>> http://lxr.bootlin.com/linux/v4.16-rc1/source/drivers/clk/sunxi-ng/ccu-sun6i-a31.c#L1137
>>>
>>> [3]:
>>>
>>> http://lxr.bootlin.com/linux/v4.16-rc1/source/drivers/clk/sunxi-ng/ccu-sun6i-a31.c#L749
>>>
>>> [4]:
>>>
>>> http://lxr.bootlin.com/linux/v4.16-rc1/source/drivers/clk/clk-divider.c#L93
>>>
>
> [1]: https://pastebin.com/tvDunAWq
> [2]: https://pastebin.com/SBn2VQLu
> [3]:
> http://lxr.bootlin.com/linux/v4.16-rc1/source/include/dt-bindings/clock/sun6i-a31-ccu.h#L187

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[linux-sunxi] Re: BUG: A31s Not booting anymore

2018-02-13 Thread Philipp Rossak 



On 13.02.2018 03:59, Chen-Yu Tsai wrote:

On Tue, Feb 13, 2018 at 9:25 AM, Philipp Rossak  wrote:



On 12.02.2018 19:21, Philipp Rossak wrote:


Hey,

When I try to boot my A31s (Bananapi M2) u-boot is showing only Starting
kernel ... . After enabling the earlyprintk I could capture this log: [1].

After reverting those 5 commits from Chen-Yu I was able to boot again:


clk: sunxi-ng: Support fixed post-dividers on NM style clocks
7d333ef1cc1b8c8951f3a2c41f6406e2295d8be9

clk: sunxi-ng: sun8i: a83t: Add /2 fixed post divider to audio PLL
10e6eb4f2c5b35ae71c9bc0db83d74238719b453

clk: sunxi-ng: sun8i: a83t: Use sigma-delta modulation for audio PLL
e952ca3c6b2ffdfbf9618e4bd3e9aad1ff3f5eb4

clk: sunxi-ng: Support fixed post-dividers on MP style clocks
946797aa3f08e2f6f5992f3ec2be44791e9b9260

clk: sunxi-ng: sun50i: a64: Add 2x fixed post-divider to MMC module clocks
83fe3be4d1974f5f50c5e2039a1609f4960e8579


I allready tried to fix it with making them save against zero:

if (cmp->common.features & CCU_FEATURE_FIXED_POSTDIV && \
  cmp->fixed_post_div with)
 rate *= cmp->fixed_post_div;

But that didn't help.

Any ideas?

Regards,
Philipp

[1]: https://pastebin.com/64Fzzqvg



It took me some time, but I have now a few more infos:

Right now the code breaks at this point here [1], with this clock [2].
If we have a look now at the clock config [3], we see here a table which is
an u8 array and also a fixed_predivs struct.


The u8 array is for mapping the parents from the index in the parents
array to the actual register value you listed below.

How are you figuring out which clock is triggering this? Because that
is not even the right type of clock. The backtrace you posted shows
the error occurring in a DIV or M type clock, not the MP type you
are pointing to.

Could you add some noisy printk calls to the sunxi_ccu_probe()
function in drivers/clk/sunxi-ng/ccu_common.c so it's much clearer
which clock is failing?


Thats what I basically did to find out which clock is failing. This here 
are the changes I'm doing [1]  and thats the dirty log [2]. It fails at 
clock NR 155 which is this one [3] mentioned before.







If we have a look at the function call where it breaks [4], shouldn't the
table be a clk_div_table struct instead of an u8?


The table argument is an option. Did you go through how the sunxi-ng driver
calls this function? As mentioned above, you are looking at the wrong thing.

Thanks
ChenYu


I followed the failing call to this function (through the clock driver). 
As you can see I added an additional printk statement to see where it fails.


Regards,
Philipp




The a31s is the only board where we have this combination of a fixed_predivs
and a table.

Philipp


Related Clock source register A31s:

: OSC24MHz/750=32KHz
0001: LOSC
0010: OSC24MHz
0011: /
0100: /
0101: /
0110: /
0111: /
1000: /
1001: /
1010: /
1011: AXICLK/4
1100: /
1101: AHB1CLK/4
1110: /
: /


[1]:
http://lxr.bootlin.com/linux/v4.16-rc1/source/drivers/clk/clk-divider.c#L89

[2]:
http://lxr.bootlin.com/linux/v4.16-rc1/source/drivers/clk/sunxi-ng/ccu-sun6i-a31.c#L1137

[3]:
http://lxr.bootlin.com/linux/v4.16-rc1/source/drivers/clk/sunxi-ng/ccu-sun6i-a31.c#L749

[4]:
http://lxr.bootlin.com/linux/v4.16-rc1/source/drivers/clk/clk-divider.c#L93



[1]: https://pastebin.com/tvDunAWq
[2]: https://pastebin.com/SBn2VQLu
[3]: 
http://lxr.bootlin.com/linux/v4.16-rc1/source/include/dt-bindings/clock/sun6i-a31-ccu.h#L187


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[linux-sunxi] Re: [PATCH] Revert "ARM: dts: sunxi: Add regulators for Sinovoip BPI-M2"

2018-02-13 Thread Chen-Yu Tsai 
On Sat, Feb 10, 2018 at 5:20 AM, Emmanuel Vadot  wrote:
> On 2018-02-05 10:05, Icenowy Zheng wrote:
>>
>> 于 2018年2月5日 GMT+08:00 下午4:55:58, Emmanuel Vadot 
>> 写到:
>>>
>>>
>>> Hello,
>>>
>>> On Sat,  3 Feb 2018 19:23:53 +0800
>>> Icenowy Zheng  wrote:
>>>
 This reverts commit 7daa213700758b5b08fc0daab09bb139dd334165.

 The original commit has several problems:

 - vdd-cpus and aldo3 (AVCC of the SoC) are not set to always-on,
>>>
>>> which

 leads to system hang when disabling unused regulators.
>>>
>>>
>>> Indeed I should have make those always-on.
>>>
 - GMAC (which uses dldo1 and aldo2) and Wi-Fi (which uses aldo1) are
>>>
>>> not

 considered, and will fail to work after adding this commit.
>>>
>>>
>>> While I understand the problem with vdd-cpus and aldo3 I don't see why
>>> when you don't declare regulator the code should do something with it.
>>> DT is supposed to describe the hardware and the code should not use
>>> hardware not described right ?
>>> The gmac node doesn't declare any regulators and the mmc2 uses
>>> reg_vcc3v0 (haven't checked on the schematics yet if it is correct).
>>
>>
>> It's because the regulator support isn't present before
>> this commit. However these parts really need special
>> regulators. I don't have M2 schematics at hand, so you'd
>> check it by yourself.
>
>
>  Yes but why does the PMIC should disable regulators not defined in the DTS
> ? That the part I don't understand and want to know where it is
> described/documented.

They are defined. See axp22x.dtsi, which you included in your patch.

Now the system is free to do whatever it wants under the constraints
of the device tree. Since you do not reference the regulator, the
kernel is free to turn it off to save power.

>
>> P.S. a proper device tree with AXP shouldn't use
>> reg_vcc3v0/3v3/1v8/etc. They're dummy
>> regulator nodes for
>> not implemented or not controllable regulators.
>>
>>>
 This indicates that this patch should be not tested at all.
>>>
>>>
>>> This have indeed not been tested with linux.
>>> I think that this commit should not be reverted, I'll send a proper
>>> patch tonight or tomorow night max.
>>
>>
>> Please test patches sent to Linux on Linux :-)
>
>
>  If my patches adhere to the bindings I don't see why.

It adheres to the bindings, but does not accurately describe the
hardware constraints.

ChenYu

>
>
>>>
>>> P.S.: Also as I'm the original sender I think I should have been in CC
>>> no ?
>>
>>
>> get_maintainer.pl didn't mention you and I forgot... sorry.
>>
>>>
>>> Cheers,
>>>
 Signed-off-by: Icenowy Zheng 
 ---
  arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts | 57
>>>
>>> 

  1 file changed, 57 deletions(-)

 diff --git a/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts
>>>
>>> b/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts

 index 51e6f1d21c32..a565316eb340 100644
 --- a/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts
 +++ b/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts
 @@ -86,10 +86,6 @@
 };
  };

 - {
 -   cpu-supply = <_dcdc3>;
 -};
 -
   {
 status = "okay";
  };
 @@ -155,17 +151,6 @@
 status = "okay";
  };

 - {
 -   status = "okay";
 -
 -   axp22x: pmic@68 {
 -   compatible = "x-powers,axp221";
 -   reg = <0x68>;
 -   interrupt-parent = <_intc>;
 -   interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
 -   };
 -};
 -
   {
 gmac_phy_reset_pin_bpi_m2: gmac_phy_reset_pin@0 {
 pins = "PA21";
 @@ -191,48 +176,6 @@
 };
  };

 -#include "axp22x.dtsi"
 -
 -_dc5ldo {
 -   regulator-min-microvolt = <70>;
 -   regulator-max-microvolt = <132>;
 -   regulator-name = "vdd-cpus";
 -};
 -
 -_dcdc1 {
 -   regulator-always-on;
 -   regulator-min-microvolt = <300>;
 -   regulator-max-microvolt = <300>;
 -   regulator-name = "vdd-3v0";
 -};
 -
 -_dcdc2 {
 -   regulator-min-microvolt = <70>;
 -   regulator-max-microvolt = <132>;
 -   regulator-name = "vdd-gpu";
 -};
 -
 -_dcdc3 {
 -   regulator-always-on;
 -   regulator-min-microvolt = <70>;
 -   regulator-max-microvolt = <132>;
 -   regulator-name = "vdd-cpu";
 -};
 -
 -_dcdc4 {
 -   regulator-always-on;
 -   regulator-min-microvolt = <70>;
 -   regulator-max-microvolt = <132>;
 -   regulator-name = "vdd-sys-dll";
 -};
 -
 -_dcdc5 {
 -   regulator-always-on;
 -   regulator-min-microvolt = <150>;
 -   regulator-max-microvolt = <150>;

[linux-sunxi] Re: [PATCH v4 0/8] ARM: sun9i: SMP and CPU hotplug support

2018-02-13 Thread Chen-Yu Tsai 
Hi Nicolas, Dave,

On Wed, Jan 17, 2018 at 4:46 PM, Chen-Yu Tsai  wrote:
> This is v4 of my sun9i SMP/hotplug support series which was started
> over two years ago [1]. We've tried to implement PSCI for both the A80
> and A83T. Results were not promising. The issue is that these two chips
> have a broken security extensions implementation. If a specific bit is
> not burned in its e-fuse, most if not all security protections don't
> work [2]. Even worse, non-secure access to the GIC become secure. This
> requires a crazy workaround in the GIC driver which probably doesn't work
> in all cases [3].
>
> Version 3 completely did away with the MCPM framework, instead just
> implementing a set of smp_ops. Most of the code from the previous
> version was reused, so the structure still has some traces of MCPM.
> As our hardware has CCI-400, we still need some sort of MMU/cache
> disabled trampoline code to enable cache coherency. Code for this
> was adapted from the MCPM framework. This and the entry code are done
> in inline assembly. Most of the other sunxi-specific code is derived
> from Allwinner code and documentation, with some references to the
> other MCPM implementations, as well as the Cortex's Technical Reference
> Manuals for the power sequencing stuff.
>
> In version 4, all traces of MCPM have been removed, except in the
> comments for atttributing code sources. Thumb2 mode is also fixed.
> It failed due to an unaligned word access.

Any more comments on this series? Or is it OK for you guys now that
there are no traces of MCPM? :)

We'll merge this series later this week for 4.17 if nothing else.

Thanks
ChenYu

>
> Hope we can get this version merged. A83T SMP support will be built on
> it.
>
> Regards
> ChenYu
>
> Changes since v3:
>   - Renamed all "MCPM" occurrences to "MC_SMP", as the MCPM framework
> is no longer used
>   - Thumb2 mode fixed
>
> Changes since v2:
>   - Do away with the MCPM framework, directly implement smp_ops
>   - Some debug messages were clarified
>   - New ARCH_SUNXI_MCPM Kconfig symbol for this feature
>
> Changes since v1:
>
>   - Leading zeroes for device node addresses removed
>   - Added device tree binding for SMP SRAM
>   - Simplified Kconfig options
>   - Switched to SPDX license identifier
>   - Map CPU to device tree node and check compatible to see if it's
> Cortex-A15 or Cortex-A7
>   - Fix incorrect CPUCFG cluster status macro that prevented cluster
> 0 L2 cache WFI detection
>   - Fixed reversed bit for turning off cluster
>   - Put cluster in reset before turning off power (or it hangs)
>   - Added dedicated workqueue for turning off power to cpus and clusters
>   - Request CPUCFG and SRAM MMIO ranges
>   - Some comments fixed or added
>   - Some debug messages added
>
> [1] http://www.spinics.net/lists/arm-kernel/msg418350.html
> [2] https://lists.denx.de/pipermail/u-boot/2017-June/294637.html
> [3] 
> https://github.com/wens/linux/commit/c48654c1f737116e7a7660183c8c74fa91970528
>
> Chen-Yu Tsai (8):
>   ARM: sun9i: Support SMP bring-up on A80
>   ARM: dts: sun9i: Add CCI-400 device nodes for A80
>   ARM: dts: sun9i: Add CPUCFG device node for A80 dtsi
>   ARM: dts: sun9i: Add PRCM device node for the A80 dtsi
>   ARM: sun9i: smp: Support CPU/cluster power down and hotplugging for
> cpu1~7
>   dt-bindings: ARM: sunxi: Document A80 SoC secure SRAM usage by SMP
> hotplug
>   ARM: sun9i: smp: Support cpu0 hotplug
>   ARM: dts: sun9i: Add secure SRAM node used for SMP hotplug
>
>  .../devicetree/bindings/arm/sunxi/smp-sram.txt |  44 ++
>  arch/arm/boot/dts/sun9i-a80.dtsi   |  75 ++
>  arch/arm/mach-sunxi/Kconfig|   7 +
>  arch/arm/mach-sunxi/Makefile   |   1 +
>  arch/arm/mach-sunxi/mc_smp.c   | 791 
> +
>  5 files changed, 918 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/arm/sunxi/smp-sram.txt
>  create mode 100644 arch/arm/mach-sunxi/mc_smp.c
>
> --
> 2.15.1
>

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