the sun6i-dma driver, as
it no longer works, and is replaced by the previous patch.
Suggestions are more than welcome.
Cheers
ChenYu
Chen-Yu Tsai (7):
clk: sunxi: Add post clk divider for factor clocks
clk: sunxi: Fix PLL6 calculation on sun6i
clk: sunxi: unify sun6i AHB1 clock with proper PLL6
fixes the N factor in the clock driver, and adds a post
PLL divider of 2 to calculate the rate for PLL6.
A further patch (to the DT) should add a fixed-factor x2 clock as
the PLL6x2 output.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
drivers/clk/sunxi/clk-sunxi.c | 6 --
1 file changed, 4
The clock driver has unified support for the ahb1 clock.
Unify the clock nodes so it works.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun8i-a23.dtsi | 12 ++--
1 file changed, 2 insertions(+), 10 deletions(-)
diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi b/arch/arm
The clock driver has unified support for the ahb1 clock.
Unify the clock nodes so it works.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun6i-a31.dtsi | 12 ++--
1 file changed, 2 insertions(+), 10 deletions(-)
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm
Some factor clocks, mostly PLLs, have an extra fixed divider just before
the clock output. Add an option to the factor clk driver config data to
specify this divider.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
drivers/clk/sunxi/clk-factors.c | 3 +++
drivers/clk/sunxi/clk-factors.h | 1 +
2
properties.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
drivers/dma/sun6i-dma.c | 23 ---
1 file changed, 23 deletions(-)
diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c
index 1f92a56..3aa10b3 100644
--- a/drivers/dma/sun6i-dma.c
+++ b/drivers/dma/sun6i-dma.c
This patch unifies the sun6i AHB1 clock, originally supported
with separate mux and divider clks. It also adds support for
the pre-divider on the PLL6 input, thus allowing the clock to
be muxed to PLL6 with proper clock rate calculation.
Signed-off-by: Chen-Yu Tsai w...@csie.org
The DMA controller requires AHB1 bus clock to be clocked from PLL6.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun6i-a31.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 8eb2c6d..1117989
Self NACK this one.
I misread the definition, and extrapolated from the init data.
The original code is correct. Sorry about the noise.
On Sat, Sep 6, 2014 at 12:06 PM, Chen-Yu Tsai w...@csie.org wrote:
clk_register_mux takes both register bit shift and mask as parameters
to which bits
On Mon, Sep 8, 2014 at 5:37 PM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
Hi,
On Mon, Sep 01, 2014 at 10:14:39PM +0800, Chen-Yu Tsai wrote:
This is a Q8 format 7 inch tablet with an Allwinner A13 SoC.
It has 512MB DRAM, 4GB NAND flash, an accelerometer, camera,
RTL8188-based WiFi
Goede hdego...@redhat.com
[w...@csie.org: spacing fixes reported by checkpatch.pl]
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/cpu/armv7/sunxi/Makefile | 1 +
arch/arm/cpu/armv7/sunxi/prcm.c| 37 +
arch/arm/include/asm/arch-sunxi/prcm.h | 238
around mmc and smp code, drop MACH_TYPE]
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/Kconfig| 3 +++
arch/arm/cpu/armv7/sunxi/cpu_info.c | 2 ++
board/sunxi/Kconfig | 10 +-
configs/Colombus_defconfig | 4
include
BOOT_TARGET_DEVICES includes USB unconditionally. This breaks when
CONFIG_CMD_USB is not defined. Use a secondary macro to conditionally
include it when CONFIG_EHCI is enabled, as we do for CONFIG_AHCI.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
include/configs/sunxi-common.h | 8 +++-
1
From: Oliver Schinagl oli...@schinagl.nl
A31 has several new and changed memory address. This patch adds them.
Signed-off-by: Oliver Schinagl oli...@schinagl.nl
Signed-off-by: Hans de Goede hdego...@redhat.com
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/include/asm/arch-sunxi/cpu.h
on sun6i.
Patch 6 adds uart0 muxing on sun6i.
Patch 7 enables sun6i support and adds defconfig for the Colombus board.
Cheers
ChenYu
Chen-Yu Tsai (2):
ARM: sunxi: Fix build break when CONFIG_USB_EHCI is not defined
ARM: sun6i: Add clock support
Hans de Goede (1):
ARM: sunxi-mmc: Add mmc
This is an A13 based Q8 format tablet with 512 MB of DRAM.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
Note this just uses one of the generic dram configurations,
that is, without the zq parameters.
---
board/sunxi/Makefile | 1 +
boards.cfg | 1 +
2 files changed, 2 insertions
This is a Q8 format 7 inch tablet with an Allwinner A13 SoC.
It has 512MB DRAM, 4GB NAND flash, an accelerometer, camera,
RTL8188-based WiFi, and micro SD slot for external storage.
It is likely made by a subsidiary of Hanns.G (Hannstar).
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
Note
Hi Ian, Hans,
On Mon, Sep 8, 2014 at 9:28 PM, Chen-Yu Tsai w...@csie.org wrote:
BOOT_TARGET_DEVICES includes USB unconditionally. This breaks when
CONFIG_CMD_USB is not defined. Use a secondary macro to conditionally
include it when CONFIG_EHCI is enabled, as we do for CONFIG_AHCI.
The other
On Fri, Sep 12, 2014 at 5:15 AM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
On Sat, Sep 06, 2014 at 06:47:27PM +0800, Chen-Yu Tsai wrote:
The DMA controller requires AHB1 bus clock to be clocked from PLL6.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun6i-a31
Hi,
On Fri, Sep 12, 2014 at 5:02 AM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
Hi,
On Sat, Sep 06, 2014 at 06:47:24PM +0800, Chen-Yu Tsai wrote:
This patch unifies the sun6i AHB1 clock, originally supported
with separate mux and divider clks. It also adds support for
the pre
Pushed, along with a23 memory controller register dumps.
On Mon, Sep 1, 2014 at 12:40 PM, Chen-Yu Tsai w...@csie.org wrote:
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
I want to get some input before i push this.
Is the dram_zq parameter suppose to be filled?
or just the lower 8 bits
This fixes the mmc code no longer working on sun8i after the changes to
stop using dma, like sun6i.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
drivers/mmc/sunxi_mmc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index
On Fri, Sep 12, 2014 at 7:06 PM, Simos Xenitellis
simos.li...@googlemail.com wrote:
On Thu, Sep 11, 2014 at 8:11 PM, Luc Verhaegen l...@skynet.be wrote:
On Thu, Sep 11, 2014 at 05:22:21PM +0300, Simos Xenitellis wrote:
Hi All,
I asked Allwinner about the possibility of donation of a few
On Fri, Sep 12, 2014 at 2:57 AM, Ian Campbell i...@hellion.org.uk wrote:
On Thu, 2014-09-11 at 19:19 +0200, Hans de Goede wrote:
Hi Chen,
On 09/11/2014 07:07 PM, Chen-Yu Tsai wrote:
Hi Ian, Hans,
On Mon, Sep 8, 2014 at 9:28 PM, Chen-Yu Tsai w...@csie.org wrote:
BOOT_TARGET_DEVICES
adds proper PLL6 and MBUS clock nodes to the DT, with a dummy
PLL5 clock node as a parent to MBUS.
Cheers
ChenYu
Chen-Yu Tsai (2):
clk: sunxi: Add sun8i MBUS clock support
ARM: dts: sun8i: Add PLL6 and MBUS clock nodes
Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
arch/arm/boot
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
drivers/clk/sunxi/clk-mod0.c | 55 +++
2 files changed, 56 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt
b
for the A23 (sun8i), as well as
the undocumented register quirk.
Patch 3 adds the dma controller node, and related dma resources, to the
DT.
Cheers
ChenYu
Chen-Yu Tsai (3):
dmaengine: sun6i: support parameterized compatible strings
dmaengine: sun6i: Add support for Allwinner A23 (sun8i
-Yu Tsai w...@csie.org
---
Documentation/devicetree/bindings/dma/sun6i-dma.txt | 2 +-
drivers/dma/Kconfig | 4 ++--
drivers/dma/sun6i-dma.c | 20
3 files changed, 23 insertions(+), 3 deletions(-)
diff --git
Add the DMA controller node and DMA bindings to the supported devices.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun8i-a23.dtsi | 19 +++
1 file changed, 19 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi b/arch/arm/boot/dts/sun8i-a23.dtsi
index
This patch adds support for hardware parameters tied to compatible
strings, so similar hardware can reuse the driver.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
drivers/dma/sun6i-dma.c | 96 +++--
1 file changed, 61 insertions(+), 35 deletions
Could someone push this to u-boot-sunxi?
On Sat, Sep 13, 2014 at 2:36 AM, Hans de Goede hdego...@redhat.com wrote:
Hi,
On 09/12/2014 01:30 PM, Chen-Yu Tsai wrote:
This fixes the mmc code no longer working on sun8i after the changes to
stop using dma, like sun6i.
Signed-off-by: Chen-Yu Tsai
The MBUS clock on sun8i is slightly different from the old mod0 clocks.
The divider is 3 bits wider, while also needing a divider table for the
higher 4 values, which all set the same divider.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
Documentation/devicetree/bindings/clock/sunxi.txt | 1
message to patch 1
- Moved sun8i-mbus clk to separate file
Cheers
ChenYu
Chen-Yu Tsai (2):
clk: sunxi: Add sun8i MBUS clock support
ARM: dts: sun8i: Add PLL6 and MBUS clock nodes
Documentation/devicetree/bindings/clock/sunxi.txt | 1 +
arch/arm/boot/dts/sun8i-a23.dtsi | 29
Now that the clock driver supports PLL6 and MBUS on sun8i correctly,
add the corresponding clock nodes to the dtsi.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun8i-a23.dtsi | 29 +++--
1 file changed, 27 insertions(+), 2 deletions(-)
diff --git
On Tue, Sep 16, 2014 at 4:12 PM, Chen-Yu Tsai w...@csie.org wrote:
Hi,
This is v2 of my sun8i MBUS clock series.
This series depends on Maxime's clk: sunxi: Improve MMC clocks support
series, specifically the patches that change the factor clocks and move
out mod0 and mbus. Ideally
Now that the clock driver supports PLL6 and MBUS on sun8i correctly,
add the corresponding clock nodes to the dtsi.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun8i-a23.dtsi | 29 +++--
1 file changed, 27 insertions(+), 2 deletions(-)
diff --git
comment style
Changes since v1:
- Added commit message to patch 1
- Moved sun8i-mbus clk to separate file
Cheers
ChenYu
Chen-Yu Tsai (2):
clk: sunxi: Add sun8i MBUS clock support
ARM: dts: sun8i: Add PLL6 and MBUS clock nodes
Documentation/devicetree/bindings/clock/sunxi.txt | 1
The MBUS clock on sun8i is slightly different from the old mod0 clocks.
The divider is 3 bits wider, while also needing a divider table for the
higher 4 values, which all set the same divider.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
Documentation/devicetree/bindings/clock/sunxi.txt | 1
On Tue, Sep 16, 2014 at 6:35 PM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
On Sat, Sep 13, 2014 at 09:53:00PM +0800, Chen-Yu Tsai wrote:
The A23 SoC has the same dma engine as the A31 (sun6i), with a
reduced amount of endpoints and physical channels. Add the proper
config data
This is a Q8 format 7 inch tablet with an Allwinner A13 SoC.
It has 512MB DRAM, 4GB NAND flash, an accelerometer, camera,
RTL8188-based WiFi, and micro SD slot for external storage.
It is likely made by a subsidiary of Hanns.G (Hannstar).
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm
Most if not all boards we've seen have a fixed 5V regulator, which is
the main power supply and/or fixed output of the PMIC.
Add this one to the common regulators DTSI.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sunxi-common-regulators.dtsi | 7 +++
1 file changed, 7
changed commit title
Changes since v2:
- Dual license under GPL/X11.
- Use extra fixed regulator for usb1-vbus.
Chen-Yu Tsai (2):
ARM: dts: sunxi: Add fixed 5V regulator
ARM: dts: sun5i: Add DT for HSG H702 tablet board
arch/arm/boot/dts/Makefile | 1 +
arch/arm
On Wed, Sep 17, 2014 at 11:55 PM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
On Tue, Sep 16, 2014 at 10:13:27PM +0800, Chen-Yu Tsai wrote:
+ /*
+ * sun8i variant requires us to toggle an undocumented register,
+ * as seen in Allwinner's SDK.
The BSP I have has
gating registers, and updated
comment to reflect its usage.
Cheers
ChenYu
Chen-Yu Tsai (3):
dmaengine: sun6i: support parameterized compatible strings
dmaengine: sun6i: Add support for Allwinner A23 (sun8i) variant
ARM: dts: sun8i: Add DMA controller node
.../devicetree/bindings/dma/sun6i
-Yu Tsai w...@csie.org
---
.../devicetree/bindings/dma/sun6i-dma.txt | 2 +-
drivers/dma/Kconfig| 4 ++--
drivers/dma/sun6i-dma.c| 27 ++
3 files changed, 30 insertions(+), 3 deletions(-)
diff --git
Add the DMA controller node and DMA bindings to the supported devices.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun8i-a23.dtsi | 19 +++
1 file changed, 19 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi b/arch/arm/boot/dts/sun8i-a23.dtsi
index
This patch adds support for hardware parameters tied to compatible
strings, so similar hardware can reuse the driver.
Signed-off-by: Chen-Yu Tsai w...@csie.org
Acked-by: Maxime Ripard maxime.rip...@free-electrons.com
---
drivers/dma/sun6i-dma.c | 96
Hi,
On Thu, Sep 18, 2014 at 4:31 PM, Hans de Goede hdego...@redhat.com wrote:
Hi,
On 09/18/2014 06:27 AM, Siarhei Siamashka wrote:
On Tue, 09 Sep 2014 09:00:57 +0200
Hans de Goede hdego...@redhat.com wrote:
Hi,
On 09/08/2014 03:28 PM, Chen-Yu Tsai wrote:
Hi everyone,
This series add
On Sat, Sep 20, 2014 at 5:59 PM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
On Wed, Sep 17, 2014 at 12:01:46AM +0800, Chen-Yu Tsai wrote:
On Tue, Sep 16, 2014 at 11:48 PM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
On Fri, Sep 12, 2014 at 10:10:25AM +0800, Chen-Yu Tsai
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
fel.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/fel.c b/fel.c
index 97f265e..c34de19 100644
--- a/fel.c
+++ b/fel.c
@@ -167,6 +167,7 @@ void aw_fel_get_version(libusb_device_handle *usb)
case 0x1633: soc_name=A31;break;
case
On Sun, Sep 21, 2014 at 8:28 PM, Ian Campbell i...@hellion.org.uk wrote:
On Sun, 2014-09-21 at 16:43 +0800, Chen-Yu Tsai wrote:
FEL mode on the A80 changed the bulk transfer endpoint.
If we use the original binary, it timeouts waiting for
bulk transfer to be received, while the FEL BROM hangs
combo chip, a headphone
jack, IR receiver, and additional GPIO headers.
This patch adds only basic support.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/Makefile | 2 +
arch/arm/boot/dts/sun9i-a80-optimus.dts | 66 +
2 files changed
The uarts on sun9i are still compatible with the dw_8250, but are
located at different addresses.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/Kconfig.debug | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index b11ad54
Merrii Technology Co., Ltd. is a Chinese ARM integration developer that
specializes in Allwinner SoC based designs.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree
The Allwinner A80 is a new Cortex octo-core A7/A15 big.LITTLE SoC.
While it's processor cores and interconnecting bus are new, it
re-uses many peripherals found in earlier Allwinner SoCs.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/mach-sunxi/Kconfig | 5 +
arch/arm/mach-sunxi
The Allwinner A80 is a new multi-purpose SoC with 4 Cortex-A7 and
4 Cortex-A15 cores in a big.LITTLE architecture, and a 64-core
PowerVR G6230 GPU.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun9i-a80.dtsi | 280 +++
1 file changed, 280
This adds a list of supported Allwinner SoC bindings.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
Documentation/devicetree/bindings/arm/sunxi.txt | 12
1 file changed, 12 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/sunxi.txt
diff --git a/Documentation
of the A80 Optimus Board.
Patch 6 documents all the Allwinner SoCs we currently support.
Cheers
ChenYu
Chen-Yu Tsai (6):
ARM: sunxi: Introduce Allwinner A80 support
ARM: sunxi: Add debug uart used by sun9i (Allwinner A80)
ARM: dts: sunxi: Add Allwinner A80 dtsi
ARM: dts: sun9i: Add A80 Optimus
FEL mode on the A80 changed the bulk transfer endpoint.
Let the fel utility look for the endpoint addresses instead
of hard-coding them.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
fel.c | 49 +++--
1 file changed, 47 insertions(+), 2 deletions
a few days before pushing,
in case anyone has some suggestions.
Changes since v1:
- Dropped A80 specific build and detect endpoints at startup
Cheer
ChenYu
Chen-Yu Tsai (2):
fel: Add A80 SoC ID
fel: Detect FEL mode bulk transfer endpoint addresses at startup
fel.c | 50
On Mon, Sep 22, 2014 at 2:56 AM, Ian Campbell i...@hellion.org.uk wrote:
On Sun, 2014-09-21 at 23:42 +0800, Chen-Yu Tsai wrote:
FEL mode on the A80 changed the bulk transfer endpoint.
Let the fel utility look for the endpoint addresses instead
of hard-coding them.
Wow, the library really
Hi,
On Mon, Sep 22, 2014 at 1:05 AM, Ian Campbell i...@hellion.org.uk wrote:
On Mon, 2014-09-08 at 21:28 +0800, Chen-Yu Tsai wrote:
From: Oliver Schinagl oli...@schinagl.nl
To setup clocks and control voltages.
perhaps add ... For P2WI and PIO, since that is apparently what it is
doing
On Mon, Sep 22, 2014 at 2:44 AM, Ian Campbell i...@hellion.org.uk wrote:
On Mon, 2014-09-08 at 21:28 +0800, Chen-Yu Tsai wrote:
From: Hans de Goede hdego...@redhat.com
Signed-off-by: Hans de Goede hdego...@redhat.com
[w...@csie.org: use setbits_le32 for reset control, drop obsolete changes
On Mon, Sep 22, 2014 at 2:35 AM, Ian Campbell i...@hellion.org.uk wrote:
On Mon, 2014-09-08 at 21:28 +0800, Chen-Yu Tsai wrote:
+#ifdef CONFIG_SPL_BUILD
Since there is no SPL support this is dead code right now, correct?
This was part of Hans' attempt to support SPL. It was not finished
On Mon, Sep 22, 2014 at 9:15 PM, Ian Campbell i...@hellion.org.uk wrote:
On Mon, 2014-09-22 at 20:47 +0800, Chen-Yu Tsai wrote:
On Mon, Sep 22, 2014 at 2:35 AM, Ian Campbell i...@hellion.org.uk wrote:
On Mon, 2014-09-08 at 21:28 +0800, Chen-Yu Tsai wrote:
+ /* Set PLL ldo voltage without
On Mon, Sep 22, 2014 at 2:10 PM, Michael Trimarchi
mich...@amarulasolutions.com wrote:
Hi
Il 08/set/2014 15:36 Chen-Yu Tsai w...@csie.org ha scritto:
From: Maxime Ripard maxime.rip...@free-electrons.com
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
Signed-off-by: Hans de
On Mon, Sep 22, 2014 at 3:01 AM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
Hi Ian,
On Sun, Sep 21, 2014 at 07:51:17PM +0100, Ian Campbell wrote:
On Mon, 2014-09-08 at 21:28 +0800, Chen-Yu Tsai wrote:
From: Maxime Ripard maxime.rip...@free-electrons.com
Add a new sun6i machine
On Mon, Sep 22, 2014 at 10:11 AM, Chen-Yu Tsai w...@csie.org wrote:
On Mon, Sep 22, 2014 at 2:44 AM, Ian Campbell i...@hellion.org.uk wrote:
On Mon, 2014-09-08 at 21:28 +0800, Chen-Yu Tsai wrote:
From: Hans de Goede hdego...@redhat.com
Signed-off-by: Hans de Goede hdego...@redhat.com
[w
On Tue, Sep 23, 2014 at 7:54 PM, Ian Campbell i...@hellion.org.uk wrote:
On Tue, 2014-09-23 at 19:50 +0800, Chen-Yu Tsai wrote:
Ian, include/configs/sun?i.h and sunxi-common.h only have config
related #defines. Are we sure this is the place for something
like register offsets?
I guess
On Wed, Sep 24, 2014 at 2:37 PM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
Hi,
Thanks, a lot for your patches :)
On Sun, Sep 21, 2014 at 10:58:10PM +0800, Chen-Yu Tsai wrote:
The Allwinner A80 is a new multi-purpose SoC with 4 Cortex-A7 and
4 Cortex-A15 cores in a big.LITTLE
On Wed, Sep 24, 2014 at 3:18 PM, Gregory CLEMENT
gregory.clem...@free-electrons.com wrote:
Hi Chen-Yu,
+
+ memory {
+ reg = 0x2000 0x4000;
Usually, what we put there was the maximum amount of RAM that can be
handled by the SoC. I think that it can go above 1GB
From: Oliver Schinagl oli...@schinagl.nl
A31 has several new and changed memory address. This patch adds them.
Signed-off-by: Oliver Schinagl oli...@schinagl.nl
Signed-off-by: Hans de Goede hdego...@redhat.com
Signed-off-by: Chen-Yu Tsai w...@csie.org
Acked-by: Ian Campbell i...@hellion.org.uk
around mmc and smp code, drop MACH_TYPE]
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/Kconfig| 3 +++
arch/arm/cpu/armv7/sunxi/cpu_info.c | 2 ++
board/sunxi/Kconfig | 10 +-
include/configs/sun6i.h | 26
UART0 is the default debug/console UART on the A31.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/include/asm/arch-sunxi/gpio.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h
b/arch/arm/include/asm/arch-sunxi/gpio.h
index f7f3d8c..ba7e69b
setbits helper in PRCM init function]
[w...@csie.org: rephrase commit message to explain what the hardware
supports and what we actually enable]
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/cpu/armv7/sunxi/Makefile | 1 +
arch/arm/cpu/armv7/sunxi/prcm.c| 33
The Colombus board is an A31 evaluation board from WITS Technology.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
configs/Colombus_defconfig | 4
1 file changed, 4 insertions(+)
create mode 100644 configs/Colombus_defconfig
diff --git a/configs/Colombus_defconfig b/configs
We have already defined macros for pull-up/down values in the
GPIO header. Use them instead of magic numbers when configuring
the UART pins.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/cpu/armv7/sunxi/board.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git
BOOT_TARGET_DEVICES includes USB unconditionally. This breaks when
CONFIG_CMD_USB is not defined. Use a secondary macro to conditionally
include it when CONFIG_EHCI is enabled, as we do for CONFIG_AHCI.
Signed-off-by: Chen-Yu Tsai w...@csie.org
Acked-by: Ian Campbell i...@hellion.org.uk
,
rewrite different FIFO address handling, add commit message]
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/include/asm/arch-sunxi/mmc.h | 5 -
drivers/mmc/sunxi_mmc.c | 11 +++
2 files changed, 11 insertions(+), 5 deletions(-)
diff --git a/arch
hdego...@redhat.com
[w...@csie.org: styling fixes reported by checkpatch.pl]
[w...@csie.org: drop unsupported SPL code block and unused gpio.h header]
Signed-off-by: Chen-Yu Tsai w...@csie.org
Cc: Tom Cubie mr.hip...@gmail.com
---
arch/arm/cpu/armv7/sunxi/Makefile | 1 +
arch/arm/cpu
: replace magic numbers with GPIO definitions]
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/cpu/armv7/sunxi/board.c | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index 95a74c5..b6d63db 100644
--- a/arch/arm/cpu/armv7
)
- Rewrite patch 9 commit message to reflect what is supported
- Split out Colombus board defconfig into separate patch (patch 10)
Cheers
ChenYu
Chen-Yu Tsai (5):
ARM: sunxi: Use macro values for setting UART GPIO pull-ups
ARM: sunxi: Fix build break when CONFIG_USB_EHCI is not defined
ARM
Hi,
On Wed, Sep 24, 2014 at 2:41 PM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
Hi Chen-Yu,
On Sun, Sep 21, 2014 at 10:58:07PM +0800, Chen-Yu Tsai wrote:
Hi everyone,
This patch series adds very basic support for Allwinner's A80 SoC,
a big.LITTLE architecture with 4 Cortex-A7s
On Wed, Sep 24, 2014 at 3:18 PM, Gregory CLEMENT
gregory.clem...@free-electrons.com wrote:
Hi Chen-Yu,
+
+ memory {
+ reg = 0x2000 0x4000;
Usually, what we put there was the maximum amount of RAM that can be
handled by the SoC. I think that it can go above 1GB
Hi Maxime, Emilio,
On Tue, Sep 16, 2014 at 11:57 PM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
Hi Emilio,
On Sat, Sep 13, 2014 at 11:43:46AM -0300, Emilio López wrote:
Hi,
El 06/09/14 a las 07:47, Chen-Yu Tsai escibió:
Some factor clocks, mostly PLLs, have an extra fixed
On Fri, Sep 26, 2014 at 8:25 AM, Mike Turquette mturque...@linaro.org wrote:
Quoting Maxime Ripard (2014-09-11 13:36:23)
Hi Chen-Yu,
On Sat, Sep 06, 2014 at 06:47:21PM +0800, Chen-Yu Tsai wrote:
Hi everyone,
This series unifies the mux and divider parts of the AHB1 clock found
on sun6i
On Thu, Sep 18, 2014 at 11:24 AM, Chen-Yu Tsai w...@csie.org wrote:
Hi everyone,
This is v2 of my sun8i DMA controller support series. This series
adds support for the DMA controller found in the Allwinner A23 SoC.
It is the same hardware as found in the A31 (sun6i) SoC. In addition
On Sat, Sep 27, 2014 at 3:07 PM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
On Wed, Sep 24, 2014 at 11:35:58PM +0800, Chen-Yu Tsai wrote:
Hi Maxime, Emilio,
On Tue, Sep 16, 2014 at 11:57 PM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
Hi Emilio,
On Sat, Sep 13, 2014
On Sun, Sep 28, 2014 at 11:33 PM, Ian Campbell i...@hellion.org.uk wrote:
On Thu, 2014-09-25 at 20:09 +0100, Ian Campbell wrote:
On Wed, 2014-09-24 at 16:01 +0800, Chen-Yu Tsai wrote:
The Colombus board is an A31 evaluation board from WITS Technology.
Signed-off-by: Chen-Yu Tsai w
Hi,
On Fri, Oct 3, 2014 at 3:29 AM, jonsm...@gmail.com jonsm...@gmail.com wrote:
I
On Thu, Oct 2, 2014 at 1:19 PM, Christian Ege k423...@gmail.com wrote:
During a quick search I had not been able to find any HDMI CEC driver. In
the docs available there is only one Register about CEC.
I
From: Oliver Schinagl oli...@schinagl.nl
A31 has several new and changed memory address. This patch adds them.
Signed-off-by: Oliver Schinagl oli...@schinagl.nl
Signed-off-by: Hans de Goede hdego...@redhat.com
Signed-off-by: Chen-Yu Tsai w...@csie.org
Acked-by: Ian Campbell i...@hellion.org.uk
setbits helper in PRCM init function]
[w...@csie.org: rephrase commit message to explain what the hardware
supports and what we actually enable]
Signed-off-by: Chen-Yu Tsai w...@csie.org
Acked-by: Ian Campbell i...@hellion.org.uk
---
arch/arm/cpu/armv7/sunxi/Makefile | 1 +
arch
UART0 is the default debug/console UART on the A31.
Signed-off-by: Chen-Yu Tsai w...@csie.org
Acked-by: Ian Campbell i...@hellion.org.uk
---
arch/arm/include/asm/arch-sunxi/gpio.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h
b/arch/arm/include
The Colombus board is an A31 evaluation board from WITS Technology.
Maxime has kindly agreed to maintain this board.
[1] http://lists.denx.de/pipermail/u-boot/2014-September/190043.html
Signed-off-by: Chen-Yu Tsai w...@csie.org
Cc: Maxime Ripard maxime.rip...@free-electrons.com
---
board/sunxi
: replace magic numbers with GPIO definitions]
Signed-off-by: Chen-Yu Tsai w...@csie.org
Acked-by: Ian Campbell i...@hellion.org.uk
---
arch/arm/cpu/armv7/sunxi/board.c | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index
around mmc and smp code, drop MACH_TYPE]
Signed-off-by: Chen-Yu Tsai w...@csie.org
Acked-by: Ian Campbell i...@hellion.org.uk
---
arch/arm/Kconfig| 3 +++
arch/arm/cpu/armv7/sunxi/cpu_info.c | 2 ++
board/sunxi/Kconfig | 10 +-
include/configs
hdego...@redhat.com
[w...@csie.org: styling fixes reported by checkpatch.pl]
[w...@csie.org: drop unsupported SPL code block and unused gpio.h header]
Signed-off-by: Chen-Yu Tsai w...@csie.org
Cc: Tom Cubie mr.hip...@gmail.com
Acked-by: Ian Campbell i...@hellion.org.uk
---
arch/arm/cpu/armv7/sunxi
,
rewrite different FIFO address handling, add commit message]
Signed-off-by: Chen-Yu Tsai w...@csie.org
Acked-by: Ian Campbell i...@hellion.org.uk
---
arch/arm/include/asm/arch-sunxi/mmc.h | 5 -
drivers/mmc/sunxi_mmc.c | 11 +++
2 files changed, 11
BOOT_TARGET_DEVICES includes USB unconditionally. This breaks when
CONFIG_CMD_USB is not defined. Use a secondary macro to conditionally
include it when CONFIG_EHCI is enabled, as we do for CONFIG_AHCI.
Signed-off-by: Chen-Yu Tsai w...@csie.org
Acked-by: Ian Campbell i...@hellion.org.uk
reserved area to adjust for sun6i's different fifo address
(patch 6)
- Rewrite patch 9 commit message to reflect what is supported
- Split out Colombus board defconfig into separate patch (patch 10)
Cheers
ChenYu
Chen-Yu Tsai (5):
ARM: sunxi: Use macro values for setting UART GPIO pull
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