[linux-sunxi] Re: Allwinner SID THS calibration data cell representation?

2019-02-25 Thread Philipp Rossak




On 19.02.19 08:54, Chen-Yu Tsai wrote:

Sorry for resurrecting an old discussion, but since someone posted patches
for H5 and H6, I thought we should resolve this. I'm working on patches to
fix / replace the big-endian issue.

On Thu, Sep 6, 2018 at 7:51 PM Maxime Ripard  wrote:


On Thu, Sep 06, 2018 at 01:47:47PM +0200, Philipp Rossak wrote:

On 04.09.2018 18:46, Emmanuel Vadot wrote:

+ /* Data cells */
+ thermal_calibration: calib@234 {
+ reg = <0x234 0x8>;
+ };

   You are declaring 8 bytes of calibration data but to my knowledge it's
only 2 bytes per sensor, so 2 bytes for H3.
   Am I missing something ?

   Thanks,


Emmanuel you are right, it is 2 bytes per Sensor and should be 2 bytes for
H3, but the thermal calibration data field is on all chips 64 bit wide - so
8 bytes. So I'm reading here the complete calibration data field.


Having one cell per channel would make more sense I guess.


Would it? The 2 32-bit words directly map onto the registers 0x74 / 0x78 in
the THS. As far as the SID is concerned, their is just one consumer for this
data, the thermal sensor. How the thermal sensor uses that data is really not
its concern. And the thermal sensor is really just copying the data from the
e-fuses into its registers. Nothing more.


Using 2 32-bit words for the THS would be also ok (from my perspective).


Furthermore, with the register access interface, the e-fuses are read/write
32 bits at a time. Seems to me it would make more sense to enforce a 32-bit
word size, so cells should be multiples of 32 bits.


For THS I'm ok with that.


Regards
ChenYu


Regards,
Philipp

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Re: [linux-sunxi] Re: [PATCH v3 27/30] ARM: dts: sun8i: h3: use calibration for ths

2018-09-06 Thread Philipp Rossak




On 06.09.2018 14:04, Icenowy Zheng wrote:



于 2018年9月6日 GMT+08:00 下午7:51:15, Maxime Ripard  写到:

On Thu, Sep 06, 2018 at 01:47:47PM +0200, Philipp Rossak wrote:

On 04.09.2018 18:46, Emmanuel Vadot wrote:

+   /* Data cells */
+   thermal_calibration: calib@234 {
+   reg = <0x234 0x8>;
+   };

   You are declaring 8 bytes of calibration data but to my knowledge

it's

only 2 bytes per sensor, so 2 bytes for H3.
   Am I missing something ?

   Thanks,


Emmanuel you are right, it is 2 bytes per Sensor and should be 2

bytes for

H3, but the thermal calibration data field is on all chips 64 bit

wide - so

8 bytes. So I'm reading here the complete calibration data field.


Having one cell per channel would make more sense I guess.

Ok I will change this.


I have mentioned that this is impossible because of wrong
addressing caused by LE2BE in SID driver.

I know! But I would like to prepare patches for it, that they can be 
merged when this is fixed.


Philipp

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[linux-sunxi] Re: [PATCH v3 27/30] ARM: dts: sun8i: h3: use calibration for ths

2018-09-06 Thread Philipp Rossak

On 04.09.2018 18:46, Emmanuel Vadot wrote:

+   /* Data cells */
+   thermal_calibration: calib@234 {
+   reg = <0x234 0x8>;
+   };

  You are declaring 8 bytes of calibration data but to my knowledge it's
only 2 bytes per sensor, so 2 bytes for H3.
  Am I missing something ?

  Thanks,


Emmanuel you are right, it is 2 bytes per Sensor and should be 2 bytes 
for H3, but the thermal calibration data field is on all chips 64 bit 
wide - so 8 bytes. So I'm reading here the complete calibration data field.


Philipp

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[linux-sunxi] Re: [PATCH v3 30/30] ARM: sun8i: a83t: full range OPP tables and CPUfreq

2018-09-06 Thread Philipp Rossak

On 06.09.2018 09:24, Quentin Schulz wrote:

Hi Philipp,

On Thu, Aug 30, 2018 at 05:45:18PM +0200, Philipp Rossak wrote:

Since we have now thermal trotteling enabeled we can now add the full
range of the OPP table.


That's not the reason why they were not added.

Please see commit 2db639d8c1663d7543c9ab5323383d94c8a76c63[1].

Basically, you only want the OPPs which can work below or at the default
voltage of the CPU supply, because the CPU supply is specific to each
board.

If you set your CPU to work at a given frequency and the voltage isn't
updated (saying opp-microvolt = ; in DT isn't enough, you need
cpu-supply to be provided and functional), the CPU might just crash.

Without cpu-supply property, underclocking isn't effective in term of
thermal cooling or power saving. Overclocking is very, very, very likely
to make the CPU crash.

It's not a very difficult thing to do to test if a given frequency work
well but it needs a specific test environment and it's a lengthy test,
you can have a look at those tools here[3] if you like. It's not because
it works in a given test case that'll work on the long term under heavy
load and constant frequency changes.

For A83T, I already did it and the outcome is the patch in [1]. Same for
A33.

So, if you want to use these three higher OPPs, you need to define them
in your board DTS and add the cpu-supply property. See what's done for
the A33 and more specifically the Sinlinx SinA33[2] as an example.

[1]https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=2db639d8c1663d7543c9ab5323383d94c8a76c63
[2]https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm/boot/dts/sun8i-a33-sinlinx-sina33.dts
[3]http://linux-sunxi.org/Hardware_Reliability_Tests#CPU

Quentin



Hey Quentin,

thanks for your feedback!

Sounds like we will never be able to run the A83T on its maximum 
frequency in mainline.


I will do some testing, during the next weeks/months when I have time.
With the old Allwinner kernel I was able to run the A83T with its 
maximum frequency without any problems since my board is very good cooled.


For now I will drop this patch.

Philipp

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[linux-sunxi] Re: [PATCH v3 05/30] iio: adc: move SUN4I_GPADC_CHANNEL define to header file

2018-09-03 Thread Philipp Rossak

On 02.09.2018 22:01, Jonathan Cameron wrote:

On Thu, 30 Aug 2018 17:44:53 +0200
Philipp Rossak  wrote:


We are moving the SUN4I_GPADC_CHANNEL define to the header file.

Maxime has raised this point in other patches...

Why?  Obvious what but I have no idea why you are doing this.

Thanks,

Jonathan

There are two reasons:
1. Personal taste: I like to have the #define stuff in the header file.
2. When I started the rework I had to get some better overview, so I 
moved it...


Since those two reasons are no good reasons to submit a patch I will 
drop it and keep it in the *.c file.


Philipp



Signed-off-by: Philipp Rossak 
---
  drivers/iio/adc/sun4i-gpadc-iio.c | 9 -
  include/linux/mfd/sun4i-gpadc.h   | 9 +
  2 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c 
b/drivers/iio/adc/sun4i-gpadc-iio.c
index d95dd0fde2a6..666329940e1e 100644
--- a/drivers/iio/adc/sun4i-gpadc-iio.c
+++ b/drivers/iio/adc/sun4i-gpadc-iio.c
@@ -109,15 +109,6 @@ struct sun4i_gpadc_iio {
struct device   *sensor_device;
  };
  
-#define SUN4I_GPADC_ADC_CHANNEL(_channel, _name) {		\

-   .type = IIO_VOLTAGE,\
-   .indexed = 1,   \
-   .channel = _channel,\
-   .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),   \
-   .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),   \
-   .datasheet_name = _name,\
-}
-
  static struct iio_map sun4i_gpadc_hwmon_maps[] = {
{
.adc_channel_label = "temp_adc",
diff --git a/include/linux/mfd/sun4i-gpadc.h b/include/linux/mfd/sun4i-gpadc.h
index 139872c2e0fe..54c7c9375c1b 100644
--- a/include/linux/mfd/sun4i-gpadc.h
+++ b/include/linux/mfd/sun4i-gpadc.h
@@ -90,6 +90,15 @@
  /* 10s delay before suspending the IP */
  #define SUN4I_GPADC_AUTOSUSPEND_DELAY 1
  
+#define SUN4I_GPADC_ADC_CHANNEL(_channel, _name) {		\

+   .type = IIO_VOLTAGE,\
+   .indexed = 1,   \
+   .channel = _channel,\
+   .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),   \
+   .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),   \
+   .datasheet_name = _name,\
+}
+
  struct sun4i_gpadc_dev {
struct device   *dev;
struct regmap   *regmap;




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[linux-sunxi] Re: [PATCH v3 18/30] iio: adc: sun4i-gpadc-iio: rework: support multiple sensors

2018-09-03 Thread Philipp Rossak

On 02.09.2018 22:11, Jonathan Cameron wrote:

This feels like a good place to factor out the code into a utility
function that just does one of them.  That should hopefully
reduce the indenting etc enough to make the code easier to read.


+   info->tzds[i].info = info;
+   info->tzds[i].sensor_id = i;
+
+   info->tzds[i].tzd = thermal_zone_of_sensor_register(
+   info->sensor_device,
+   i, >tzds[i], _ts_tz_ops);
+   /*
+* Do not fail driver probing when failing to register in
+* thermal because no thermal DT node is found.
+*/
+   if (IS_ERR(info->tzds[i].tzd) && \
+   PTR_ERR(info->tzds[i].tzd) != -ENODEV) {
+   dev_err(>dev,
+   "could not register thermal sensor: %ld\n",
+   PTR_ERR(info->tzds[i].tzd));
+   return PTR_ERR(info->tzds[i].tzd);
+   }


So this code above should be placed in a separate function and called by 
the for loop?

Did I understand that right?

Philipp

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[linux-sunxi] Re: [PATCH v3 20/30] iio: adc: sun4i-gpadc-iio: rework: device specific suspend & resume

2018-08-31 Thread Philipp Rossak




On 31.08.2018 11:09, Maxime Ripard wrote:

+static int sun4i_ths_suspend(struct sun4i_gpadc_iio *info)

suspend is already a hook in the kernel, which hasn't the same meaning
than runtime_suspend (and the same applies to resume), so we'd rather
pick a better name. And all the functions (and the driver) use gpadc,
please continue to use that prefix.


I agree.
For the newer sensors (from H3) the Sensor is referenced in the 
datasheets as Thermal Sensor short THS. So I would like to use for the 
newer sensors that prefix. Is that ok?


Philipp

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[linux-sunxi] Re: [PATCH v3 21/30] iio: adc: sun4i-gpadc-iio: add support for H3 thermal sensor

2018-08-31 Thread Philipp Rossak

On 31.08.2018 11:11, Maxime Ripard wrote:

+   regmap_write(info->regmap, SUN8I_H3_THS_CTRL0,
+   SUN4I_GPADC_CTRL0_T_ACQ(0xff));
+
+   regmap_write(info->regmap, SUN8I_H3_THS_CTRL2,
+   SUN8I_H3_THS_ACQ1(0x3f));
+
+   regmap_write(info->regmap, SUN8I_H3_THS_STAT,
+   SUN8I_H3_THS_INTS_TDATA_IRQ_0);
+
+   regmap_write(info->regmap, SUN8I_H3_THS_FILTER,
+   SUN4I_GPADC_CTRL3_FILTER_EN |
+   SUN4I_GPADC_CTRL3_FILTER_TYPE(0x2));
+
+   regmap_write(info->regmap, SUN8I_H3_THS_INTC,
+   SUN8I_H3_THS_INTC_TDATA_IRQ_EN0 |
+   SUN8I_H3_THS_TEMP_PERIOD(0x55));
+
+   regmap_read(info->regmap, SUN8I_H3_THS_CTRL2, );
+
+   regmap_write(info->regmap, SUN8I_H3_THS_CTRL2,
+   SUN8I_H3_THS_TEMP_SENSE_EN0 | value);

Ideally, all these values should have a comment explaining what they
are.

And we really start to have a lot of registers defines. We'd be better
off using regmap_fields.


I will rework this in the next version.

Thanks,
Philipp

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Re: [linux-sunxi] Re: [PATCH v3 21/30] iio: adc: sun4i-gpadc-iio: add support for H3 thermal sensor

2018-08-31 Thread Philipp Rossak




On 31.08.2018 11:51, Icenowy Zheng wrote:

Personally I suggest to leave out all SID or calibration related
patches here.

Currently we seems to be wrongly converting SID to big endian, however,
the orgnization of the THS calibration data on H6 shows that it's
surely little endian:

It consists a temperature value in 1/10 celsuis as unit, and some
thermal register readout values, which are the values read out at the
given temperature, and every value here (the temperature and the
readout) are all half word length.

Let the temperature value be AABB, the two readout values be XXYY and
ZZWW, the oragnization is:
BB AA YY XX WW ZZ ** ** .

When converting the SID to big endian, it becomes:
XX YY AA BB ** ** ZZ WW ,
which is non-sense, and not able to do sub-word cell addressing.

Maxime, should I drop the LE2BE conversion in SID driver? (I doubt
whether it will break compatibility.)

Philipp, could you delay to send any code that uses SID?


Yes for sure! I will move the related patches to the end of the series 
and add a DO-NOT-MERGE flag in the title. So I can get those also 
ready/reviewed but not merged.


Icenowy, do you know more about the A83T SID? From the general specs it 
could be the same like on the A64 or the H3.


Thanks,
Philipp

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Re: [linux-sunxi] [PATCH v3 21/30] iio: adc: sun4i-gpadc-iio: add support for H3 thermal sensor

2018-08-30 Thread Philipp Rossak




On 30.08.2018 22:00, Philipp Rossak wrote:

On 30.08.2018 18:27, Ondřej Jirman wrote:

+static int sun8i_h3_calibrate(struct sun4i_gpadc_iio *info)
+{
+//    regmap_write(info->regmap, SUNXI_THS_CDATA_0_1,
+//    info->calibration_data[0]);
+//    regmap_write(info->regmap, SUNXI_THS_CDATA_2_3,
+//    info->calibration_data[1]);

This should probably be implemented, or left out completely.

regards,
   o.


Thanks you are right!
This should be implemented! I will fix this in the next version!

Thanks,
Philipp


I just realized this function need to check if calibration datas are 
available. Writing zeros to the calibration data regs "breaks" the 
thermal sensor.


Philipp

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Re: [linux-sunxi] [PATCH v3 30/30] ARM: sun8i: a83t: full range OPP tables and CPUfreq

2018-08-30 Thread Philipp Rossak

On 30.08.2018 18:38, Ondřej Jirman wrote:

Hello,

On Thu, Aug 30, 2018 at 05:45:18PM +0200, Philipp Rossak wrote:

Since we have now thermal trotteling enabeled we can now add the full
range of the OPP table.


I'm not sure we can. I have a tablet with A83T SoC and it gets unstable
at these frequencies even with thermal throttling on mainline kernel. (Though
I have my own THS driver, but I doubt a different driver will change much.)

There might be some other issue left in the cpufreq code. I'll let others
test this on a better cooled boards though.

Did you/someone test this?

regards,
   o.
I have a good cooled device, with big heatsinks and a fan blowing 
directly on it. But there is some big issue left!


cat /sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_max_freq
[   85.076270] Unable to handle kernel paging request at virtual address 
2e83c684

[   85.083519] pgd = (ptrval)
[   85.086220] [2e83c684] *pgd=
[   85.089813] Internal error: Oops: 5 [#3] SMP ARM
[   85.094429] Modules linked in:
[   85.097483] CPU: 4 PID: 127 Comm: sh Tainted: G  D W 
4.18.0-00031-g8f59917020b9-dirty #2

[   85.106597] Hardware name: Allwinner A83t board
[   85.30] PC is at down_write+0x14/0x54
[   85.115135] LR is at anon_vma_clone+0x9c/0x1e4
[   85.119571] pc : []lr : []psr: 6013
[   85.125826] sp : ede45e70  ip : 01a0  fp : eea3c690
[   85.131041] r10: eea4193c  r9 : 00400200  r8 : c0a942a4
[   85.136255] r7 : 2e83c680  r6 : eea3aea0  r5 : eea3b220  r4 : 2e83c684
[   85.142771] r3 : 0001  r2 : 2e83c680  r1 : ede45e58  r0 : 2e83c684
[   85.149287] Flags: nZCv  IRQs on  FIQs on  Mode SVC_32  ISA ARM 
Segment none

[   85.156410] Control: 10c5387d  Table: 6df1806a  DAC: 0051
[   85.162145] Process sh (pid: 127, stack limit = 0x(ptrval))
[   85.167706] Stack: (0xede45e70 to 0xede46000)
[   85.172057] 5e60: eea3b900 
c01e71b8 eea41900 ffebd684
[   85.180221] 5e80: c0a637b0 c07ea07c c0a10754 eea3aea0 eea41900 
c0a04c48 edd71880 
[   85.188385] 5ea0: eea3aea0 eea41900 c0a69030 c01e7324 0002 
edd701c0 c0a04c48 edd71880
[   85.196548] 5ec0:  c011c2f4 0069  0002 
  
[   85.204711] 5ee0:  edd701c0 edd82280 eea3af00 edd701f8 
edd718b8 eea3af08 eea3af14
[   85.212875] 5f00: eea3af10 ede44000 edd8255c 01200011  
ede45f14 ede45f14 b61ea11a
[   85.221039] 5f20: edd805c0 01200011 c0a04c48 beef38b0  
  0078
[   85.229202] 5f40: beef38dc c011ce0c    
ede44000 00ae c012d9e0
[   85.237365] 5f60: eea43480  0400 b61ea11a  
b6fb5068 b6f8b670 beef38b0
[   85.245529] 5f80: 0078 c0101204 ede44000 0078 beef38dc 
c011d1bc b6fb5068 
[   85.253692] 5fa0: 00ae c0101000 b6fb5068 b6f8b670 01200011 
  
[   85.261856] 5fc0: b6fb5068 b6f8b670 beef38b0 0078 b6f8ac4c 
b6fb5490  beef38dc
[   85.270020] 5fe0: 0002 beef38b0  b6f5bfd0 6010 
01200011  
[   85.278191] [] (down_write) from [] 
(anon_vma_clone+0x9c/0x1e4)
[   85.285836] [] (anon_vma_clone) from [] 
(anon_vma_fork+0x24/0x160)
[   85.293741] [] (anon_vma_fork) from [] 
(copy_process.part.3+0xbc4/0x158c)
[   85.302253] [] (copy_process.part.3) from [] 
(_do_fork+0xb0/0x394)
[   85.310157] [] (_do_fork) from [] 
(sys_clone+0x20/0x28)
[   85.317107] [] (sys_clone) from [] 
(ret_fast_syscall+0x0/0x54)

[   85.324661] Exception stack(0xede45fa8 to 0xede45ff0)
[   85.329704] 5fa0:   b6fb5068 b6f8b670 01200011 
  
[   85.337868] 5fc0: b6fb5068 b6f8b670 beef38b0 0078 b6f8ac4c 
b6fb5490  beef38dc

[   85.346021] 5fe0: 0002 beef38b0  b6f5bfd0
[   85.351068] Code: e1a04000 f590f000 e3a03001 e34f3fff (e1902f9f)
[   85.357200] ---[ end trace aad10e0b4fcbf194 ]---


OR

cat /sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_cur_freq
[   73.873939] [ cut here ]
[   73.878584] WARNING: CPU: 5 PID: 132 at mm/rmap.c:235 
unlink_anon_vmas+0x1f4/0x1fc

[   73.886210] Modules linked in:
[   73.889276] CPU: 5 PID: 132 Comm: sh Tainted: G  D 
4.18.0-00031-g8f59917020b9-dirty #2

[   73.898391] Hardware name: Allwinner A83t board
[   73.902934] [] (unwind_backtrace) from [] 
(show_stack+0x10/0x14)
[   73.910671] [] (show_stack) from [] 
(dump_stack+0x84/0x98)
[   73.917887] [] (dump_stack) from [] 
(__warn+0xfc/0x114)
[   73.924840] [] (__warn) from [] 
(warn_slowpath_null+0x40/0x48)
[   73.932398] [] (warn_slowpath_null) from [] 
(unlink_anon_vmas+0x1f4/0x1fc)
[   73.941006] [] (unlink_anon_vmas) from [] 
(free_pgtables+0x78/0xcc)
[   73.948999] [] (free_pgtables) from [] 
(exit_mmap+0xe4/0x188)

[   73.956471] [] (exit_mmap) from [] (mmput+0x40/0xf0)
[   73.963169] [] (mmput) from [] 
(flush_old_exec+0x550/0x6e0)
[   73.970473] [] (flush_old_exec) from [] 
(load_elf_binary+0x2f0/0x1324)
[   73.978726] [] (load_elf_binary) from

Re: [linux-sunxi] [PATCH v3 21/30] iio: adc: sun4i-gpadc-iio: add support for H3 thermal sensor

2018-08-30 Thread Philipp Rossak

On 30.08.2018 18:27, Ondřej Jirman wrote:

+static int sun8i_h3_calibrate(struct sun4i_gpadc_iio *info)
+{
+// regmap_write(info->regmap, SUNXI_THS_CDATA_0_1,
+// info->calibration_data[0]);
+// regmap_write(info->regmap, SUNXI_THS_CDATA_2_3,
+// info->calibration_data[1]);

This should probably be implemented, or left out completely.

regards,
   o.


Thanks you are right!
This should be implemented! I will fix this in the next version!

Thanks,
Philipp

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[linux-sunxi] [PATCH v3 19/30] iio: adc: sun4i-gpadc-iio: rework: support nvmem calibration data

2018-08-30 Thread Philipp Rossak
This patch reworks the driver to support nvmem calibration cells.
The driver checks if the nvmem calibration is supported and reads out
the nvmem.

Signed-off-by: Philipp Rossak 
---
 drivers/iio/adc/sun4i-gpadc-iio.c | 24 
 1 file changed, 24 insertions(+)

diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c 
b/drivers/iio/adc/sun4i-gpadc-iio.c
index 18ab72e52d78..2fd73d143815 100644
--- a/drivers/iio/adc/sun4i-gpadc-iio.c
+++ b/drivers/iio/adc/sun4i-gpadc-iio.c
@@ -27,6 +27,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -70,6 +71,7 @@ struct gpadc_data {
boolhas_mod_clk;
u32 temp_data_base;
int sensor_count;
+   boolsupports_nvmem;
 };
 
 static irqreturn_t sun4i_gpadc_data_irq_handler(int irq, void *dev_id);
@@ -146,6 +148,7 @@ struct sun4i_gpadc_iio {
struct clk  *bus_clk;
struct clk  *mod_clk;
struct reset_control*reset;
+   u32 calibration_data[2];
 };
 
 static const struct iio_chan_spec sun4i_gpadc_channels[] = {
@@ -484,6 +487,9 @@ static int sun4i_gpadc_probe_dt(struct platform_device 
*pdev,
struct resource *mem;
void __iomem *base;
int ret;
+   struct nvmem_cell *cell;
+   ssize_t cell_size;
+   u32 *cell_data;
 
info->data = of_device_get_match_data(>dev);
if (!info->data)
@@ -494,6 +500,24 @@ static int sun4i_gpadc_probe_dt(struct platform_device 
*pdev,
if (IS_ERR(base))
return PTR_ERR(base);
 
+   if (info->data->supports_nvmem) {
+
+   cell = nvmem_cell_get(>dev, "calibration");
+   if (IS_ERR(cell)) {
+   if (PTR_ERR(cell) == -EPROBE_DEFER)
+   return PTR_ERR(cell);
+   } else {
+   cell_data = (u32 *)nvmem_cell_read(cell, _size);
+   if (cell_size != 8)
+   dev_err(>dev,
+   "Calibration data has wrong size\n");
+   else {
+   info->calibration_data[0] = cell_data[0];
+   info->calibration_data[1] = cell_data[1];
+   }
+   }
+   }
+
if (info->data->has_bus_clk)
info->regmap = devm_regmap_init_mmio_clk(>dev, "bus",
base, _gpadc_regmap_config);
-- 
2.11.0

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[linux-sunxi] [PATCH v3 25/30] ARM: dts: sun8i: h3: add thermal zone to H3

2018-08-30 Thread Philipp Rossak
This patch adds the thermal zones to the H3. We have only one sensor and
that is placed in the cpu.

Signed-off-by: Philipp Rossak 
---
 arch/arm/boot/dts/sun8i-h3.dtsi| 31 +++
 arch/arm/boot/dts/sunxi-h3-h5.dtsi |  1 +
 2 files changed, 32 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 5b7994cb1471..954848d5df50 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -78,6 +78,8 @@
clock-names = "cpu";
operating-points-v2 = <_opp_table>;
#cooling-cells = <2>;
+   cooling-min-level = <0>;
+   cooling-max-level = <15>;
};
 
cpu@1 {
@@ -102,6 +104,35 @@
};
};
 
+   thermal-zones {
+   cpu-thermal {
+   /* milliseconds */
+   polling-delay-passive = <250>;
+   polling-delay = <1000>;
+   thermal-sensors = <>;
+
+   trips {
+   cpu_hot_trip: cpu-warm {
+   temperature = <65000>;
+   hysteresis = <2000>;
+   type = "passive";
+   };
+   cpu_very_hot_trip: cpu-very-hot {
+   temperature = <9>;
+   hysteresis = <2000>;
+   type = "critical";
+   };
+   };
+
+   cooling-maps {
+   cpu-warm-limit {
+   trip = <_hot_trip>;
+   cooling-device = < 
THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+   };
+   };
+   };
+   };
+
timer {
compatible = "arm,armv7-timer";
interrupts = ,
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi 
b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index 3520e4ad6042..2c83f4893757 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -47,6 +47,7 @@
 #include 
 #include 
 #include 
+#include 
 
 / {
interrupt-parent = <>;
-- 
2.11.0

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[linux-sunxi] [PATCH v3 24/30] ARM: dts: sun8i: h3: add support for the thermal sensor in H3

2018-08-30 Thread Philipp Rossak
This patch adds the missing compatible and the thermal sensor cells.
The H3 has one sensor.

Signed-off-by: Philipp Rossak 
---
 arch/arm/boot/dts/sun8i-h3.dtsi | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 41d57c76f290..5b7994cb1471 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -185,3 +185,8 @@
  {
compatible = "allwinner,sun8i-h3-pinctrl";
 };
+
+ {
+   compatible = "allwinner,sun8i-h3-ths";
+   #thermal-sensor-cells = <0>;
+};
-- 
2.11.0

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[linux-sunxi] [PATCH v3 27/30] ARM: dts: sun8i: h3: use calibration for ths

2018-08-30 Thread Philipp Rossak
The H3 SID is supported by the kernel so we can add a NVMEM Data cell,
that contains the calibration data.

On the H3 the eFuses are located at the offset 0x200. The thermal data
itself has an offset of 0x34 from the eFuse base. So we end on an offset
of 0x234.

Signed-off-by: Philipp Rossak 
---
 arch/arm/boot/dts/sun8i-h3.dtsi | 9 +
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 1866aec69ec1..0fc447f0c02a 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -106,8 +106,15 @@
 
soc {
sid: eeprom@1c14000 {
+   #address-cells = <1>;
+   #size-cells = <1>;
compatible = "allwinner,sun8i-h3-sid";
reg = <0x01c14000 0x400>;
+
+   /* Data cells */
+   thermal_calibration: calib@234 {
+   reg = <0x234 0x8>;
+   };
};
};
 
@@ -227,4 +234,6 @@
  {
compatible = "allwinner,sun8i-h3-ths";
#thermal-sensor-cells = <0>;
+   nvmem-cells = <_calibration>;
+   nvmem-cell-names = "calibration";
 };
-- 
2.11.0

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[linux-sunxi] [PATCH v3 30/30] ARM: sun8i: a83t: full range OPP tables and CPUfreq

2018-08-30 Thread Philipp Rossak
Since we have now thermal trotteling enabeled we can now add the full
range of the OPP table.

The operating points were found in Allwinner BSP and fex files.

Signed-off-by: Philipp Rossak 
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 32 
 1 file changed, 32 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 78aa448e869f..ddcf404f9c80 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -250,6 +250,22 @@
opp-microvolt = <84>;
clock-latency-ns = <244144>; /* 8 32k periods */
};
+
+   opp-160800 {
+   opp-hz = /bits/ 64 <160800>;
+   opp-microvolt = <92>;
+   clock-latency-ns = <244144>; /* 8 32k periods */
+   };
+   opp-18 { /* BOOT FREQ */
+   opp-hz = /bits/ 64 <18>;
+   opp-microvolt = <100>;
+   clock-latency-ns = <244144>; /* 8 32k periods */
+   };
+   opp-201600 {
+   opp-hz = /bits/ 64 <201600>;
+   opp-microvolt = <108>;
+   clock-latency-ns = <244144>; /* 8 32k periods */
+   };
};
 
cpu1_opp_table: opp_table1 {
@@ -303,6 +319,22 @@
opp-microvolt = <84>;
clock-latency-ns = <244144>; /* 8 32k periods */
};
+
+   opp-160800 {
+   opp-hz = /bits/ 64 <160800>;
+   opp-microvolt = <92>;
+   clock-latency-ns = <244144>; /* 8 32k periods */
+   };
+   opp-18 { /* BOOT FREQ */
+   opp-hz = /bits/ 64 <18>;
+   opp-microvolt = <100>;
+   clock-latency-ns = <244144>; /* 8 32k periods */
+   };
+   opp-201600 {
+   opp-hz = /bits/ 64 <201600>;
+   opp-microvolt = <108>;
+   clock-latency-ns = <244144>; /* 8 32k periods */
+   };
};
 
soc {
-- 
2.11.0

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[linux-sunxi] [PATCH v3 29/30] ARM: dts: sun8i: a83t: add thermal zone to A83T

2018-08-30 Thread Philipp Rossak
This patch adds the thermal zones to the A83T. Sensor 0 is located
besides the cpu cluster 0. Sensor 1 is located besides cluster 1 and
sensor 2 is located besides in the gpu.

Signed-off-by: Philipp Rossak 
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 103 ++
 1 file changed, 103 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index f2f745930b08..78aa448e869f 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -50,6 +50,7 @@
 #include 
 #include 
 #include 
+#include 
 
 / {
interrupt-parent = <>;
@@ -69,6 +70,9 @@
cci-control-port = <_control0>;
enable-method = "allwinner,sun8i-a83t-smp";
reg = <0>;
+   #cooling-cells = <2>;
+   cooling-min-level = <0>;
+   cooling-max-level = <7>;
};
 
cpu@1 {
@@ -107,6 +111,9 @@
cci-control-port = <_control1>;
enable-method = "allwinner,sun8i-a83t-smp";
reg = <0x100>;
+   #cooling-cells = <2>;
+   cooling-min-level = <0>;
+   cooling-max-level = <7>;
};
 
cpu@101 {
@@ -1035,4 +1042,100 @@
#size-cells = <0>;
};
};
+
+   thermal-zones {
+   cpu0_thermal: cpu0-thermal {
+   polling-delay-passive = <1000>;
+   polling-delay = <5000>;
+   thermal-sensors = < 0>;
+
+   trips {
+   cpu0_warm: cpu_warm {
+   temperature = <7>;
+   hysteresis = <2000>;
+   type = "passive";
+   };
+   cpu0_hot: cpu_hot {
+   temperature = <8>;
+   hysteresis = <2000>;
+   type = "passive";
+   };
+   cpu0_very_hot: cpu_very_hot {
+   temperature = <9>;
+   hysteresis = <2000>;
+   type = "passive";
+   };
+   cpu0_crit: cpu_crit {
+   temperature = <105000>;
+   hysteresis = <2000>;
+   type = "critical";
+   };
+   };
+
+   cooling-maps {
+   cpu_warm_limit_cpu {
+   trip = <_warm>;
+   cooling-device = < 
THERMAL_NO_LIMIT 4>;
+   };
+   cpu_hot_limit_cpu {
+   trip = <_hot>;
+   cooling-device = < 5 5>;
+   };
+   cpu_very_hot_limit_cpu {
+   trip = <_very_hot>;
+   cooling-device = < 7 
THERMAL_NO_LIMIT>;
+   };
+   };
+   };
+
+   cpu1_thermal: cpu1-thermal {
+   polling-delay-passive = <1000>;
+   polling-delay = <5000>;
+   thermal-sensors = < 1>;
+
+   trips {
+   cpu1_warm: cpu_warm {
+   temperature = <7>;
+   hysteresis = <2000>;
+   type = "passive";
+   };
+   cpu1_hot: cpu_hot {
+   temperature = <8>;
+   hysteresis = <2000>;
+   type = "passive";
+   };
+   cpu1_very_hot: cpu_very_hot {
+   temperature = <9>;
+   hysteresis = <2000>;
+   type = "passive";
+   };
+   

[linux-sunxi] [PATCH v3 28/30] ARM: dts: sun8i: a83t: add support for the thermal sensor in A83T

2018-08-30 Thread Philipp Rossak
As we have gained the support for the thermal sensor in A83T,
we can now add its device nodes to the device tree.

The A83T seems to have a broken IRQ 31, thus we use here IRQ 41.

Signed-off-by: Philipp Rossak 
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 8 
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 2be23d600957..f2f745930b08 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -757,6 +757,14 @@
clocks = <>;
};
 
+   ths: thermal-sensor@1f04000 {
+   compatible = "allwinner,sun8i-a83t-ths";
+   reg = <0x01f04000 0x100>;
+   interrupts = ;
+   #thermal-sensor-cells = <1>;
+   #io-channel-cells = <0>;
+   };
+
watchdog@1c20ca0 {
compatible = "allwinner,sun6i-a31-wdt";
reg = <0x01c20ca0 0x20>;
-- 
2.11.0

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[linux-sunxi] [PATCH v3 26/30] ARM: dts: sun8i: h3: enable H3 sid controller

2018-08-30 Thread Philipp Rossak
This patch enables the the sid controller in the H3. It can be used
for thermal calibration data.

Signed-off-by: Philipp Rossak 
---
 arch/arm/boot/dts/sun8i-h3.dtsi | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 954848d5df50..1866aec69ec1 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -104,6 +104,13 @@
};
};
 
+   soc {
+   sid: eeprom@1c14000 {
+   compatible = "allwinner,sun8i-h3-sid";
+   reg = <0x01c14000 0x400>;
+   };
+   };
+
thermal-zones {
cpu-thermal {
/* milliseconds */
-- 
2.11.0

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[linux-sunxi] [PATCH v3 22/30] iio: adc: sun4i-gpadc-iio: add support for A83T thermal sensor

2018-08-30 Thread Philipp Rossak
This patch adds support for the A83T ths sensor.

The A83T supports interrupts. The interrupt is configured to update the
the sensor values every second.

Signed-off-by: Philipp Rossak 
---
 drivers/iio/adc/sun4i-gpadc-iio.c   | 59 +
 include/linux/iio/adc/sun4i-gpadc.h |  6 
 2 files changed, 65 insertions(+)

diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c 
b/drivers/iio/adc/sun4i-gpadc-iio.c
index d5c7971b2558..a184a87c56d4 100644
--- a/drivers/iio/adc/sun4i-gpadc-iio.c
+++ b/drivers/iio/adc/sun4i-gpadc-iio.c
@@ -84,6 +84,8 @@ static int sun8i_h3_ths_resume(struct sun4i_gpadc_iio *info);
 static int sun8i_h3_ths_suspend(struct sun4i_gpadc_iio *info);
 static irqreturn_t sunx8i_h3_irq_thread(int irq, void *data);
 
+static int sun8i_a83t_ths_resume(struct sun4i_gpadc_iio *info);
+
 static const struct gpadc_data sun4i_gpadc_data = {
.temp_offset = -1932,
.temp_scale = 133,
@@ -158,6 +160,21 @@ static const struct gpadc_data sun8i_h3_ths_data = {
.ths_irq_clear = SUN8I_H3_THS_INTS_TDATA_IRQ_0,
 };
 
+static const struct gpadc_data sun8i_a83t_ths_data = {
+   .temp_offset = -2724,
+   .temp_scale = -70,
+   .temp_data_base = SUN8I_H3_THS_TDATA0,
+   .ths_irq_thread = sunx8i_h3_irq_thread,
+   .support_irq = true,
+   .sensor_count = 3,
+   .supports_nvmem = true,
+   .ths_resume = sun8i_a83t_ths_resume,
+   .ths_suspend = sun8i_h3_ths_suspend,
+   .ths_irq_clear = SUN8I_H3_THS_INTS_TDATA_IRQ_0 |
+   SUN8I_A83T_THS_INTS_TDATA_IRQ_1 |
+   SUN8I_A83T_THS_INTS_TDATA_IRQ_2,
+};
+
 struct sun4i_sensor_tzd {
struct sun4i_gpadc_iio  *info;
struct thermal_zone_device  *tzd;
@@ -541,6 +558,44 @@ static int sun8i_h3_ths_resume(struct sun4i_gpadc_iio 
*info)
return 0;
 }
 
+static int sun8i_a83t_ths_resume(struct sun4i_gpadc_iio *info)
+{
+   u32 value;
+
+   sun8i_h3_calibrate(info);
+
+   regmap_write(info->regmap, SUN8I_H3_THS_CTRL0,
+   SUN4I_GPADC_CTRL0_T_ACQ(0x13f));
+
+   regmap_write(info->regmap, SUN8I_H3_THS_CTRL2,
+   SUN8I_H3_THS_ACQ1(0x13f));
+
+   regmap_write(info->regmap, SUN8I_H3_THS_STAT,
+   SUN8I_H3_THS_INTS_TDATA_IRQ_0   |
+   SUN8I_A83T_THS_INTS_TDATA_IRQ_1 |
+   SUN8I_A83T_THS_INTS_TDATA_IRQ_2);
+
+   regmap_write(info->regmap, SUN8I_H3_THS_FILTER,
+   SUN4I_GPADC_CTRL3_FILTER_EN |
+   SUN4I_GPADC_CTRL3_FILTER_TYPE(0x2));
+
+   regmap_write(info->regmap, SUN8I_H3_THS_INTC,
+   SUN8I_H3_THS_INTC_TDATA_IRQ_EN0 |
+   SUN8I_A83T_THS_INTC_TDATA_IRQ_EN1 |
+   SUN8I_A83T_THS_INTC_TDATA_IRQ_EN2 |
+   SUN8I_H3_THS_TEMP_PERIOD(0x257));
+
+   regmap_read(info->regmap, SUN8I_H3_THS_CTRL2, );
+
+   regmap_write(info->regmap, SUN8I_H3_THS_CTRL2,
+   SUN8I_H3_THS_TEMP_SENSE_EN0   |
+   SUN8I_A83T_THS_TEMP_SENSE_EN1 |
+   SUN8I_A83T_THS_TEMP_SENSE_EN2 |
+   value);
+
+   return 0;
+}
+
 static int sun4i_gpadc_get_temp(void *data, int *temp)
 {
struct sun4i_sensor_tzd *tzd = data;
@@ -588,6 +643,10 @@ static const struct of_device_id sun4i_gpadc_of_id[] = {
.compatible = "allwinner,sun8i-h3-ths",
.data = _h3_ths_data,
},
+   {
+   .compatible = "allwinner,sun8i-a83t-ths",
+   .data = _a83t_ths_data,
+   },
{ /* sentinel */ }
 };
 
diff --git a/include/linux/iio/adc/sun4i-gpadc.h 
b/include/linux/iio/adc/sun4i-gpadc.h
index 169b4de9a34d..673459bb3ec3 100644
--- a/include/linux/iio/adc/sun4i-gpadc.h
+++ b/include/linux/iio/adc/sun4i-gpadc.h
@@ -105,13 +105,19 @@
 #define SUN8I_H3_THS_CTRL2 0x40
 #define SUN8I_H3_THS_ACQ1(x)   (GENMASK(31, 16) & ((x) << 16))
 #define SUN8I_H3_THS_TEMP_SENSE_EN0BIT(0)
+#define SUN8I_A83T_THS_TEMP_SENSE_EN1  BIT(1)
+#define SUN8I_A83T_THS_TEMP_SENSE_EN2  BIT(2)
 
 #define SUN8I_H3_THS_INTC  0x44
 #define SUN8I_H3_THS_TEMP_PERIOD(x)(GENMASK(31, 12) & ((x) << 12))
 #define SUN8I_H3_THS_INTC_TDATA_IRQ_EN0BIT(8)
+#define SUN8I_A83T_THS_INTC_TDATA_IRQ_EN1  BIT(9)
+#define SUN8I_A83T_THS_INTC_TDATA_IRQ_EN2  BIT(10)
 
 #define SUN8I_H3_THS_STAT  0x48
 #define SUN8I_H3_THS_INTS_TDATA_IRQ_0  BIT(8)
+#define SUN8I_A83T_THS_INTS_TDATA_IRQ_1BIT(9)
+#define SUN8I_A83T_THS_INTS_TDATA_IRQ_2BIT(10)
 
 #define SUN8I_H3_THS_FILTER0x70
 #define S

[linux-sunxi] [PATCH v3 20/30] iio: adc: sun4i-gpadc-iio: rework: device specific suspend & resume

2018-08-30 Thread Philipp Rossak
Different sensors will have different suspend and resume functions. So
we are modularize the suspend and resume functions.

The resume function configures and initializes the thermal sensor and
the suspend function disables the sensors.

Signed-off-by: Philipp Rossak 
---
 drivers/iio/adc/sun4i-gpadc-iio.c | 20 
 1 file changed, 20 insertions(+)

diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c 
b/drivers/iio/adc/sun4i-gpadc-iio.c
index 2fd73d143815..c7b46c82e3e5 100644
--- a/drivers/iio/adc/sun4i-gpadc-iio.c
+++ b/drivers/iio/adc/sun4i-gpadc-iio.c
@@ -76,6 +76,9 @@ struct gpadc_data {
 
 static irqreturn_t sun4i_gpadc_data_irq_handler(int irq, void *dev_id);
 
+static int sun4i_ths_resume(struct sun4i_gpadc_iio *info);
+static int sun4i_ths_suspend(struct sun4i_gpadc_iio *info);
+
 static const struct gpadc_data sun4i_gpadc_data = {
.temp_offset = -1932,
.temp_scale = 133,
@@ -87,6 +90,8 @@ static const struct gpadc_data sun4i_gpadc_data = {
.ths_irq_thread = sun4i_gpadc_data_irq_handler,
.support_irq = true,
.temp_data_base = SUN4I_GPADC_TEMP_DATA,
+   .ths_resume = sun4i_ths_resume,
+   .ths_suspend = sun4i_ths_suspend,
.sensor_count = 1,
 };
 
@@ -101,6 +106,8 @@ static const struct gpadc_data sun5i_gpadc_data = {
.ths_irq_thread = sun4i_gpadc_data_irq_handler,
.support_irq = true,
.temp_data_base = SUN4I_GPADC_TEMP_DATA,
+   .ths_resume = sun4i_ths_resume,
+   .ths_suspend = sun4i_ths_suspend,
.sensor_count = 1,
 };
 
@@ -115,6 +122,8 @@ static const struct gpadc_data sun6i_gpadc_data = {
.ths_irq_thread = sun4i_gpadc_data_irq_handler,
.support_irq = true,
.temp_data_base = SUN4I_GPADC_TEMP_DATA,
+   .ths_resume = sun4i_ths_resume,
+   .ths_suspend = sun4i_ths_suspend,
.sensor_count = 1,
 };
 
@@ -123,6 +132,8 @@ static const struct gpadc_data sun8i_a33_gpadc_data = {
.temp_scale = 162,
.tp_mode_en = SUN8I_A33_GPADC_CTRL1_CHOP_TEMP_EN,
.temp_data_base = SUN4I_GPADC_TEMP_DATA,
+   .ths_resume = sun4i_ths_resume,
+   .ths_suspend = sun4i_ths_suspend,
.sensor_count = 1,
 };
 
@@ -401,6 +412,11 @@ static irqreturn_t sun4i_gpadc_data_irq_handler(int irq, 
void *dev_id)
 static int sun4i_gpadc_runtime_suspend(struct device *dev)
 {
struct sun4i_gpadc_iio *info = iio_priv(dev_get_drvdata(dev));
+   return info->data->ths_suspend(info);
+}
+
+static int sun4i_ths_suspend(struct sun4i_gpadc_iio *info)
+{
 
/* Disable the ADC on IP */
regmap_write(info->regmap, SUN4I_GPADC_CTRL1, 0);
@@ -415,7 +431,11 @@ static int sun4i_gpadc_runtime_suspend(struct device *dev)
 static int sun4i_gpadc_runtime_resume(struct device *dev)
 {
struct sun4i_gpadc_iio *info = iio_priv(dev_get_drvdata(dev));
+   return info->data->ths_resume(info);
+}
 
+static int sun4i_ths_resume(struct sun4i_gpadc_iio *info)
+{
/* clkin = 6MHz */
regmap_write(info->regmap, SUN4I_GPADC_CTRL0,
 SUN4I_GPADC_CTRL0_ADC_CLK_DIVIDER(2) |
-- 
2.11.0

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[linux-sunxi] [PATCH v3 21/30] iio: adc: sun4i-gpadc-iio: add support for H3 thermal sensor

2018-08-30 Thread Philipp Rossak
This patch adds support for the H3 ths sensor.

The H3 supports interrupts. The interrupt is configured to update the
the sensor values every second. The calibration data is writen at the
begin of the init process.

Signed-off-by: Philipp Rossak 
---
 drivers/iio/adc/sun4i-gpadc-iio.c   | 91 +
 include/linux/iio/adc/sun4i-gpadc.h | 18 
 2 files changed, 109 insertions(+)

diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c 
b/drivers/iio/adc/sun4i-gpadc-iio.c
index c7b46c82e3e5..d5c7971b2558 100644
--- a/drivers/iio/adc/sun4i-gpadc-iio.c
+++ b/drivers/iio/adc/sun4i-gpadc-iio.c
@@ -72,6 +72,7 @@ struct gpadc_data {
u32 temp_data_base;
int sensor_count;
boolsupports_nvmem;
+   u32 ths_irq_clear;
 };
 
 static irqreturn_t sun4i_gpadc_data_irq_handler(int irq, void *dev_id);
@@ -79,6 +80,10 @@ static irqreturn_t sun4i_gpadc_data_irq_handler(int irq, 
void *dev_id);
 static int sun4i_ths_resume(struct sun4i_gpadc_iio *info);
 static int sun4i_ths_suspend(struct sun4i_gpadc_iio *info);
 
+static int sun8i_h3_ths_resume(struct sun4i_gpadc_iio *info);
+static int sun8i_h3_ths_suspend(struct sun4i_gpadc_iio *info);
+static irqreturn_t sunx8i_h3_irq_thread(int irq, void *data);
+
 static const struct gpadc_data sun4i_gpadc_data = {
.temp_offset = -1932,
.temp_scale = 133,
@@ -137,6 +142,22 @@ static const struct gpadc_data sun8i_a33_gpadc_data = {
.sensor_count = 1,
 };
 
+static const struct gpadc_data sun8i_h3_ths_data = {
+   .temp_offset = -1791,
+   .temp_scale = -121,
+   .temp_data_base = SUN8I_H3_THS_TDATA0,
+   .ths_irq_thread = sunx8i_h3_irq_thread,
+   .support_irq = true,
+   .has_bus_clk = true,
+   .has_bus_rst = true,
+   .has_mod_clk = true,
+   .sensor_count = 1,
+   .supports_nvmem = true,
+   .ths_resume = sun8i_h3_ths_resume,
+   .ths_suspend = sun8i_h3_ths_suspend,
+   .ths_irq_clear = SUN8I_H3_THS_INTS_TDATA_IRQ_0,
+};
+
 struct sun4i_sensor_tzd {
struct sun4i_gpadc_iio  *info;
struct thermal_zone_device  *tzd;
@@ -409,6 +430,31 @@ static irqreturn_t sun4i_gpadc_data_irq_handler(int irq, 
void *dev_id)
return IRQ_HANDLED;
 }
 
+static irqreturn_t sunx8i_h3_irq_thread(int irq, void *data)
+{
+   struct sun4i_gpadc_iio *info = data;
+   int i;
+
+   regmap_write(info->regmap, SUN8I_H3_THS_STAT,
+   info->data->ths_irq_clear);
+
+   for (i = 0; i < info->data->sensor_count; i++)
+   thermal_zone_device_update(info->tzds[i].tzd,
+   THERMAL_EVENT_TEMP_SAMPLE);
+
+   return IRQ_HANDLED;
+}
+
+static int sun8i_h3_calibrate(struct sun4i_gpadc_iio *info)
+{
+// regmap_write(info->regmap, SUNXI_THS_CDATA_0_1,
+// info->calibration_data[0]);
+// regmap_write(info->regmap, SUNXI_THS_CDATA_2_3,
+// info->calibration_data[1]);
+
+   return 0;
+}
+
 static int sun4i_gpadc_runtime_suspend(struct device *dev)
 {
struct sun4i_gpadc_iio *info = iio_priv(dev_get_drvdata(dev));
@@ -428,6 +474,16 @@ static int sun4i_ths_suspend(struct sun4i_gpadc_iio *info)
return 0;
 }
 
+static int sun8i_h3_ths_suspend(struct sun4i_gpadc_iio *info)
+{
+   /* Disable ths interrupt */
+   regmap_write(info->regmap, SUN8I_H3_THS_INTC, 0x0);
+   /* Disable temperature sensor */
+   regmap_write(info->regmap, SUN8I_H3_THS_CTRL2, 0x0);
+
+   return 0;
+}
+
 static int sun4i_gpadc_runtime_resume(struct device *dev)
 {
struct sun4i_gpadc_iio *info = iio_priv(dev_get_drvdata(dev));
@@ -454,6 +510,37 @@ static int sun4i_ths_resume(struct sun4i_gpadc_iio *info)
return 0;
 }
 
+static int sun8i_h3_ths_resume(struct sun4i_gpadc_iio *info)
+{
+   u32 value;
+
+   sun8i_h3_calibrate(info);
+
+   regmap_write(info->regmap, SUN8I_H3_THS_CTRL0,
+   SUN4I_GPADC_CTRL0_T_ACQ(0xff));
+
+   regmap_write(info->regmap, SUN8I_H3_THS_CTRL2,
+   SUN8I_H3_THS_ACQ1(0x3f));
+
+   regmap_write(info->regmap, SUN8I_H3_THS_STAT,
+   SUN8I_H3_THS_INTS_TDATA_IRQ_0);
+
+   regmap_write(info->regmap, SUN8I_H3_THS_FILTER,
+   SUN4I_GPADC_CTRL3_FILTER_EN |
+   SUN4I_GPADC_CTRL3_FILTER_TYPE(0x2));
+
+   regmap_write(info->regmap, SUN8I_H3_THS_INTC,
+   SUN8I_H3_THS_INTC_TDATA_IRQ_EN0 |
+   SUN8I_H3_THS_TEMP_PERIOD(0x55));
+
+   regmap_read(info->regmap, SUN8I_H3_THS_CTRL2, );
+
+   regmap_write(info->regmap, SUN8I_H3_THS_CTRL2,
+   SUN8I_H3_THS_TEMP_SENSE_EN0 | value);
+
+   return 0;
+}
+
 static int sun4i_gpadc_get_temp(void *data, int *temp)
 {
struct sun4i_sensor_tzd *tzd =

[linux-sunxi] [PATCH v3 23/30] ARM: dts: sunxi-h3-h5: add support for the thermal sensor in H3 and H5

2018-08-30 Thread Philipp Rossak
As we have gained the support for the thermal sensor in H3 and H5,
we can now add its device nodes to the device tree. The H3 and H5 share
most of its compatible. The compatible and the thermal sensor cells
will be added in an additional patch per device.

Signed-off-by: Philipp Rossak 
---
 arch/arm/boot/dts/sunxi-h3-h5.dtsi | 9 +
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi 
b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index c3bff1105e5d..3520e4ad6042 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -488,6 +488,15 @@
};
};
 
+   ths: thermal-sensor@1c25000 {
+   reg = <0x01c25000 0x400>;
+   interrupts = ;
+   clocks = < CLK_BUS_THS>, < CLK_THS>;
+   clock-names = "bus", "mod";
+   resets = < RST_BUS_THS>;
+   #io-channel-cells = <0>;
+   };
+
timer@1c20c00 {
compatible = "allwinner,sun4i-a10-timer";
reg = <0x01c20c00 0xa0>;
-- 
2.11.0

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[linux-sunxi] [PATCH v3 18/30] iio: adc: sun4i-gpadc-iio: rework: support multiple sensors

2018-08-30 Thread Philipp Rossak
For adding newer sensor some basic rework of the code is necessary.

This patch reworks the driver to be able to handle more than one
thermal sensor. Newer SoC like the A80 have 4 thermal sensors.
Because of this the maximal sensor count value was set to 4.

The sensor_id value is set during sensor registration and is for each
registered sensor indiviual. This makes it able to differntiate the
sensors when the value is read from the register.

In function sun4i_gpadc_read_raw(), the sensor number of the ths sensor
was directly set to 0 (sun4i_gpadc_temp_read(x,x,0)). This selects
in the temp_read function automatically sensor 0. A check for the
sensor_id is here not required since the old sensors only have one
thermal sensor. In addition to that is the sun4i_gpadc_read_raw()
function only used by the "older" sensors (before A33) where the
thermal sensor was a cobination of an adc and a thermal sensor.

Signed-off-by: Philipp Rossak 
---
 drivers/iio/adc/sun4i-gpadc-iio.c   | 63 +
 include/linux/iio/adc/sun4i-gpadc.h |  3 ++
 2 files changed, 46 insertions(+), 20 deletions(-)

diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c 
b/drivers/iio/adc/sun4i-gpadc-iio.c
index c12de48c4e86..18ab72e52d78 100644
--- a/drivers/iio/adc/sun4i-gpadc-iio.c
+++ b/drivers/iio/adc/sun4i-gpadc-iio.c
@@ -69,6 +69,7 @@ struct gpadc_data {
boolhas_bus_rst;
boolhas_mod_clk;
u32 temp_data_base;
+   int sensor_count;
 };
 
 static irqreturn_t sun4i_gpadc_data_irq_handler(int irq, void *dev_id);
@@ -84,6 +85,7 @@ static const struct gpadc_data sun4i_gpadc_data = {
.ths_irq_thread = sun4i_gpadc_data_irq_handler,
.support_irq = true,
.temp_data_base = SUN4I_GPADC_TEMP_DATA,
+   .sensor_count = 1,
 };
 
 static const struct gpadc_data sun5i_gpadc_data = {
@@ -97,6 +99,7 @@ static const struct gpadc_data sun5i_gpadc_data = {
.ths_irq_thread = sun4i_gpadc_data_irq_handler,
.support_irq = true,
.temp_data_base = SUN4I_GPADC_TEMP_DATA,
+   .sensor_count = 1,
 };
 
 static const struct gpadc_data sun6i_gpadc_data = {
@@ -110,6 +113,7 @@ static const struct gpadc_data sun6i_gpadc_data = {
.ths_irq_thread = sun4i_gpadc_data_irq_handler,
.support_irq = true,
.temp_data_base = SUN4I_GPADC_TEMP_DATA,
+   .sensor_count = 1,
 };
 
 static const struct gpadc_data sun8i_a33_gpadc_data = {
@@ -117,6 +121,13 @@ static const struct gpadc_data sun8i_a33_gpadc_data = {
.temp_scale = 162,
.tp_mode_en = SUN8I_A33_GPADC_CTRL1_CHOP_TEMP_EN,
.temp_data_base = SUN4I_GPADC_TEMP_DATA,
+   .sensor_count = 1,
+};
+
+struct sun4i_sensor_tzd {
+   struct sun4i_gpadc_iio  *info;
+   struct thermal_zone_device  *tzd;
+   unsigned intsensor_id;
 };
 
 struct sun4i_gpadc_iio {
@@ -130,7 +141,7 @@ struct sun4i_gpadc_iio {
const struct gpadc_data *data;
/* prevents concurrent reads of temperature and ADC */
struct mutexmutex;
-   struct thermal_zone_device  *tzd;
+   struct sun4i_sensor_tzd tzds[MAX_SENSOR_COUNT];
struct device   *sensor_device;
struct clk  *bus_clk;
struct clk  *mod_clk;
@@ -280,7 +291,8 @@ static int sun4i_gpadc_adc_read(struct iio_dev *indio_dev, 
int channel,
SUN4I_GPADC_IRQ_FIFO_DATA);
 }
 
-static int sun4i_gpadc_temp_read(struct iio_dev *indio_dev, int *val)
+static int sun4i_gpadc_temp_read(struct iio_dev *indio_dev, int *val,
+   int sensor)
 {
struct sun4i_gpadc_iio *info = iio_priv(indio_dev);
 
@@ -290,7 +302,8 @@ static int sun4i_gpadc_temp_read(struct iio_dev *indio_dev, 
int *val)
 
pm_runtime_get_sync(indio_dev->dev.parent);
 
-   regmap_read(info->regmap, info->data->temp_data_base, val);
+   regmap_read(info->regmap, info->data->temp_data_base + 0x4 * sensor,
+   val);
 
pm_runtime_mark_last_busy(indio_dev->dev.parent);
pm_runtime_put_autosuspend(indio_dev->dev.parent);
@@ -334,7 +347,7 @@ static int sun4i_gpadc_read_raw(struct iio_dev *indio_dev,
ret = sun4i_gpadc_adc_read(indio_dev, chan->channel,
   val);
else
-   ret = sun4i_gpadc_temp_read(indio_dev, val);
+   ret = sun4i_gpadc_temp_read(indio_dev, val, 0);
 
if (ret)
return ret;
@@ -420,10 +433,11 @@ static int sun4i_gpadc_runtime_resume(struct device *dev)
 
 static int sun4i_gpadc_get_temp(void *data, int *temp)
 {
-   struct sun4i_gpadc_iio *info = data;
+   struct sun4i_sensor_tzd *tzd = data;
+   struct sun4i_gpadc_iio *info = t

[linux-sunxi] [PATCH v3 17/30] iio: adc: sun4i-gpadc-iio: rework: support clocks and reset

2018-08-30 Thread Philipp Rossak
For adding newer sensor some basic rework of the code is necessary.

The SoCs after H3 has newer thermal sensor ADCs, which have two clock
inputs (bus clock and sampling clock) and a reset. The registers are
also re-arranged.

This commit reworks the code, adds the process of the clocks and resets.

Signed-off-by: Philipp Rossak 
---
 drivers/iio/adc/sun4i-gpadc-iio.c | 72 +--
 1 file changed, 70 insertions(+), 2 deletions(-)

diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c 
b/drivers/iio/adc/sun4i-gpadc-iio.c
index c278e165e161..c12de48c4e86 100644
--- a/drivers/iio/adc/sun4i-gpadc-iio.c
+++ b/drivers/iio/adc/sun4i-gpadc-iio.c
@@ -22,6 +22,7 @@
  * shutdown for not being used.
  */
 
+#include 
 #include 
 #include 
 #include 
@@ -31,6 +32,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 
@@ -63,6 +65,9 @@ struct gpadc_data {
int (*ths_suspend)(struct sun4i_gpadc_iio *info);
int (*ths_resume)(struct sun4i_gpadc_iio *info);
boolsupport_irq;
+   boolhas_bus_clk;
+   boolhas_bus_rst;
+   boolhas_mod_clk;
u32 temp_data_base;
 };
 
@@ -127,6 +132,9 @@ struct sun4i_gpadc_iio {
struct mutexmutex;
struct thermal_zone_device  *tzd;
struct device   *sensor_device;
+   struct clk  *bus_clk;
+   struct clk  *mod_clk;
+   struct reset_control*reset;
 };
 
 static const struct iio_chan_spec sun4i_gpadc_channels[] = {
@@ -472,8 +480,13 @@ static int sun4i_gpadc_probe_dt(struct platform_device 
*pdev,
if (IS_ERR(base))
return PTR_ERR(base);
 
-   info->regmap = devm_regmap_init_mmio(>dev, base,
-_gpadc_regmap_config);
+   if (info->data->has_bus_clk)
+   info->regmap = devm_regmap_init_mmio_clk(>dev, "bus",
+   base, _gpadc_regmap_config);
+   else
+   info->regmap = devm_regmap_init_mmio(>dev, base,
+   _gpadc_regmap_config);
+
if (IS_ERR(info->regmap)) {
ret = PTR_ERR(info->regmap);
dev_err(>dev, "failed to init regmap: %d\n", ret);
@@ -498,9 +511,58 @@ static int sun4i_gpadc_probe_dt(struct platform_device 
*pdev,
}
}
 
+   if (info->data->has_bus_rst) {
+   info->reset = devm_reset_control_get(>dev, NULL);
+   if (IS_ERR(info->reset)) {
+   ret = PTR_ERR(info->reset);
+   return ret;
+   }
+
+   ret = reset_control_deassert(info->reset);
+   if (ret)
+   return ret;
+   }
+
+   if (info->data->has_bus_clk) {
+   info->bus_clk = devm_clk_get(>dev, "bus");
+   if (IS_ERR(info->bus_clk)) {
+   ret = PTR_ERR(info->bus_clk);
+   goto assert_reset;
+   }
+
+   ret = clk_prepare_enable(info->bus_clk);
+   if (ret)
+   goto assert_reset;
+   }
+
+   if (info->data->has_mod_clk) {
+   info->mod_clk = devm_clk_get(>dev, "mod");
+   if (IS_ERR(info->mod_clk)) {
+   ret = PTR_ERR(info->mod_clk);
+   goto disable_bus_clk;
+   }
+
+   /* Running at 4MHz */
+   ret = clk_set_rate(info->mod_clk, 400);
+   if (ret)
+   goto disable_bus_clk;
+
+   ret = clk_prepare_enable(info->mod_clk);
+   if (ret)
+   goto disable_bus_clk;
+   }
+
info->sensor_device = >dev;
 
return 0;
+
+disable_bus_clk:
+   clk_disable_unprepare(info->bus_clk);
+
+assert_reset:
+   reset_control_assert(info->reset);
+
+   return ret;
 }
 
 static int sun4i_gpadc_probe(struct platform_device *pdev)
@@ -586,6 +648,12 @@ static int sun4i_gpadc_remove(struct platform_device *pdev)
if (!info->data->support_irq)
iio_map_array_unregister(indio_dev);
 
+   clk_disable_unprepare(info->mod_clk);
+
+   clk_disable_unprepare(info->bus_clk);
+
+   reset_control_assert(info->reset);
+
return 0;
 }
 
-- 
2.11.0

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[linux-sunxi] [PATCH v3 12/30] mfd: Remove old mfd driver & Move sun4i-gpadc.h to iio/adc/

2018-08-30 Thread Philipp Rossak
Since we reworked the sun4i-gpadc iio driver we can now remove the mfd
driver and move it's header to include/linux/iio/adc.

Signed-off-by: Philipp Rossak 
---
 drivers/iio/adc/sun4i-gpadc-iio.c|   2 +-
 drivers/mfd/sun4i-gpadc.c| 181 ---
 include/linux/{mfd => iio/adc}/sun4i-gpadc.h |   0
 3 files changed, 1 insertion(+), 182 deletions(-)
 delete mode 100644 drivers/mfd/sun4i-gpadc.c
 rename include/linux/{mfd => iio/adc}/sun4i-gpadc.h (100%)

diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c 
b/drivers/iio/adc/sun4i-gpadc-iio.c
index 79b8efdab803..e1fe5e8e9dc0 100644
--- a/drivers/iio/adc/sun4i-gpadc-iio.c
+++ b/drivers/iio/adc/sun4i-gpadc-iio.c
@@ -37,7 +37,7 @@
 #include 
 #include 
 #include 
-#include 
+#include 
 
 static unsigned int sun4i_gpadc_chan_select(unsigned int chan)
 {
diff --git a/drivers/mfd/sun4i-gpadc.c b/drivers/mfd/sun4i-gpadc.c
deleted file mode 100644
index 9cfc88134d03..
--- a/drivers/mfd/sun4i-gpadc.c
+++ /dev/null
@@ -1,181 +0,0 @@
-/* ADC MFD core driver for sunxi platforms
- *
- * Copyright (c) 2016 Quentin Schulz 
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- */
-
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-
-#include 
-
-#define ARCH_SUN4I_A10 0
-#define ARCH_SUN5I_A13 1
-#define ARCH_SUN6I_A31 2
-
-static struct resource adc_resources[] = {
-   DEFINE_RES_IRQ_NAMED(SUN4I_GPADC_IRQ_FIFO_DATA, "FIFO_DATA_PENDING"),
-   DEFINE_RES_IRQ_NAMED(SUN4I_GPADC_IRQ_TEMP_DATA, "TEMP_DATA_PENDING"),
-};
-
-static const struct regmap_irq sun4i_gpadc_regmap_irq[] = {
-   REGMAP_IRQ_REG(SUN4I_GPADC_IRQ_FIFO_DATA, 0,
-  SUN4I_GPADC_INT_FIFOC_TP_DATA_IRQ_EN),
-   REGMAP_IRQ_REG(SUN4I_GPADC_IRQ_TEMP_DATA, 0,
-  SUN4I_GPADC_INT_FIFOC_TEMP_IRQ_EN),
-};
-
-static const struct regmap_irq_chip sun4i_gpadc_regmap_irq_chip = {
-   .name = "sun4i_gpadc_irq_chip",
-   .status_base = SUN4I_GPADC_INT_FIFOS,
-   .ack_base = SUN4I_GPADC_INT_FIFOS,
-   .mask_base = SUN4I_GPADC_INT_FIFOC,
-   .init_ack_masked = true,
-   .mask_invert = true,
-   .irqs = sun4i_gpadc_regmap_irq,
-   .num_irqs = ARRAY_SIZE(sun4i_gpadc_regmap_irq),
-   .num_regs = 1,
-};
-
-static struct mfd_cell sun4i_gpadc_cells[] = {
-   {
-   .name   = "sun4i-a10-gpadc-iio",
-   .resources = adc_resources,
-   .num_resources = ARRAY_SIZE(adc_resources),
-   },
-   { .name = "iio_hwmon" }
-};
-
-static struct mfd_cell sun5i_gpadc_cells[] = {
-   {
-   .name   = "sun5i-a13-gpadc-iio",
-   .resources = adc_resources,
-   .num_resources = ARRAY_SIZE(adc_resources),
-   },
-   { .name = "iio_hwmon" },
-};
-
-static struct mfd_cell sun6i_gpadc_cells[] = {
-   {
-   .name   = "sun6i-a31-gpadc-iio",
-   .resources = adc_resources,
-   .num_resources = ARRAY_SIZE(adc_resources),
-   },
-   { .name = "iio_hwmon" },
-};
-
-static const struct regmap_config sun4i_gpadc_regmap_config = {
-   .reg_bits = 32,
-   .val_bits = 32,
-   .reg_stride = 4,
-   .fast_io = true,
-};
-
-static const struct of_device_id sun4i_gpadc_of_match[] = {
-   {
-   .compatible = "allwinner,sun4i-a10-ts",
-   .data = (void *)ARCH_SUN4I_A10,
-   }, {
-   .compatible = "allwinner,sun5i-a13-ts",
-   .data = (void *)ARCH_SUN5I_A13,
-   }, {
-   .compatible = "allwinner,sun6i-a31-ts",
-   .data = (void *)ARCH_SUN6I_A31,
-   }, { /* sentinel */ }
-};
-
-MODULE_DEVICE_TABLE(of, sun4i_gpadc_of_match);
-
-static int sun4i_gpadc_probe(struct platform_device *pdev)
-{
-   struct sun4i_gpadc_dev *dev;
-   struct resource *mem;
-   const struct of_device_id *of_id;
-   const struct mfd_cell *cells;
-   unsigned int irq, size;
-   int ret;
-
-   of_id = of_match_node(sun4i_gpadc_of_match, pdev->dev.of_node);
-   if (!of_id)
-   return -EINVAL;
-
-   switch ((long)of_id->data) {
-   case ARCH_SUN4I_A10:
-   cells = sun4i_gpadc_cells;
-   size = ARRAY_SIZE(sun4i_gpadc_cells);
-   break;
-   case ARCH_SUN5I_A13:
-   cells = sun5i_gpadc_cells;
-   size = ARRAY_SIZE(sun5i_gpadc_cells);
-   break;
-   case ARCH_SUN6I_A31:
-   cells = sun6i_gpadc_cells;
-   size = ARRAY_SIZE(sun6i_gpadc_cells);
-   break;
-   default:
-   return -EINVAL;
-   }
-
-   dev = devm_kzalloc(>dev, sizeof(*dev), GFP

[linux-sunxi] [PATCH v3 03/30] iio: adc: Remove ID table

2018-08-30 Thread Philipp Rossak
To disable the driver we are removing the compatibles.

Signed-off-by: Philipp Rossak 
---
 drivers/iio/adc/sun4i-gpadc-iio.c | 9 -
 1 file changed, 9 deletions(-)

diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c 
b/drivers/iio/adc/sun4i-gpadc-iio.c
index 04d7147e0110..d95dd0fde2a6 100644
--- a/drivers/iio/adc/sun4i-gpadc-iio.c
+++ b/drivers/iio/adc/sun4i-gpadc-iio.c
@@ -698,21 +698,12 @@ static int sun4i_gpadc_remove(struct platform_device 
*pdev)
return 0;
 }
 
-static const struct platform_device_id sun4i_gpadc_id[] = {
-   { "sun4i-a10-gpadc-iio", (kernel_ulong_t)_gpadc_data },
-   { "sun5i-a13-gpadc-iio", (kernel_ulong_t)_gpadc_data },
-   { "sun6i-a31-gpadc-iio", (kernel_ulong_t)_gpadc_data },
-   { /* sentinel */ },
-};
-MODULE_DEVICE_TABLE(platform, sun4i_gpadc_id);
-
 static struct platform_driver sun4i_gpadc_driver = {
.driver = {
.name = "sun4i-gpadc-iio",
.of_match_table = sun4i_gpadc_of_id,
.pm = _gpadc_pm_ops,
},
-   .id_table = sun4i_gpadc_id,
.probe = sun4i_gpadc_probe,
.remove = sun4i_gpadc_remove,
 };
-- 
2.11.0

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[linux-sunxi] [PATCH v3 15/30] iio: adc: sun4i-gpadc-iio: rename A33-specified registers to contain A33

2018-08-30 Thread Philipp Rossak
From: Icenowy Zheng 

As the H3 SoC, which is also in sun8i line, has totally different
register map for the thermal sensor (a cut down version of GPADC), we
should rename A23/A33-specified registers to contain A33, in order to
prevent obfuscation with H3 registers. Currently these registers are
only prefixed "SUN8I", not "SUN8I_A33".

Add "_A33" after "SUN8I" on the register names.

Signed-off-by: Icenowy Zheng 
Reviewed-by: Chen-Yu Tsai 
Acked-by: Maxime Ripard 
Acked-by: Lee Jones 
Acked-by: Jonathan Cameron 
---
 drivers/iio/adc/sun4i-gpadc-iio.c   | 2 +-
 include/linux/iio/adc/sun4i-gpadc.h | 6 +++---
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c 
b/drivers/iio/adc/sun4i-gpadc-iio.c
index e1fe5e8e9dc0..d48f338af563 100644
--- a/drivers/iio/adc/sun4i-gpadc-iio.c
+++ b/drivers/iio/adc/sun4i-gpadc-iio.c
@@ -106,7 +106,7 @@ static const struct gpadc_data sun6i_gpadc_data = {
 static const struct gpadc_data sun8i_a33_gpadc_data = {
.temp_offset = -1662,
.temp_scale = 162,
-   .tp_mode_en = SUN8I_GPADC_CTRL1_CHOP_TEMP_EN,
+   .tp_mode_en = SUN8I_A33_GPADC_CTRL1_CHOP_TEMP_EN,
 };
 
 struct sun4i_gpadc_iio {
diff --git a/include/linux/iio/adc/sun4i-gpadc.h 
b/include/linux/iio/adc/sun4i-gpadc.h
index ca59336f246b..d6850f39dcfb 100644
--- a/include/linux/iio/adc/sun4i-gpadc.h
+++ b/include/linux/iio/adc/sun4i-gpadc.h
@@ -38,9 +38,9 @@
 #define SUN6I_GPADC_CTRL1_ADC_CHAN_SELECT(x)   (GENMASK(3, 0) & BIT(x))
 #define SUN6I_GPADC_CTRL1_ADC_CHAN_MASKGENMASK(3, 0)
 
-/* TP_CTRL1 bits for sun8i SoCs */
-#define SUN8I_GPADC_CTRL1_CHOP_TEMP_EN BIT(8)
-#define SUN8I_GPADC_CTRL1_GPADC_CALI_ENBIT(7)
+/* TP_CTRL1 bits for A33 */
+#define SUN8I_A33_GPADC_CTRL1_CHOP_TEMP_EN BIT(8)
+#define SUN8I_A33_GPADC_CTRL1_GPADC_CALI_ENBIT(7)
 
 #define SUN4I_GPADC_CTRL2  0x08
 
-- 
2.11.0

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[linux-sunxi] [PATCH v3 07/30] iio: adc: remove mfd_probe & sunwi_irq_init function

2018-08-30 Thread Philipp Rossak
In the previous commit we removed the function call, now we remove the
unused functions.

Signed-off-by: Philipp Rossak 
---
 drivers/iio/adc/sun4i-gpadc-iio.c | 126 --
 1 file changed, 126 deletions(-)

diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c 
b/drivers/iio/adc/sun4i-gpadc-iio.c
index d6f00d3b802d..f787442a9e5f 100644
--- a/drivers/iio/adc/sun4i-gpadc-iio.c
+++ b/drivers/iio/adc/sun4i-gpadc-iio.c
@@ -431,55 +431,6 @@ static const struct dev_pm_ops sun4i_gpadc_pm_ops = {
.runtime_resume = _gpadc_runtime_resume,
 };
 
-static int sun4i_irq_init(struct platform_device *pdev, const char *name,
- irq_handler_t handler, const char *devname,
- unsigned int *irq, atomic_t *atomic)
-{
-   int ret;
-   struct sun4i_gpadc_dev *mfd_dev = dev_get_drvdata(pdev->dev.parent);
-   struct sun4i_gpadc_iio *info = iio_priv(dev_get_drvdata(>dev));
-
-   /*
-* Once the interrupt is activated, the IP continuously performs
-* conversions thus throws interrupts. The interrupt is activated right
-* after being requested but we want to control when these interrupts
-* occur thus we disable it right after being requested. However, an
-* interrupt might occur between these two instructions and we have to
-* make sure that does not happen, by using atomic flags. We set the
-* flag before requesting the interrupt and unset it right after
-* disabling the interrupt. When an interrupt occurs between these two
-* instructions, reading the atomic flag will tell us to ignore the
-* interrupt.
-*/
-   atomic_set(atomic, 1);
-
-   ret = platform_get_irq_byname(pdev, name);
-   if (ret < 0) {
-   dev_err(>dev, "no %s interrupt registered\n", name);
-   return ret;
-   }
-
-   ret = regmap_irq_get_virq(mfd_dev->regmap_irqc, ret);
-   if (ret < 0) {
-   dev_err(>dev, "failed to get virq for irq %s\n", name);
-   return ret;
-   }
-
-   *irq = ret;
-   ret = devm_request_any_context_irq(>dev, *irq, handler, 0,
-  devname, info);
-   if (ret < 0) {
-   dev_err(>dev, "could not request %s interrupt: %d\n",
-   name, ret);
-   return ret;
-   }
-
-   disable_irq(*irq);
-   atomic_set(atomic, 0);
-
-   return 0;
-}
-
 static const struct of_device_id sun4i_gpadc_of_id[] = {
{
.compatible = "allwinner,sun8i-a33-ths",
@@ -523,83 +474,6 @@ static int sun4i_gpadc_probe_dt(struct platform_device 
*pdev,
return 0;
 }
 
-static int sun4i_gpadc_probe_mfd(struct platform_device *pdev,
-struct iio_dev *indio_dev)
-{
-   struct sun4i_gpadc_iio *info = iio_priv(indio_dev);
-   struct sun4i_gpadc_dev *sun4i_gpadc_dev =
-   dev_get_drvdata(pdev->dev.parent);
-   int ret;
-
-   info->no_irq = false;
-   info->regmap = sun4i_gpadc_dev->regmap;
-
-   indio_dev->num_channels = ARRAY_SIZE(sun4i_gpadc_channels);
-   indio_dev->channels = sun4i_gpadc_channels;
-
-   info->data = (struct gpadc_data 
*)platform_get_device_id(pdev)->driver_data;
-
-   /*
-* Since the controller needs to be in touchscreen mode for its thermal
-* sensor to operate properly, and that switching between the two modes
-* needs a delay, always registering in the thermal framework will
-* significantly slow down the conversion rate of the ADCs.
-*
-* Therefore, instead of depending on THERMAL_OF in Kconfig, we only
-* register the sensor if that option is enabled, eventually leaving
-* that choice to the user.
-*/
-
-   if (IS_ENABLED(CONFIG_THERMAL_OF)) {
-   /*
-* This driver is a child of an MFD which has a node in the DT
-* but not its children, because of DT backward compatibility
-* for A10, A13 and A31 SoCs. Therefore, the resulting devices
-* of this driver do not have an of_node variable.
-* However, its parent (the MFD driver) has an of_node variable
-* and since devm_thermal_zone_of_sensor_register uses its first
-* argument to match the phandle defined in the node of the
-* thermal driver with the of_node of the device passed as first
-* argument and the third argument to call ops from
-* thermal_zone_of_device_ops, the solution is to use the parent
-* device as first argument to match the phandle with its
-* of_node, and the device from this driver as third argument to
-* return the temperatu

[linux-sunxi] [PATCH v3 09/30] iio: adc: Threat A33 as thermal sensor and remove non thermal sun4i channel

2018-08-30 Thread Philipp Rossak
We want to use this driver mostly as thermal sensor, that still supports
the adc for the older chips, thus we threat the A33 as thermal sensor.
We also remove the adc channel without thermal support.

Signed-off-by: Philipp Rossak 
---
 drivers/iio/adc/sun4i-gpadc-iio.c | 19 ---
 1 file changed, 19 deletions(-)

diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c 
b/drivers/iio/adc/sun4i-gpadc-iio.c
index ab474ce86fb6..658a7e3e3370 100644
--- a/drivers/iio/adc/sun4i-gpadc-iio.c
+++ b/drivers/iio/adc/sun4i-gpadc-iio.c
@@ -123,23 +123,6 @@ static const struct iio_chan_spec sun4i_gpadc_channels[] = 
{
},
 };
 
-static const struct iio_chan_spec sun4i_gpadc_channels_no_temp[] = {
-   SUN4I_GPADC_ADC_CHANNEL(0, "adc_chan0"),
-   SUN4I_GPADC_ADC_CHANNEL(1, "adc_chan1"),
-   SUN4I_GPADC_ADC_CHANNEL(2, "adc_chan2"),
-   SUN4I_GPADC_ADC_CHANNEL(3, "adc_chan3"),
-};
-
-static const struct iio_chan_spec sun8i_a33_gpadc_channels[] = {
-   {
-   .type = IIO_TEMP,
-   .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
- BIT(IIO_CHAN_INFO_SCALE) |
- BIT(IIO_CHAN_INFO_OFFSET),
-   .datasheet_name = "temp_adc",
-   },
-};
-
 static const struct regmap_config sun4i_gpadc_regmap_config = {
.reg_bits = 32,
.val_bits = 32,
@@ -444,8 +427,6 @@ static int sun4i_gpadc_probe_dt(struct platform_device 
*pdev,
return -ENODEV;
 
info->no_irq = true;
-   indio_dev->num_channels = ARRAY_SIZE(sun8i_a33_gpadc_channels);
-   indio_dev->channels = sun8i_a33_gpadc_channels;
 
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
base = devm_ioremap_resource(>dev, mem);
-- 
2.11.0

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[linux-sunxi] [PATCH v3 13/30] arm: config: Enable SUN4I_GPADC in defconfig

2018-08-30 Thread Philipp Rossak
Since we have now new compatibles we can enable the SUN4I_GPADC driver
next to the sun4i-ts driver.

Signed-off-by: Philipp Rossak 
---
 arch/arm/configs/sunxi_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/configs/sunxi_defconfig b/arch/arm/configs/sunxi_defconfig
index df433abfcb02..2189349820ac 100644
--- a/arch/arm/configs/sunxi_defconfig
+++ b/arch/arm/configs/sunxi_defconfig
@@ -132,6 +132,7 @@ CONFIG_DMA_SUN6I=y
 # CONFIG_IOMMU_SUPPORT is not set
 CONFIG_EXTCON=y
 CONFIG_IIO=y
+CONFIG_SUN4I_GPADC=y
 CONFIG_AXP20X_ADC=y
 CONFIG_PWM=y
 CONFIG_PWM_SUN4I=y
-- 
2.11.0

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[linux-sunxi] [PATCH v3 10/30] iio: adc: rework irq and adc_channel handling

2018-08-30 Thread Philipp Rossak
We rework the irq handling and the adc_channel handling.
This is requiered since we merge the mfd driver into the adc driver.

Signed-off-by: Philipp Rossak 
---
 drivers/iio/adc/sun4i-gpadc-iio.c | 157 --
 include/linux/mfd/sun4i-gpadc.h   |   7 --
 2 files changed, 98 insertions(+), 66 deletions(-)

diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c 
b/drivers/iio/adc/sun4i-gpadc-iio.c
index 658a7e3e3370..a2027614ee0c 100644
--- a/drivers/iio/adc/sun4i-gpadc-iio.c
+++ b/drivers/iio/adc/sun4i-gpadc-iio.c
@@ -49,6 +49,8 @@ static unsigned int sun6i_gpadc_chan_select(unsigned int chan)
return SUN6I_GPADC_CTRL1_ADC_CHAN_SELECT(chan);
 }
 
+struct sun4i_gpadc_iio;
+
 struct gpadc_data {
int temp_offset;
int temp_scale;
@@ -56,8 +58,15 @@ struct gpadc_data {
unsigned inttp_adc_select;
unsigned int(*adc_chan_select)(unsigned int chan);
unsigned intadc_chan_mask;
+   booladc_channel;
+   irqreturn_t (*ths_irq_thread)(int irq, void *dev_id);
+   int (*ths_suspend)(struct sun4i_gpadc_iio *info);
+   int (*ths_resume)(struct sun4i_gpadc_iio *info);
+   boolsupport_irq;
 };
 
+static irqreturn_t sun4i_gpadc_data_irq_handler(int irq, void *dev_id);
+
 static const struct gpadc_data sun4i_gpadc_data = {
.temp_offset = -1932,
.temp_scale = 133,
@@ -65,6 +74,9 @@ static const struct gpadc_data sun4i_gpadc_data = {
.tp_adc_select = SUN4I_GPADC_CTRL1_TP_ADC_SELECT,
.adc_chan_select = _gpadc_chan_select,
.adc_chan_mask = SUN4I_GPADC_CTRL1_ADC_CHAN_MASK,
+   .adc_channel = true,
+   .ths_irq_thread = sun4i_gpadc_data_irq_handler,
+   .support_irq = true,
 };
 
 static const struct gpadc_data sun5i_gpadc_data = {
@@ -74,6 +86,9 @@ static const struct gpadc_data sun5i_gpadc_data = {
.tp_adc_select = SUN4I_GPADC_CTRL1_TP_ADC_SELECT,
.adc_chan_select = _gpadc_chan_select,
.adc_chan_mask = SUN4I_GPADC_CTRL1_ADC_CHAN_MASK,
+   .adc_channel = true,
+   .ths_irq_thread = sun4i_gpadc_data_irq_handler,
+   .support_irq = true,
 };
 
 static const struct gpadc_data sun6i_gpadc_data = {
@@ -83,6 +98,9 @@ static const struct gpadc_data sun6i_gpadc_data = {
.tp_adc_select = SUN6I_GPADC_CTRL1_TP_ADC_SELECT,
.adc_chan_select = _gpadc_chan_select,
.adc_chan_mask = SUN6I_GPADC_CTRL1_ADC_CHAN_MASK,
+   .adc_channel = true,
+   .ths_irq_thread = sun4i_gpadc_data_irq_handler,
+   .support_irq = true,
 };
 
 static const struct gpadc_data sun8i_a33_gpadc_data = {
@@ -96,13 +114,10 @@ struct sun4i_gpadc_iio {
struct completion   completion;
int temp_data;
u32 adc_data;
+   unsigned intirq_data_type;
struct regmap   *regmap;
-   unsigned intfifo_data_irq;
-   atomic_tignore_fifo_data_irq;
-   unsigned inttemp_data_irq;
-   atomic_tignore_temp_data_irq;
+   unsigned intirq;
const struct gpadc_data *data;
-   boolno_irq;
/* prevents concurrent reads of temperature and ADC */
struct mutexmutex;
struct thermal_zone_device  *tzd;
@@ -130,6 +145,20 @@ static const struct regmap_config 
sun4i_gpadc_regmap_config = {
.fast_io = true,
 };
 
+static int sun4i_gpadc_irq_init(struct sun4i_gpadc_iio *info)
+{
+   u32 reg;
+
+   if (info->irq_data_type == SUN4I_GPADC_IRQ_FIFO_DATA)
+   reg = SUN4I_GPADC_INT_FIFOC_TEMP_IRQ_EN;
+   else
+   reg = SUN4I_GPADC_INT_FIFOC_TEMP_IRQ_EN;
+
+   regmap_write(info->regmap, SUN4I_GPADC_INT_FIFOC, reg);
+
+   return 0;
+}
+
 static int sun4i_prepare_for_irq(struct iio_dev *indio_dev, int channel,
 unsigned int irq)
 {
@@ -151,7 +180,7 @@ static int sun4i_prepare_for_irq(struct iio_dev *indio_dev, 
int channel,
if (ret)
return ret;
 
-   if (irq == info->fifo_data_irq) {
+   if (irq == SUN4I_GPADC_IRQ_FIFO_DATA) {
ret = regmap_write(info->regmap, SUN4I_GPADC_CTRL1,
   info->data->tp_mode_en |
   info->data->tp_adc_select |
@@ -172,6 +201,8 @@ static int sun4i_prepare_for_irq(struct iio_dev *indio_dev, 
int channel,
ret = regmap_write(info->regmap, SUN4I_GPADC_CTRL1,
   info->data->tp_mode_en);
}
+   if (info->data->support_irq)
+   sun4i_gpadc_irq_init(info);
 
if (ret)
return ret;
@@ -194,11 +225,12 @@ static int sun4i_gpadc_read(struc

[linux-sunxi] [PATCH v3 01/30] mfd: Makefile: Remove build option for MFD:sun4i-gpadc

2018-08-30 Thread Philipp Rossak
Since we are merging the mfd driver into the sun4i-gpadc driver we need
to remove the build options for the sun4i-gpadc driver.

Signed-off-by: Philipp Rossak 
---
 drivers/mfd/Makefile | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index e9fd20dba18d..c680994db988 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -220,7 +220,6 @@ obj-$(CONFIG_INTEL_SOC_PMIC_CHTDC_TI)   += 
intel_soc_pmic_chtdc_ti.o
 obj-$(CONFIG_MFD_MT6397)   += mt6397-core.o
 
 obj-$(CONFIG_MFD_ALTERA_A10SR) += altera-a10sr.o
-obj-$(CONFIG_MFD_SUN4I_GPADC)  += sun4i-gpadc.o
 
 obj-$(CONFIG_MFD_STM32_LPTIMER)+= stm32-lptimer.o
 obj-$(CONFIG_MFD_STM32_TIMERS) += stm32-timers.o
-- 
2.11.0

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[linux-sunxi] [PATCH v3 02/30] mfd: Kconfig: Remove MFD_SUN4I_GPADC config option

2018-08-30 Thread Philipp Rossak
We are merging the mfd:sun4i-gpadc driver into the
iio/adc/sun4i-gpadc driver. So we need to remove the MFD_SUN4I_GPADC
config option.

Signed-off-by: Philipp Rossak 
---
 drivers/mfd/Kconfig | 17 -
 1 file changed, 17 deletions(-)

diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index b860eb5aa194..c7ab57d65610 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -40,23 +40,6 @@ config MFD_ACT8945A
  linear regulators, along with a complete ActivePath battery
  charger.
 
-config MFD_SUN4I_GPADC
-   tristate "Allwinner sunxi platforms' GPADC MFD driver"
-   select MFD_CORE
-   select REGMAP_MMIO
-   select REGMAP_IRQ
-   depends on ARCH_SUNXI || COMPILE_TEST
-   depends on !TOUCHSCREEN_SUN4I
-   help
- Select this to get support for Allwinner SoCs (A10, A13 and A31) ADC.
- This driver will only map the hardware interrupt and registers, you
- have to select individual drivers based on this MFD to be able to use
- the ADC or the thermal sensor. This will try to probe the ADC driver
- sun4i-gpadc-iio and the hwmon driver iio_hwmon.
-
- To compile this driver as a module, choose M here: the module will be
- called sun4i-gpadc.
-
 config MFD_AS3711
bool "AMS AS3711"
select MFD_CORE
-- 
2.11.0

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[linux-sunxi] [PATCH v3 11/30] iio: adc: add new compatibles

2018-08-30 Thread Philipp Rossak
We are now adding the new compatibles.

Signed-off-by: Philipp Rossak 
---
 drivers/iio/adc/sun4i-gpadc-iio.c | 12 
 1 file changed, 12 insertions(+)

diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c 
b/drivers/iio/adc/sun4i-gpadc-iio.c
index a2027614ee0c..79b8efdab803 100644
--- a/drivers/iio/adc/sun4i-gpadc-iio.c
+++ b/drivers/iio/adc/sun4i-gpadc-iio.c
@@ -435,6 +435,18 @@ static const struct of_device_id sun4i_gpadc_of_id[] = {
.compatible = "allwinner,sun8i-a33-ths",
.data = _a33_gpadc_data,
},
+   {
+   .compatible = "allwinner,sun4i-a10-gpadc",
+   .data = _gpadc_data
+   },
+   {
+   .compatible = "allwinner,sun5i-a13-gpadc",
+   .data = _gpadc_data
+   },
+   {
+   .compatible = "allwinner,sun6i-a31-gpadc",
+   .data = _gpadc_data
+   },
{ /* sentinel */ }
 };
 
-- 
2.11.0

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[linux-sunxi] [PATCH v3 05/30] iio: adc: move SUN4I_GPADC_CHANNEL define to header file

2018-08-30 Thread Philipp Rossak
We are moving the SUN4I_GPADC_CHANNEL define to the header file.

Signed-off-by: Philipp Rossak 
---
 drivers/iio/adc/sun4i-gpadc-iio.c | 9 -
 include/linux/mfd/sun4i-gpadc.h   | 9 +
 2 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c 
b/drivers/iio/adc/sun4i-gpadc-iio.c
index d95dd0fde2a6..666329940e1e 100644
--- a/drivers/iio/adc/sun4i-gpadc-iio.c
+++ b/drivers/iio/adc/sun4i-gpadc-iio.c
@@ -109,15 +109,6 @@ struct sun4i_gpadc_iio {
struct device   *sensor_device;
 };
 
-#define SUN4I_GPADC_ADC_CHANNEL(_channel, _name) { \
-   .type = IIO_VOLTAGE,\
-   .indexed = 1,   \
-   .channel = _channel,\
-   .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),   \
-   .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),   \
-   .datasheet_name = _name,\
-}
-
 static struct iio_map sun4i_gpadc_hwmon_maps[] = {
{
.adc_channel_label = "temp_adc",
diff --git a/include/linux/mfd/sun4i-gpadc.h b/include/linux/mfd/sun4i-gpadc.h
index 139872c2e0fe..54c7c9375c1b 100644
--- a/include/linux/mfd/sun4i-gpadc.h
+++ b/include/linux/mfd/sun4i-gpadc.h
@@ -90,6 +90,15 @@
 /* 10s delay before suspending the IP */
 #define SUN4I_GPADC_AUTOSUSPEND_DELAY  1
 
+#define SUN4I_GPADC_ADC_CHANNEL(_channel, _name) { \
+   .type = IIO_VOLTAGE,\
+   .indexed = 1,   \
+   .channel = _channel,\
+   .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),   \
+   .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),   \
+   .datasheet_name = _name,\
+}
+
 struct sun4i_gpadc_dev {
struct device   *dev;
struct regmap   *regmap;
-- 
2.11.0

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[linux-sunxi] [PATCH v3 14/30] dt-bindings: update the Allwinner GPADC device tree binding for H3 & A83T

2018-08-30 Thread Philipp Rossak
Allwinner H3 features a thermal sensor like the one in A33, but has its
register re-arranged, the clock divider moved to CCU (originally the
clock divider is in ADC) and added a pair of bus clock and reset.

Allwinner A83T features a thermal sensor similar to the H3, the ths clock,
the bus clock and the reset was removed from the CCU. The THS in A83T
has a clock that is directly connected and runs with 24 MHz.

Update the binding document to cover H3 and A83T.

Signed-off-by: Philipp Rossak 
---
 .../devicetree/bindings/iio/adc/sun4i-gpadc.txt| 41 --
 1 file changed, 38 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/iio/adc/sun4i-gpadc.txt 
b/Documentation/devicetree/bindings/iio/adc/sun4i-gpadc.txt
index a7ef9dd21f04..9116ad308cf1 100644
--- a/Documentation/devicetree/bindings/iio/adc/sun4i-gpadc.txt
+++ b/Documentation/devicetree/bindings/iio/adc/sun4i-gpadc.txt
@@ -4,12 +4,35 @@ The Allwinner SoCs all have an ADC that can also act as a 
thermal sensor
 and sometimes as a touchscreen controller.
 
 Required properties:
-  - compatible: "allwinner,sun8i-a33-ths",
+  - compatible: must contain one of the following compatibles:
+   - "allwinner,sun8i-a33-ths"
+   - "allwinner,sun8i-h3-ths"
+   - "allwinner,sun8i-a83t-ths"
   - reg: mmio address range of the chip,
-  - #thermal-sensor-cells: shall be 0,
+  - #thermal-sensor-cells:
+   Please refer ,
   - #io-channel-cells: shall be 0,
 
-Example:
+Required properties for the following compatibles:
+   - "allwinner,sun8i-h3-ths"
+   - "allwinner,sun8i-a83t-ths"
+  - interrupts: the sampling interrupt of the ADC,
+
+Required properties for the following compatibles:
+   - "allwinner,sun8i-h3-ths"
+  - clocks: the bus clock and the input clock of the ADC,
+  - clock-names: should be "bus" and "mod",
+  - resets: the bus reset of the ADC,
+
+Optional properties for the following compatibles:
+   - "allwinner,sun8i-h3-ths"
+   - "allwinner,sun8i-a83t-ths"
+  - nvmem-cells: A phandle to the calibration data provided by a nvmem device.
+  - nvmem-cell-names: Should be "calibration".
+
+Details see: bindings/nvmem/nvmem.txt
+
+Example for A33:
ths: ths@1c25000 {
compatible = "allwinner,sun8i-a33-ths";
reg = <0x01c25000 0x100>;
@@ -17,6 +40,18 @@ Example:
#io-channel-cells = <0>;
};
 
+Example for H3:
+   ths: thermal-sensor@1c25000 {
+   compatible = "allwinner,sun8i-h3-ths";
+   reg = <0x01c25000 0x400>;
+   clocks = < CLK_BUS_THS>, < CLK_THS>;
+   clock-names = "bus", "mod";
+   resets = < RST_BUS_THS>;
+   interrupts = ;
+   #thermal-sensor-cells = <0>;
+   #io-channel-cells = <0>;
+   };
+
 sun4i, sun5i and sun6i SoCs are also supported via these bindings:
 
 Required properties:
-- 
2.11.0

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[linux-sunxi] [PATCH v3 16/30] iio: adc: sun4i-gpadc-iio: rework: readout temp_data

2018-08-30 Thread Philipp Rossak
For adding newer sensor some basic rework of the code is necessary.

This commit reworks the code and uses regmap field to read out
temp_data.

Signed-off-by: Philipp Rossak 
---
 drivers/iio/adc/sun4i-gpadc-iio.c | 21 +
 1 file changed, 13 insertions(+), 8 deletions(-)

diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c 
b/drivers/iio/adc/sun4i-gpadc-iio.c
index d48f338af563..c278e165e161 100644
--- a/drivers/iio/adc/sun4i-gpadc-iio.c
+++ b/drivers/iio/adc/sun4i-gpadc-iio.c
@@ -63,6 +63,7 @@ struct gpadc_data {
int (*ths_suspend)(struct sun4i_gpadc_iio *info);
int (*ths_resume)(struct sun4i_gpadc_iio *info);
boolsupport_irq;
+   u32 temp_data_base;
 };
 
 static irqreturn_t sun4i_gpadc_data_irq_handler(int irq, void *dev_id);
@@ -77,6 +78,7 @@ static const struct gpadc_data sun4i_gpadc_data = {
.adc_channel = true,
.ths_irq_thread = sun4i_gpadc_data_irq_handler,
.support_irq = true,
+   .temp_data_base = SUN4I_GPADC_TEMP_DATA,
 };
 
 static const struct gpadc_data sun5i_gpadc_data = {
@@ -89,6 +91,7 @@ static const struct gpadc_data sun5i_gpadc_data = {
.adc_channel = true,
.ths_irq_thread = sun4i_gpadc_data_irq_handler,
.support_irq = true,
+   .temp_data_base = SUN4I_GPADC_TEMP_DATA,
 };
 
 static const struct gpadc_data sun6i_gpadc_data = {
@@ -101,12 +104,14 @@ static const struct gpadc_data sun6i_gpadc_data = {
.adc_channel = true,
.ths_irq_thread = sun4i_gpadc_data_irq_handler,
.support_irq = true,
+   .temp_data_base = SUN4I_GPADC_TEMP_DATA,
 };
 
 static const struct gpadc_data sun8i_a33_gpadc_data = {
.temp_offset = -1662,
.temp_scale = 162,
.tp_mode_en = SUN8I_A33_GPADC_CTRL1_CHOP_TEMP_EN,
+   .temp_data_base = SUN4I_GPADC_TEMP_DATA,
 };
 
 struct sun4i_gpadc_iio {
@@ -271,18 +276,18 @@ static int sun4i_gpadc_temp_read(struct iio_dev 
*indio_dev, int *val)
 {
struct sun4i_gpadc_iio *info = iio_priv(indio_dev);
 
-   if (!info->data->support_irq) {
-   pm_runtime_get_sync(indio_dev->dev.parent);
+   if (info->data->adc_channel)
+   return sun4i_gpadc_read(indio_dev, 0, val,
+   SUN4I_GPADC_IRQ_TEMP_DATA);
 
-   regmap_read(info->regmap, SUN4I_GPADC_TEMP_DATA, val);
+   pm_runtime_get_sync(indio_dev->dev.parent);
 
-   pm_runtime_mark_last_busy(indio_dev->dev.parent);
-   pm_runtime_put_autosuspend(indio_dev->dev.parent);
+   regmap_read(info->regmap, info->data->temp_data_base, val);
 
-   return 0;
-   }
+   pm_runtime_mark_last_busy(indio_dev->dev.parent);
+   pm_runtime_put_autosuspend(indio_dev->dev.parent);
 
-   return sun4i_gpadc_read(indio_dev, 0, val, SUN4I_GPADC_IRQ_TEMP_DATA);
+   return 0;
 }
 
 static int sun4i_gpadc_temp_offset(struct iio_dev *indio_dev, int *val)
-- 
2.11.0

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[linux-sunxi] [PATCH v3 06/30] iio: adc: remove ofnode options

2018-08-30 Thread Philipp Rossak
Since we are merging the mfd dirver into the adc driver we don't need
two different probing functions. Thus we remove the ofnode options

Signed-off-by: Philipp Rossak 
---
 drivers/iio/adc/sun4i-gpadc-iio.c | 5 +
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c 
b/drivers/iio/adc/sun4i-gpadc-iio.c
index 666329940e1e..d6f00d3b802d 100644
--- a/drivers/iio/adc/sun4i-gpadc-iio.c
+++ b/drivers/iio/adc/sun4i-gpadc-iio.c
@@ -622,10 +622,7 @@ static int sun4i_gpadc_probe(struct platform_device *pdev)
indio_dev->info = _gpadc_iio_info;
indio_dev->modes = INDIO_DIRECT_MODE;
 
-   if (pdev->dev.of_node)
-   ret = sun4i_gpadc_probe_dt(pdev, indio_dev);
-   else
-   ret = sun4i_gpadc_probe_mfd(pdev, indio_dev);
+   ret = sun4i_gpadc_probe_dt(pdev, indio_dev);
 
if (ret)
return ret;
-- 
2.11.0

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[linux-sunxi] [PATCH v3 00/30] IIO-based thermal sensor driver for Allwinner H3 and A83T SoC

2018-08-30 Thread Philipp Rossak
Allwiner H3 and A83T SoCs have a thermal sensor, which is a large refactored
version of the old Allwinner "GPADC" (although it have already only
thermal part left in A33).

This patch tried to add support for the sensor in H3 and A83T based on

This Patchtseries was in the beginning based on Icenowy Zengs v4 patchseries 
[1]. Since we decided to merge the mfd driver into the GPADC this changed. So 
only one patch could be reused.

Patches that adds support for H5, A64, A80 and H6 SoCs are allready prepared,
and will be upstreamed if this patchseries is applied and the testing is done.

Sorry for delaying this.

Regards,
Philipp 

changes since v2:
* mfd driver is now merged into the gpadc driver
* complete rework

changes since v1:
* collecting all acks 
* rewording commits/fix typos
* move code in place where it is used
* fix naming conventions of defines
* clarify commits
* update documentation to cover the new nvmem calibraion
* change nvmem calibration



Icenowy Zheng (1):
  iio: adc: sun4i-gpadc-iio: rename A33-specified registers to contain
A33

Philipp Rossak (29):
  mfd: Makefile: Remove build option for MFD:sun4i-gpadc
  mfd: Kconfig: Remove MFD_SUN4I_GPADC config option
  iio: adc: Remove ID table
  iio: adc: Kconfig: Update Kconfig to new build options
  iio: adc: move SUN4I_GPADC_CHANNEL define to header file
  iio: adc: remove ofnode options
  iio: adc: remove mfd_probe & sunwi_irq_init function
  iio: adc: remove hwmon structure
  iio: adc: Threat A33 as thermal sensor and remove non thermal sun4i
channel
  iio: adc: rework irq and adc_channel handling
  iio: adc: add new compatibles
  mfd: Remove old mfd driver & Move sun4i-gpadc.h to iio/adc/
  arm: config: Enable SUN4I_GPADC in defconfig
  dt-bindings: update the Allwinner GPADC device tree binding for H3 &
A83T
  iio: adc: sun4i-gpadc-iio: rework: readout temp_data
  iio: adc: sun4i-gpadc-iio: rework: support clocks and reset
  iio: adc: sun4i-gpadc-iio: rework: support multiple sensors
  iio: adc: sun4i-gpadc-iio: rework: support nvmem calibration data
  iio: adc: sun4i-gpadc-iio: rework: device specific suspend & resume
  iio: adc: sun4i-gpadc-iio: add support for H3 thermal sensor
  iio: adc: sun4i-gpadc-iio: add support for A83T thermal sensor
  ARM: dts: sunxi-h3-h5: add support for the thermal sensor in H3 and H5
  ARM: dts: sun8i: h3: add support for the thermal sensor in H3
  ARM: dts: sun8i: h3: add thermal zone to H3
  ARM: dts: sun8i: h3: enable H3 sid controller
  ARM: dts: sun8i: h3: use calibration for ths
  ARM: dts: sun8i: a83t: add support for the thermal sensor in A83T
  ARM: dts: sun8i: a83t: add thermal zone to A83T
  ARM: sun8i: a83t: full range OPP tables and CPUfreq

 .../devicetree/bindings/iio/adc/sun4i-gpadc.txt|  41 +-
 arch/arm/boot/dts/sun8i-a83t.dtsi  | 143 +
 arch/arm/boot/dts/sun8i-h3.dtsi|  52 ++
 arch/arm/boot/dts/sunxi-h3-h5.dtsi |  10 +
 arch/arm/configs/sunxi_defconfig   |   1 +
 drivers/iio/adc/Kconfig|  11 +-
 drivers/iio/adc/sun4i-gpadc-iio.c  | 617 +
 drivers/mfd/Kconfig|  17 -
 drivers/mfd/Makefile   |   1 -
 drivers/mfd/sun4i-gpadc.c  | 181 --
 include/linux/{mfd => iio/adc}/sun4i-gpadc.h   |  47 +-
 11 files changed, 681 insertions(+), 440 deletions(-)
 delete mode 100644 drivers/mfd/sun4i-gpadc.c
 rename include/linux/{mfd => iio/adc}/sun4i-gpadc.h (72%)

-- 
2.11.0

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[linux-sunxi] [PATCH v3 04/30] iio: adc: Kconfig: Update Kconfig to new build options

2018-08-30 Thread Philipp Rossak
Since we are merging the mfd driver into the iio adc driver we need to
update the Kconfig build options.

Signed-off-by: Philipp Rossak 
---
 drivers/iio/adc/Kconfig | 11 +++
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
index 9da79070357c..5d0cffd6d2e4 100644
--- a/drivers/iio/adc/Kconfig
+++ b/drivers/iio/adc/Kconfig
@@ -713,13 +713,16 @@ config STX104
  array module parameter.
 
 config SUN4I_GPADC
-   tristate "Support for the Allwinner SoCs GPADC"
+   tristate "Allwinner sunxi platforms' GPADC/Thermal driver"
+   select REGMAP_MMIO
+   select REGMAP_IRQ
depends on IIO
-   depends on MFD_SUN4I_GPADC || MACH_SUN8I
-   depends on THERMAL || !THERMAL_OF
+   depends on ARCH_SUNXI || MACH_SUN8I
+   depends on THERMAL && THERMAL_OF
help
  Say yes here to build support for Allwinner (A10, A13 and A31) SoCs
- GPADC. This ADC provides 4 channels which can be used as an ADC or as
+ GPADC or newer SOCs (A33, H3, A83T, ...) Thermal sensor driver.
+ This ADC provides 4 channels which can be used as an ADC or as
  a touchscreen input and one channel for thermal sensor.
 
  The thermal sensor slows down ADC readings and can be disabled by
-- 
2.11.0

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Re: [linux-sunxi] Re: [PATCH v2 14/16] arm: dts: sun8i: h3: enable H3 sid controller

2018-04-20 Thread Philipp Rossak

Hi Kyle,

I'm already working on a Version 3 of this patch series. Right now this 
slowed down since I'm very busy and the ToDo-List is still very long.


My plan is to send out a version during this release cycle.

If you need it right now feel free to submit patches!

Philipp

On 19.04.2018 17:19, Kyle Evans wrote:

On Thu, Apr 19, 2018 at 10:13 AM, Icenowy Zheng <icen...@aosc.io> wrote:



于 2018年4月19日 GMT+08:00 下午11:11:22, Kyle Evans <kev...@freebsd.org> 写到:

On Mon, Jan 29, 2018 at 6:03 AM, Philipp Rossak <embe...@gmail.com>
wrote:



On 29.01.2018 10:52, Maxime Ripard wrote:


On Mon, Jan 29, 2018 at 12:29:17AM +0100, Philipp Rossak wrote:


This patch enables the the sid controller in the H3. It can be used
for thermal calibration data.

Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
   arch/arm/boot/dts/sun8i-h3.dtsi | 7 +++
   1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi
b/arch/arm/boot/dts/sun8i-h3.dtsi
index 3f83f6a27c74..9bb5cc29fec5 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -72,6 +72,13 @@
 };
 };
   + soc {
+   sid: eeprom@1c14000 {
+   compatible = "allwinner,sun8i-h3-sid";
+   reg = <0x01c14000 0x400>;
+   };
+   };
+



Shouldn't you also use a nvmem-cells property to the THS node?

Maxime



Oh seems like I forgot that.
As related to the wiki [1] this should be 64 bit wide at the address

0x34. I

will add that in the next version.


[1]: http://linux-sunxi.org/SID_Register_Guide#eFUSE

Thanks,
Philipp



Hi,

Any chance this will see a v3 soon? I'm kind of interested in sid node
for h3. =)


This patch is independent and can be easily sent out
by its own.



Right- I had considered doing so, but wanted to make sure I wasn't
going to collide with this series if a v3 is imminent.



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[linux-sunxi] Re: [RESEND PATCH v5 0/6] IR support for A83T

2018-03-02 Thread Philipp Rossak



On 13.02.2018 13:29, Philipp Rossak wrote:

This patch series adds support for the sunxi A83T ir module and enhances
the sunxi-ir driver. Right now the base clock frequency for the ir driver
is a hard coded define and is set to 8 MHz.
This works for the most common ir receivers. On the Sinovoip Bananapi M3
the ir receiver needs, a 3 MHz base clock frequency to work without
problems with this driver.

This patch series adds support for an optinal property that makes it able
to override the default base clock frequency and enables the ir interface
on the a83t and the Bananapi M3.

changes since v4:
* rename cir pin from cir_pins to r_cir_pin
* drop unit-adress from r_cir_pin
* add a83t compatible to the cir node
* move muxing options to dtsi
* rename cir label and reorder it in the bananpim3.dts file

changes since v3:
* collecting all acks & reviewd by
* fixed typos

changes since v2:
* reorder cir pin (alphabetical)
* fix typo in documentation

changes since v1:
* fix typos, reword Documentation
* initialize 'b_clk_freq' to 'SUNXI_IR_BASE_CLK' & remove if statement
* change dev_info() to dev_dbg()
* change naming to cir* in dts/dtsi
* Added acked Ackedi-by to related patch
* use whole memory block instead of registers needed + fix for h3/h5

changes since rfc:
* The property is now optinal. If the property is not available in
   the dtb the driver uses the default base clock frequency.
* the driver prints out the the selected base clock frequency.
* changed devicetree property from base-clk-frequency to clock-frequency

Regards,
Philipp

Philipp Rossak (6):
   media: rc: update sunxi-ir driver to get base clock frequency from
 devicetree
   media: dt: bindings: Update binding documentation for sunxi IR
 controller
   arm: dts: sun8i: a83t: Add the cir pin for the A83T
   arm: dts: sun8i: a83t: Add support for the cir interface
   arm: dts: sun8i: a83t: bananapi-m3: Enable IR controller
   arm: dts: sun8i: h3-h5: ir register size should be the whole memory
 block

  Documentation/devicetree/bindings/media/sunxi-ir.txt |  3 +++
  arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts |  5 +
  arch/arm/boot/dts/sun8i-a83t.dtsi| 18 ++
  arch/arm/boot/dts/sunxi-h3-h5.dtsi   |  2 +-
  drivers/media/rc/sunxi-cir.c | 19 +++
  5 files changed, 38 insertions(+), 9 deletions(-)



I talked yesterday with Maxime about this patch series. And he told me 
if the first to patches got merged, he will apply the dts patches to the 
sunxi tree.


Sean, can you merge the first two patches through the rc-core?

Thanks,
Philipp

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[linux-sunxi] Re: [RFC PATCH] ARM: configs: sunxi: Set ondemand govenor as default

2018-02-26 Thread Philipp Rossak



On 19.02.2018 09:10, Maxime Ripard wrote:

On Sat, Feb 17, 2018 at 03:22:35PM +0100, Philipp Rossak wrote:

Right now the performance govenor is the default frequency govenor on
sunxi devices. This causes some general problems.
When the cpu is idle the cpu runs with its maximum frequency.
This causes a higher cpu temperature in the idle state. When the cpu is
now under load the cpu gets with that higher idle temperature now faster
to its thermal limits.
An other big problem of the performace govenor is the missing
thermal throttling. Some tests with cpuburn resulted in a system crash
when the soc reached its thermal limits since no thermal throttling
occurred.


This won't change anything with cpuburn. While cpuburn will be
running, ondemand will increase the frequency of the cores to the
maximum frequency, putting yourself in the exact same situation.


I see here a totally different behavior on the hardware (Bananapi M2, A31s).
First ondemand increases the cpu frequency, when the maximum temperature 
is reached, then it throttles down the cpu step by step to its minimum.

And the cpu doesn't get killed, like with the performance govenor.

I can record some "logs" with RPi-Monitor if this is requiered.


The only difference is going to be when you're idle or have a rather
small CPU load. But then, you won't heat much in that case either.


With this patch we set the default frequency govenor to ondemand mode
and reduce the temperature when the cpu is idle and activate the thermal
throtteling.


This patch doesn't activate the thermal throttling.

Maxime



Sorry for my late reply!
Philipp

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[linux-sunxi] [PATCH v4] rtc: ac100: Fix ac100 determine rate bug

2018-02-26 Thread Philipp Rossak
This patch fixes a bug, that prevents the Allwinner A83T and the A80
from a successful boot.

The bug is there since v4.16-rc1 and appeared after the clk branch was
merged.

You can find the shortend trace below:

Unable to handle kernel NULL pointer dereference at virtual address

pgd = (ptrval)
[] *pgd=
Internal error: Oops: 5 [#1] SMP ARM
Modules linked in:
CPU: 0 PID: 49 Comm: kworker/0:1 Not tainted 4.15.0-10190-gb89e32ccd1be #2
Hardware name: Allwinner sun8i Family
Workqueue: events deferred_probe_work_func
PC is at clk_hw_get_rate+0x0/0x34
LR is at ac100_clkout_determine_rate+0x48/0x19c

[ ... ]

(clk_hw_get_rate) from (ac100_clkout_determine_rate+0x48/0x19c)
(ac100_clkout_determine_rate) from  (clk_core_set_rate_nolock+0x3c/0x1a0)
(clk_core_set_rate_nolock) from (clk_set_rate+0x30/0x88)
(clk_set_rate) from (of_clk_set_defaults+0x200/0x364)
(of_clk_set_defaults) from (platform_drv_probe+0x18/0xb0)

To fix that bug, we first check if the return of the
clk_hw_get_parent_by_index is non zero. If it is zero we skip that
clock parent.

The BUG report could be found here: https://lkml.org/lkml/2018/2/10/198

Fixes: 04940631b8d2 ("rtc: ac100: Add clk output support")

Signed-off-by: Philipp Rossak <embe...@gmail.com>
---

Changes in v4:
* add more information to the comment
Changes in v3:
* add information when the bug appeared 
* make the comment more clear
Changes in v2:
* add tag Fixes: ... to commit message
* add comment to if statement why we are doing this check

 drivers/rtc/rtc-ac100.c | 24 +++-
 1 file changed, 23 insertions(+), 1 deletion(-)

diff --git a/drivers/rtc/rtc-ac100.c b/drivers/rtc/rtc-ac100.c
index 8ff9dc3fe5bf..08ca8c46a8ff 100644
--- a/drivers/rtc/rtc-ac100.c
+++ b/drivers/rtc/rtc-ac100.c
@@ -183,7 +183,29 @@ static int ac100_clkout_determine_rate(struct clk_hw *hw,
 
for (i = 0; i < num_parents; i++) {
struct clk_hw *parent = clk_hw_get_parent_by_index(hw, i);
-   unsigned long tmp, prate = clk_hw_get_rate(parent);
+   unsigned long tmp, prate;
+
+   /*
+* The clock has two parents, one is a fixed clock which is
+* internally registered by the ac100 driver. The other parent
+* is a clock from the codec side of the chip, which we
+* properly declare and reference in the devicetree and is
+* not implemented in any driver right now.
+* If the clock core looks for the parent of that second
+* missing clock, it can't find one that is registered and
+* returns NULL.
+* So we end up in a situation where clk_hw_get_num_parents
+* returns the amount of clocks we can be parented to, but
+* clk_hw_get_parent_by_index will not return the orphan
+* clocks.
+* Thus we need to check if the parent exists before
+* we get the parent rate, so we could use the RTC
+* without waiting for the codec to be supported.
+*/
+   if (!parent)
+   continue;
+
+   prate = clk_hw_get_rate(parent);
 
tmp = ac100_clkout_round_rate(hw, req->rate, prate);
 
-- 
2.11.0

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[linux-sunxi] [RFC PATCH] ARM: configs: sunxi: Set ondemand govenor as default

2018-02-17 Thread Philipp Rossak
Right now the performance govenor is the default frequency govenor on
sunxi devices. This causes some general problems.
When the cpu is idle the cpu runs with its maximum frequency.
This causes a higher cpu temperature in the idle state. When the cpu is
now under load the cpu gets with that higher idle temperature now faster
to its thermal limits.
An other big problem of the performace govenor is the missing
thermal throttling. Some tests with cpuburn resulted in a system crash
when the soc reached its thermal limits since no thermal throttling
occurred.

With this patch we set the default frequency govenor to ondemand mode
and reduce the temperature when the cpu is idle and activate the thermal
throtteling.

Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
 arch/arm/configs/sunxi_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/configs/sunxi_defconfig b/arch/arm/configs/sunxi_defconfig
index df433abfcb02..e5812851091c 100644
--- a/arch/arm/configs/sunxi_defconfig
+++ b/arch/arm/configs/sunxi_defconfig
@@ -14,6 +14,7 @@ CONFIG_CMA=y
 CONFIG_ARM_APPENDED_DTB=y
 CONFIG_ARM_ATAG_DTB_COMPAT=y
 CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
 CONFIG_CPUFREQ_DT=y
 CONFIG_VFP=y
 CONFIG_NEON=y
-- 
2.11.0

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[linux-sunxi] Re: [PATCH v3] rtc: ac100: Fix ac100 determine rate bug

2018-02-16 Thread Philipp Rossak



On 16.02.2018 13:59, Chen-Yu Tsai wrote:

On Fri, Feb 16, 2018 at 8:49 PM, Philipp Rossak <embe...@gmail.com> wrote:



On 16.02.2018 05:10, Chen-Yu Tsai wrote:


On Fri, Feb 16, 2018 at 1:53 AM, Philipp Rossak <embe...@gmail.com> wrote:




On 15.02.2018 15:11, Maxime Ripard wrote:



On Wed, Feb 14, 2018 at 02:56:12PM +0100, Philipp Rossak wrote:



This patch fixes a bug, that prevents the Allwinner A83T and the A80
from a successful boot.

The bug is there since v4.16-rc1 and appeared after the clk branch was
merged.




Out of curiosity, which patch has introduced this? I couldn't find any
obvious match.



I wasn't also n



To be honest, I'm not sure why this is hitting you and not me.
I have both A83T boards that have assigned-clock-rates set for
the ac100 clock outputs for WiFi. I have them running 4.16-rc1
and have not seen this. The device tree patches that add these
are in 4.15.



Now it is getting curious ... .
I already mentioned that bug in the sunxi-irc and someone else was hitting
that problem also...
I tested it also with the same toolchain you are using (gcc 7.3.0-1 Debian),
but that didn't made any difference.

I don't think that issue is related with the Hardware, but to be on the save
side: Which Hardware version of the BPI-M3 do you have? I have version 1.2.

Can someone else can confirm this bug?


So I might have remembered wrong, as I just realized I have your
patch in my a83t branches. I don't hit this on the A80, which also
has the AC100, but doesn't use assigned-clock-rates in the device
tree.

Could you try rolling back to 4.15 and see if you still hit it?


Clean 4.15, no patches, just cloned before building: No issues.







You can find the shortend trace below:

Unable to handle kernel NULL pointer dereference at virtual address

pgd = (ptrval)
[] *pgd=
Internal error: Oops: 5 [#1] SMP ARM
Modules linked in:
CPU: 0 PID: 49 Comm: kworker/0:1 Not tainted 4.15.0-10190-gb89e32ccd1be
#2
Hardware name: Allwinner sun8i Family
Workqueue: events deferred_probe_work_func
PC is at clk_hw_get_rate+0x0/0x34
LR is at ac100_clkout_determine_rate+0x48/0x19c

[ ... ]

(clk_hw_get_rate) from (ac100_clkout_determine_rate+0x48/0x19c)
(ac100_clkout_determine_rate) from
(clk_core_set_rate_nolock+0x3c/0x1a0)
(clk_core_set_rate_nolock) from (clk_set_rate+0x30/0x88)
(clk_set_rate) from (of_clk_set_defaults+0x200/0x364)
(of_clk_set_defaults) from (platform_drv_probe+0x18/0xb0)

To fix that bug, we first check if the return of the
clk_hw_get_parent_by_index is non zero. If it is zero we skip that
clock parent.

The BUG report could be found here: https://lkml.org/lkml/2018/2/10/198

Fixes: 04940631b8d2 ("rtc: ac100: Add clk output support")

Signed-off-by: Philipp Rossak <embe...@gmail.com>
---

Changes in v3:
  * add information when the bug appeared
  * make the comment more clear
Changes in v2:
  * add tag Fixes: ... to commit message
  * add comment to if statement why we are doing this check

drivers/rtc/rtc-ac100.c | 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/drivers/rtc/rtc-ac100.c b/drivers/rtc/rtc-ac100.c
index 8ff9dc3fe5bf..2412aa2e8399 100644
--- a/drivers/rtc/rtc-ac100.c
+++ b/drivers/rtc/rtc-ac100.c
@@ -183,7 +183,24 @@ static int ac100_clkout_determine_rate(struct
clk_hw
*hw,
  for (i = 0; i < num_parents; i++) {
  struct clk_hw *parent = clk_hw_get_parent_by_index(hw,
i);
-   unsigned long tmp, prate = clk_hw_get_rate(parent);
+   unsigned long tmp, prate;
+
+   /*
+* The clock has two parents, one is a fixed clock
which
is
+* internally registered by the ac100 driver. The other
parent
+* is a clock from the codec side of the chip, which we
+* properly declare and reference in the devicetree and
is
+* not implemented in any driver right now.
+* If the clock core looks for the parent of that
second
+* missing clock, it can't one that is registered and
+* returns NULL.
+* Thus we need to check if the parent exists before
+* we get the parent rate.
+*/
+   if (!parent)
+   continue;




I'm sorry, but I still don't get it. When you register that clock, you
will give it two parents. Why would that change during the life of the
clock?

This really looks like a workaround rather than an actual fix.

Maxime


I agree this is more a workaround!
A proper solution/fix would be to define the devicetree correct like
this:

diff --git a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
index 6550bf0e594b..6f56d429f17e 100644
--- a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
@@ -175,11 +175,18 @@
 

[linux-sunxi] Re: [PATCH v3] rtc: ac100: Fix ac100 determine rate bug

2018-02-16 Thread Philipp Rossak



On 16.02.2018 05:10, Chen-Yu Tsai wrote:

On Fri, Feb 16, 2018 at 1:53 AM, Philipp Rossak <embe...@gmail.com> wrote:



On 15.02.2018 15:11, Maxime Ripard wrote:


On Wed, Feb 14, 2018 at 02:56:12PM +0100, Philipp Rossak wrote:


This patch fixes a bug, that prevents the Allwinner A83T and the A80
from a successful boot.

The bug is there since v4.16-rc1 and appeared after the clk branch was
merged.



Out of curiosity, which patch has introduced this? I couldn't find any
obvious match.



I wasn't also n


To be honest, I'm not sure why this is hitting you and not me.
I have both A83T boards that have assigned-clock-rates set for
the ac100 clock outputs for WiFi. I have them running 4.16-rc1
and have not seen this. The device tree patches that add these
are in 4.15.



Now it is getting curious ... .
I already mentioned that bug in the sunxi-irc and someone else was 
hitting that problem also...
I tested it also with the same toolchain you are using (gcc 7.3.0-1 
Debian), but that didn't made any difference.


I don't think that issue is related with the Hardware, but to be on the 
save side: Which Hardware version of the BPI-M3 do you have? I have 
version 1.2.


Can someone else can confirm this bug?




You can find the shortend trace below:

Unable to handle kernel NULL pointer dereference at virtual address

pgd = (ptrval)
[] *pgd=
Internal error: Oops: 5 [#1] SMP ARM
Modules linked in:
CPU: 0 PID: 49 Comm: kworker/0:1 Not tainted 4.15.0-10190-gb89e32ccd1be
#2
Hardware name: Allwinner sun8i Family
Workqueue: events deferred_probe_work_func
PC is at clk_hw_get_rate+0x0/0x34
LR is at ac100_clkout_determine_rate+0x48/0x19c

[ ... ]

(clk_hw_get_rate) from (ac100_clkout_determine_rate+0x48/0x19c)
(ac100_clkout_determine_rate) from  (clk_core_set_rate_nolock+0x3c/0x1a0)
(clk_core_set_rate_nolock) from (clk_set_rate+0x30/0x88)
(clk_set_rate) from (of_clk_set_defaults+0x200/0x364)
(of_clk_set_defaults) from (platform_drv_probe+0x18/0xb0)

To fix that bug, we first check if the return of the
clk_hw_get_parent_by_index is non zero. If it is zero we skip that
clock parent.

The BUG report could be found here: https://lkml.org/lkml/2018/2/10/198

Fixes: 04940631b8d2 ("rtc: ac100: Add clk output support")

Signed-off-by: Philipp Rossak <embe...@gmail.com>
---

Changes in v3:
 * add information when the bug appeared
 * make the comment more clear
Changes in v2:
 * add tag Fixes: ... to commit message
 * add comment to if statement why we are doing this check

   drivers/rtc/rtc-ac100.c | 19 ++-
   1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/drivers/rtc/rtc-ac100.c b/drivers/rtc/rtc-ac100.c
index 8ff9dc3fe5bf..2412aa2e8399 100644
--- a/drivers/rtc/rtc-ac100.c
+++ b/drivers/rtc/rtc-ac100.c
@@ -183,7 +183,24 @@ static int ac100_clkout_determine_rate(struct clk_hw
*hw,
 for (i = 0; i < num_parents; i++) {
 struct clk_hw *parent = clk_hw_get_parent_by_index(hw,
i);
-   unsigned long tmp, prate = clk_hw_get_rate(parent);
+   unsigned long tmp, prate;
+
+   /*
+* The clock has two parents, one is a fixed clock which
is
+* internally registered by the ac100 driver. The other
parent
+* is a clock from the codec side of the chip, which we
+* properly declare and reference in the devicetree and
is
+* not implemented in any driver right now.
+* If the clock core looks for the parent of that second
+* missing clock, it can't one that is registered and
+* returns NULL.
+* Thus we need to check if the parent exists before
+* we get the parent rate.
+*/
+   if (!parent)
+   continue;



I'm sorry, but I still don't get it. When you register that clock, you
will give it two parents. Why would that change during the life of the
clock?

This really looks like a workaround rather than an actual fix.

Maxime


I agree this is more a workaround!
A proper solution/fix would be to define the devicetree correct like this:

diff --git a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
index 6550bf0e594b..6f56d429f17e 100644
--- a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
@@ -175,11 +175,18 @@
 compatible = "x-powers,ac100-rtc";
 interrupt-parent = <_intc>;
 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
-   clocks = <_codec>;
+   clocks = <_rtc_32k>;
 #clock-cells = <1>;
 clock-output-names = "cko1_rtc",
  

[linux-sunxi] Re: [PATCH v3] rtc: ac100: Fix ac100 determine rate bug

2018-02-15 Thread Philipp Rossak



On 15.02.2018 15:11, Maxime Ripard wrote:

On Wed, Feb 14, 2018 at 02:56:12PM +0100, Philipp Rossak wrote:

This patch fixes a bug, that prevents the Allwinner A83T and the A80
from a successful boot.

The bug is there since v4.16-rc1 and appeared after the clk branch was
merged.


Out of curiosity, which patch has introduced this? I couldn't find any
obvious match.



I wasn't also n


You can find the shortend trace below:

Unable to handle kernel NULL pointer dereference at virtual address

pgd = (ptrval)
[] *pgd=
Internal error: Oops: 5 [#1] SMP ARM
Modules linked in:
CPU: 0 PID: 49 Comm: kworker/0:1 Not tainted 4.15.0-10190-gb89e32ccd1be #2
Hardware name: Allwinner sun8i Family
Workqueue: events deferred_probe_work_func
PC is at clk_hw_get_rate+0x0/0x34
LR is at ac100_clkout_determine_rate+0x48/0x19c

[ ... ]

(clk_hw_get_rate) from (ac100_clkout_determine_rate+0x48/0x19c)
(ac100_clkout_determine_rate) from  (clk_core_set_rate_nolock+0x3c/0x1a0)
(clk_core_set_rate_nolock) from (clk_set_rate+0x30/0x88)
(clk_set_rate) from (of_clk_set_defaults+0x200/0x364)
(of_clk_set_defaults) from (platform_drv_probe+0x18/0xb0)

To fix that bug, we first check if the return of the
clk_hw_get_parent_by_index is non zero. If it is zero we skip that
clock parent.

The BUG report could be found here: https://lkml.org/lkml/2018/2/10/198

Fixes: 04940631b8d2 ("rtc: ac100: Add clk output support")

Signed-off-by: Philipp Rossak <embe...@gmail.com>
---

Changes in v3:
* add information when the bug appeared
* make the comment more clear
Changes in v2:
* add tag Fixes: ... to commit message
* add comment to if statement why we are doing this check

  drivers/rtc/rtc-ac100.c | 19 ++-
  1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/drivers/rtc/rtc-ac100.c b/drivers/rtc/rtc-ac100.c
index 8ff9dc3fe5bf..2412aa2e8399 100644
--- a/drivers/rtc/rtc-ac100.c
+++ b/drivers/rtc/rtc-ac100.c
@@ -183,7 +183,24 @@ static int ac100_clkout_determine_rate(struct clk_hw *hw,
  
  	for (i = 0; i < num_parents; i++) {

struct clk_hw *parent = clk_hw_get_parent_by_index(hw, i);
-   unsigned long tmp, prate = clk_hw_get_rate(parent);
+   unsigned long tmp, prate;
+
+   /*
+* The clock has two parents, one is a fixed clock which is
+* internally registered by the ac100 driver. The other parent
+* is a clock from the codec side of the chip, which we
+* properly declare and reference in the devicetree and is
+* not implemented in any driver right now.
+* If the clock core looks for the parent of that second
+* missing clock, it can't one that is registered and
+* returns NULL.
+* Thus we need to check if the parent exists before
+* we get the parent rate.
+*/
+   if (!parent)
+   continue;


I'm sorry, but I still don't get it. When you register that clock, you
will give it two parents. Why would that change during the life of the
clock?

This really looks like a workaround rather than an actual fix.

Maxime


I agree this is more a workaround!
A proper solution/fix would be to define the devicetree correct like this:

diff --git a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts 
b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts

index 6550bf0e594b..6f56d429f17e 100644
--- a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
@@ -175,11 +175,18 @@
compatible = "x-powers,ac100-rtc";
interrupt-parent = <_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
-   clocks = <_codec>;
+   clocks = <_rtc_32k>;
#clock-cells = <1>;
clock-output-names = "cko1_rtc",
 "cko2_rtc",
 "cko3_rtc";
+
+   ac100_rtc_32k: rtc-32k-oscillator {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency  = <32768>;
+   clock-output-names = "ac100-rtc-32k";
+   };
};
};
 };

What do you think about that solution?

I already tested it and it looks like it is working.

Philipp

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[linux-sunxi] Re: [PATCH v2 0/2] Fix broken bananapi m2 devicetree/regulators

2018-02-15 Thread Philipp Rossak



On 15.02.2018 10:08, Maxime Ripard wrote:

On Wed, Feb 14, 2018 at 03:10:23PM +0100, Philipp Rossak wrote:

This patchseries fixes the bananapi m1 devicetree, to be able to boot again.
The first two patches update/improve the devicetree and the last patch adds
all missing regulators.

Regards,
Philipp

Changes since v1:
* squashed commit 1 and 3
* fix wrong mmc regulator

Philipp Rossak (2):
   arm: dts: sun6i: a31s: bpi-m2: improve pmic properties
   arm: dts: sun6i: a31s: fix: bpi-m2: add missing regulators


Applied both.

I had to make a couple of changes though, in the commit title arm
should be uppercase, and the fix isn't needed.

I also added stable in Cc, since these patches have been there for
quite some time.

Maxime



Thanks!

Philipp

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[linux-sunxi] [PATCH v2 2/2] arm: dts: sun6i: a31s: fix: bpi-m2: add missing regulators

2018-02-14 Thread Philipp Rossak
This patch fixes a bootproblem with the Bananapi M2 board. Since there
are some regulators missing we add them right now. Those values come
from the schematic, below you can find a small overview:

* reg_aldo1:  3,3V, powers the wifi
* reg_aldo2:  2,5V, powers the IO of the RTL8211E
* reg_aldo3:  3,3V, powers the audio

* reg_dldo1:  3,0V, powers the RTL8211E
* reg_dldo2:  2,8V, powers the analog part of the csi
* reg_dldo3:  3,3V, powers misc
* reg_eldo1:  1,8V, powers the csi
* reg_ldo_io1:1,8V, powers the gpio

* reg_dc5ldo: needs to be always on

This patch updates also the vmmc-supply properties on the mmc0 and mmc2
node to use the allready existent regulators.
We can now remove the sunxi-common-regulators.dtsi include since we
don't need it anymore.

Fixes: 7daa21370075 ("ARM: dts: sunxi: Add regulators for Sinovoip
BPI-M2")

Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
 arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts | 61 ++--
 1 file changed, 58 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts 
b/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts
index fb34f32502cf..b2758dd8ce43 100644
--- a/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts
+++ b/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts
@@ -42,7 +42,6 @@
 
 /dts-v1/;
 #include "sun6i-a31s.dtsi"
-#include "sunxi-common-regulators.dtsi"
 #include 
 
 / {
@@ -99,6 +98,7 @@
pinctrl-0 = <_pins_rgmii_a>, <_phy_reset_pin_bpi_m2>;
phy = <>;
phy-mode = "rgmii";
+   phy-supply = <_dldo1>;
snps,reset-gpio = < 0 21 GPIO_ACTIVE_HIGH>; /* PA21 */
snps,reset-active-low;
snps,reset-delays-us = <0 1 3>;
@@ -118,7 +118,7 @@
  {
pinctrl-names = "default";
pinctrl-0 = <_pins_a>, <_cd_pin_bpi_m2>;
-   vmmc-supply = <_vcc3v0>;
+   vmmc-supply = <_dcdc1>;
bus-width = <4>;
cd-gpios = < 0 4 GPIO_ACTIVE_HIGH>; /* PA4 */
cd-inverted;
@@ -132,7 +132,7 @@
  {
pinctrl-names = "default";
pinctrl-0 = <_pins_a>;
-   vmmc-supply = <_vcc3v0>;
+   vmmc-supply = <_aldo1>;
mmc-pwrseq = <_pwrseq>;
bus-width = <4>;
non-removable;
@@ -195,7 +195,28 @@
 
 #include "axp22x.dtsi"
 
+_aldo1 {
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   regulator-name = "vcc-wifi";
+};
+
+_aldo2 {
+   regulator-always-on;
+   regulator-min-microvolt = <250>;
+   regulator-max-microvolt = <250>;
+   regulator-name = "vcc-gmac";
+};
+
+_aldo3 {
+   regulator-always-on;
+   regulator-min-microvolt = <300>;
+   regulator-max-microvolt = <300>;
+   regulator-name = "avcc";
+};
+
 _dc5ldo {
+   regulator-always-on;
regulator-min-microvolt = <70>;
regulator-max-microvolt = <132>;
regulator-name = "vdd-cpus";
@@ -235,6 +256,40 @@
regulator-name = "vcc-dram";
 };
 
+_dldo1 {
+   regulator-min-microvolt = <300>;
+   regulator-max-microvolt = <300>;
+   regulator-name = "vcc-mac";
+};
+
+_dldo2 {
+   regulator-min-microvolt = <280>;
+   regulator-max-microvolt = <280>;
+   regulator-name = "avdd-csi";
+};
+
+_dldo3 {
+   regulator-always-on;
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   regulator-name = "vcc-pb";
+};
+
+_eldo1 {
+   regulator-min-microvolt = <180>;
+   regulator-max-microvolt = <180>;
+   regulator-name = "vdd-csi";
+   status = "okay";
+};
+
+_ldo_io1 {
+   regulator-always-on;
+   regulator-min-microvolt = <180>;
+   regulator-max-microvolt = <180>;
+   regulator-name = "vcc-pm-cpus";
+   status = "okay";
+};
+
  {
pinctrl-names = "default";
pinctrl-0 = <_pins_a>;
-- 
2.11.0

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[linux-sunxi] [PATCH v2 1/2] arm: dts: sun6i: a31s: bpi-m2: improve pmic properties

2018-02-14 Thread Philipp Rossak
The eldoin is supplied from the dcdc1 regulator. The N_VBUSEN pin is
connected to an external power regulator (SY6280AAC).
With this commit we update the pmic binding properties to support
those features.

Fixes: 7daa21370075 ("ARM: dts: sunxi: Add regulators for Sinovoip
BPI-M2")

Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
 arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts 
b/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts
index 51e6f1d21c32..fb34f32502cf 100644
--- a/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts
+++ b/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts
@@ -163,6 +163,8 @@
reg = <0x68>;
interrupt-parent = <_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+   eldoin-supply = <_dcdc1>;
+   x-powers,drive-vbus-en;
};
 };
 
-- 
2.11.0

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[linux-sunxi] [PATCH v2 0/2] Fix broken bananapi m2 devicetree/regulators

2018-02-14 Thread Philipp Rossak
This patchseries fixes the bananapi m1 devicetree, to be able to boot again.
The first two patches update/improve the devicetree and the last patch adds
all missing regulators.

Regards,
Philipp

Changes since v1:
* squashed commit 1 and 3
* fix wrong mmc regulator

Philipp Rossak (2):
  arm: dts: sun6i: a31s: bpi-m2: improve pmic properties
  arm: dts: sun6i: a31s: fix: bpi-m2: add missing regulators

 arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts | 63 ++--
 1 file changed, 60 insertions(+), 3 deletions(-)

-- 
2.11.0

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[linux-sunxi] [PATCH v3] rtc: ac100: Fix ac100 determine rate bug

2018-02-14 Thread Philipp Rossak
This patch fixes a bug, that prevents the Allwinner A83T and the A80
from a successful boot.

The bug is there since v4.16-rc1 and appeared after the clk branch was
merged.

You can find the shortend trace below:

Unable to handle kernel NULL pointer dereference at virtual address

pgd = (ptrval)
[] *pgd=
Internal error: Oops: 5 [#1] SMP ARM
Modules linked in:
CPU: 0 PID: 49 Comm: kworker/0:1 Not tainted 4.15.0-10190-gb89e32ccd1be #2
Hardware name: Allwinner sun8i Family
Workqueue: events deferred_probe_work_func
PC is at clk_hw_get_rate+0x0/0x34
LR is at ac100_clkout_determine_rate+0x48/0x19c

[ ... ]

(clk_hw_get_rate) from (ac100_clkout_determine_rate+0x48/0x19c)
(ac100_clkout_determine_rate) from  (clk_core_set_rate_nolock+0x3c/0x1a0)
(clk_core_set_rate_nolock) from (clk_set_rate+0x30/0x88)
(clk_set_rate) from (of_clk_set_defaults+0x200/0x364)
(of_clk_set_defaults) from (platform_drv_probe+0x18/0xb0)

To fix that bug, we first check if the return of the
clk_hw_get_parent_by_index is non zero. If it is zero we skip that
clock parent.

The BUG report could be found here: https://lkml.org/lkml/2018/2/10/198

Fixes: 04940631b8d2 ("rtc: ac100: Add clk output support")

Signed-off-by: Philipp Rossak <embe...@gmail.com>
---

Changes in v3:
* add information when the bug appeared 
* make the comment more clear
Changes in v2:
* add tag Fixes: ... to commit message
* add comment to if statement why we are doing this check

 drivers/rtc/rtc-ac100.c | 19 ++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/drivers/rtc/rtc-ac100.c b/drivers/rtc/rtc-ac100.c
index 8ff9dc3fe5bf..2412aa2e8399 100644
--- a/drivers/rtc/rtc-ac100.c
+++ b/drivers/rtc/rtc-ac100.c
@@ -183,7 +183,24 @@ static int ac100_clkout_determine_rate(struct clk_hw *hw,
 
for (i = 0; i < num_parents; i++) {
struct clk_hw *parent = clk_hw_get_parent_by_index(hw, i);
-   unsigned long tmp, prate = clk_hw_get_rate(parent);
+   unsigned long tmp, prate;
+
+   /*
+* The clock has two parents, one is a fixed clock which is
+* internally registered by the ac100 driver. The other parent
+* is a clock from the codec side of the chip, which we
+* properly declare and reference in the devicetree and is
+* not implemented in any driver right now.
+* If the clock core looks for the parent of that second
+* missing clock, it can't one that is registered and
+* returns NULL.
+* Thus we need to check if the parent exists before
+* we get the parent rate.
+*/
+   if (!parent)
+   continue;
+
+   prate = clk_hw_get_rate(parent);
 
tmp = ac100_clkout_round_rate(hw, req->rate, prate);
 
-- 
2.11.0

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Re: [linux-sunxi] [PATCH v2] rtc: ac100: Fix ac100 determine rate bug

2018-02-13 Thread Philipp Rossak



On 13.02.2018 14:44, Chen-Yu Tsai wrote:

On Tue, Feb 13, 2018 at 9:32 PM, Maxime Ripard
<maxime.rip...@bootlin.com> wrote:

On Tue, Feb 13, 2018 at 01:14:14PM +0100, Philipp Rossak wrote:

This patch fixes a bug, that prevents the Allwinner A83T and the A80
from a successful boot. You can find the shortend trace below:


Since when is it there?

The bug is there since v4.16-rc1 and appeared after the clk branch was 
merged.


^^ Should I add this info also in the commit message?


Unable to handle kernel NULL pointer dereference at virtual address

pgd = (ptrval)
[] *pgd=
Internal error: Oops: 5 [#1] SMP ARM
Modules linked in:
CPU: 0 PID: 49 Comm: kworker/0:1 Not tainted 4.15.0-10190-gb89e32ccd1be #2
Hardware name: Allwinner sun8i Family
Workqueue: events deferred_probe_work_func
PC is at clk_hw_get_rate+0x0/0x34
LR is at ac100_clkout_determine_rate+0x48/0x19c

[ ... ]

(clk_hw_get_rate) from (ac100_clkout_determine_rate+0x48/0x19c)
(ac100_clkout_determine_rate) from  (clk_core_set_rate_nolock+0x3c/0x1a0)
(clk_core_set_rate_nolock) from (clk_set_rate+0x30/0x88)
(clk_set_rate) from (of_clk_set_defaults+0x200/0x364)
(of_clk_set_defaults) from (platform_drv_probe+0x18/0xb0)

To fix that bug, we first check if the return of the
clk_hw_get_parent_by_index is non zero. If it is zero we skip that
clock parent.

The BUG report could be found here: https://lkml.org/lkml/2018/2/10/198

Fixes: 04940631b8d2 ("rtc: ac100: Add clk output support")


Should it be sent to stable?


Signed-off-by: Philipp Rossak <embe...@gmail.com>
---

Changes in v2:
   * add tag Fixes: ... to commit message
   * add comment to if statement why we are doing this check

  drivers/rtc/rtc-ac100.c | 12 +++-
  1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/rtc/rtc-ac100.c b/drivers/rtc/rtc-ac100.c
index 8ff9dc3fe5bf..ba73201d8cc1 100644
--- a/drivers/rtc/rtc-ac100.c
+++ b/drivers/rtc/rtc-ac100.c
@@ -183,7 +183,17 @@ static int ac100_clkout_determine_rate(struct clk_hw *hw,

   for (i = 0; i < num_parents; i++) {
   struct clk_hw *parent = clk_hw_get_parent_by_index(hw, i);
- unsigned long tmp, prate = clk_hw_get_rate(parent);
+ unsigned long tmp, prate;
+
+ /*
+  * We purposefully left open the possibility to use the clock
+  * from the codec side but it is not implemented right now.
+  * Thus we need to check if the parent exists.
+  */
+ if (!parent)
+ continue;
+
+ prate = clk_hw_get_rate(parent);


clk_hw_get_num_parents should return the exact number of parents,
which is going to be 1 if you only have one parent, like all DTS seems
to have.

If not, then it should be explained in the comment and / or fixed
properly.


The clock has two parents. One is a fixed clock internally registered
by the driver. This is actually an external crystal, and we should
probably add a device node and the works for it. The other parent
is a clock from the codec side, which we properly declare and
reference in the device tree. This clock, though defined, is not
implemented in any driver (because we don't have any ATM).

This second missing clock is what's causing issues here. The clk core
looks for the parent by name, can't find one that is registered, and
returns NULL.

I guess the comment above is still not clear enough?


I can get more detailed in the comment. I thought about this:

The clock has two parents, one is a fixed clock which is internally 
registered by the ac100 driver. The other parent is a clock from the 
codec side of the chip, which we properly declare and reference in the 
devicetree and is not implemented in any driver right now.
If the clock core looks for the parent of that second missing clock, it 
can't one that is registered and returns NULL.

Thus we need to check if the parent exists before we get the parent rate.

Is that ok for you?

Philipp



ChenYu


Maxime

--
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Embedded Linux and Kernel engineering
http://bootlin.com


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[linux-sunxi] [RESEND PATCH v5 4/6] arm: dts: sun8i: a83t: Add support for the cir interface

2018-02-13 Thread Philipp Rossak
The cir interface is like on the H3 located at 0x01f02000 and is exactly
the same. This patch adds support for the ir interface on the A83T.

Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 13 +
 1 file changed, 13 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index f7f78a27e21d..1e04a5cfd32d 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -704,6 +704,19 @@
#reset-cells = <1>;
};
 
+   r_cir: ir@1f02000 {
+   compatible = "allwinner,sun8i-a83t-ir",
+"allwinner,sun5i-a13-ir";
+   clocks = <_ccu CLK_APB0_IR>, <_ccu CLK_IR>;
+   clock-names = "apb", "ir";
+   resets = <_ccu RST_APB0_IR>;
+   interrupts = ;
+   reg = <0x01f02000 0x400>;
+   pinctrl-names = "default";
+   pinctrl-0 = <_cir_pin>;
+   status = "disabled";
+   };
+
r_pio: pinctrl@1f02c00 {
compatible = "allwinner,sun8i-a83t-r-pinctrl";
reg = <0x01f02c00 0x400>;
-- 
2.11.0

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[linux-sunxi] [RESEND PATCH v5 2/6] media: dt: bindings: Update binding documentation for sunxi IR controller

2018-02-13 Thread Philipp Rossak
This patch updates documentation for Device-Tree bindings for sunxi IR
controller and adds the new optional property for the base clock
frequency.

Signed-off-by: Philipp Rossak <embe...@gmail.com>
Acked-by: Maxime Ripard <maxime.rip...@free-electrons.com>
Reviewed-by: Rob Herring <r...@kernel.org>
---
 Documentation/devicetree/bindings/media/sunxi-ir.txt | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/media/sunxi-ir.txt 
b/Documentation/devicetree/bindings/media/sunxi-ir.txt
index 91648c569b1e..278098987edb 100644
--- a/Documentation/devicetree/bindings/media/sunxi-ir.txt
+++ b/Documentation/devicetree/bindings/media/sunxi-ir.txt
@@ -11,6 +11,8 @@ Required properties:
 Optional properties:
 - linux,rc-map-name: see rc.txt file in the same directory.
 - resets : phandle + reset specifier pair
+- clock-frequency  : IR Receiver clock frequency, in Hertz. Defaults to 8 MHz
+if missing.
 
 Example:
 
@@ -18,6 +20,7 @@ ir0: ir@1c21800 {
compatible = "allwinner,sun4i-a10-ir";
clocks = <_gates 6>, <_clk>;
clock-names = "apb", "ir";
+   clock-frequency = <300>;
resets = <_rst 1>;
interrupts = <0 5 1>;
reg = <0x01C21800 0x40>;
-- 
2.11.0

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[linux-sunxi] [RESEND PATCH v5 1/6] media: rc: update sunxi-ir driver to get base clock frequency from devicetree

2018-02-13 Thread Philipp Rossak
This patch updates the sunxi-ir driver to set the base clock frequency from
devicetree.

This is necessary since there are different ir receivers on the
market, that operate with different frequencies. So this value could be
set if the attached ir receiver needs a different base clock frequency,
than the default 8 MHz.

Signed-off-by: Philipp Rossak <embe...@gmail.com>
Reviewed-by: Andi Shyti <andi.sh...@samsung.com>
Acked-by: Sean Young <s...@mess.org>
---
 drivers/media/rc/sunxi-cir.c | 19 +++
 1 file changed, 11 insertions(+), 8 deletions(-)

diff --git a/drivers/media/rc/sunxi-cir.c b/drivers/media/rc/sunxi-cir.c
index 97f367b446c4..f500cea228a9 100644
--- a/drivers/media/rc/sunxi-cir.c
+++ b/drivers/media/rc/sunxi-cir.c
@@ -72,12 +72,8 @@
 /* CIR_REG register idle threshold */
 #define REG_CIR_ITHR(val)(((val) << 8) & (GENMASK(15, 8)))
 
-/* Required frequency for IR0 or IR1 clock in CIR mode */
+/* Required frequency for IR0 or IR1 clock in CIR mode (default) */
 #define SUNXI_IR_BASE_CLK 800
-/* Frequency after IR internal divider  */
-#define SUNXI_IR_CLK  (SUNXI_IR_BASE_CLK / 64)
-/* Sample period in ns */
-#define SUNXI_IR_SAMPLE   (10ul / SUNXI_IR_CLK)
 /* Noise threshold in samples  */
 #define SUNXI_IR_RXNOISE  1
 /* Idle Threshold in samples */
@@ -122,7 +118,8 @@ static irqreturn_t sunxi_ir_irq(int irqno, void *dev_id)
/* for each bit in fifo */
dt = readb(ir->base + SUNXI_IR_RXFIFO_REG);
rawir.pulse = (dt & 0x80) != 0;
-   rawir.duration = ((dt & 0x7f) + 1) * SUNXI_IR_SAMPLE;
+   rawir.duration = ((dt & 0x7f) + 1) *
+ir->rc->rx_resolution;
ir_raw_event_store_with_filter(ir->rc, );
}
}
@@ -148,6 +145,7 @@ static int sunxi_ir_probe(struct platform_device *pdev)
struct device_node *dn = dev->of_node;
struct resource *res;
struct sunxi_ir *ir;
+   u32 b_clk_freq = SUNXI_IR_BASE_CLK;
 
ir = devm_kzalloc(dev, sizeof(struct sunxi_ir), GFP_KERNEL);
if (!ir)
@@ -172,6 +170,9 @@ static int sunxi_ir_probe(struct platform_device *pdev)
return PTR_ERR(ir->clk);
}
 
+   /* Base clock frequency (optional) */
+   of_property_read_u32(dn, "clock-frequency", _clk_freq);
+
/* Reset (optional) */
ir->rst = devm_reset_control_get_optional_exclusive(dev, NULL);
if (IS_ERR(ir->rst))
@@ -180,11 +181,12 @@ static int sunxi_ir_probe(struct platform_device *pdev)
if (ret)
return ret;
 
-   ret = clk_set_rate(ir->clk, SUNXI_IR_BASE_CLK);
+   ret = clk_set_rate(ir->clk, b_clk_freq);
if (ret) {
dev_err(dev, "set ir base clock failed!\n");
goto exit_reset_assert;
}
+   dev_dbg(dev, "set base clock frequency to %d Hz.\n", b_clk_freq);
 
if (clk_prepare_enable(ir->apb_clk)) {
dev_err(dev, "try to enable apb_ir_clk failed\n");
@@ -225,7 +227,8 @@ static int sunxi_ir_probe(struct platform_device *pdev)
ir->rc->map_name = ir->map_name ?: RC_MAP_EMPTY;
ir->rc->dev.parent = dev;
ir->rc->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;
-   ir->rc->rx_resolution = SUNXI_IR_SAMPLE;
+   /* Frequency after IR internal divider with sample period in ns */
+   ir->rc->rx_resolution = (10ul / (b_clk_freq / 64));
ir->rc->timeout = MS_TO_NS(SUNXI_IR_TIMEOUT);
ir->rc->driver_name = SUNXI_IR_DEV;
 
-- 
2.11.0

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[linux-sunxi] [RESEND PATCH v5 3/6] arm: dts: sun8i: a83t: Add the cir pin for the A83T

2018-02-13 Thread Philipp Rossak
The CIR Pin of the A83T is located at PL12.

Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 7f4955a5fab7..f7f78a27e21d 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -716,6 +716,11 @@
interrupt-controller;
#interrupt-cells = <3>;
 
+   r_cir_pin: r-cir-pin {
+   pins = "PL12";
+   function = "s_cir_rx";
+   };
+
r_rsb_pins: r-rsb-pins {
pins = "PL0", "PL1";
function = "s_rsb";
-- 
2.11.0

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[linux-sunxi] [RESEND PATCH v5 5/6] arm: dts: sun8i: a83t: bananapi-m3: Enable IR controller

2018-02-13 Thread Philipp Rossak
The Bananapi M3 has an onboard IR receiver.
This enables the onboard IR receiver subnode.
Unlike the other IR receivers this one needs a base clock frequency
of 300 Hz (3 MHz), to be able to work.

Signed-off-by: Philipp Rossak <embe...@gmail.com>
Acked-by: Chen-Yu Tsai <w...@csie.org>
---
 arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts 
b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
index 6550bf0e594b..26c015fd4f4d 100644
--- a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
@@ -145,6 +145,11 @@
status = "okay";
 };
 
+_cir {
+   clock-frequency = <300>;
+   status = "okay";
+};
+
 _rsb {
status = "okay";
 
-- 
2.11.0

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[linux-sunxi] [RESEND PATCH v5 6/6] arm: dts: sun8i: h3-h5: ir register size should be the whole memory block

2018-02-13 Thread Philipp Rossak
The size of the register should be the size of the whole memory block,
not just the registers, that are needed.

Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
 arch/arm/boot/dts/sunxi-h3-h5.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi 
b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index 7a83b15225c7..22f6e126b8df 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -712,7 +712,7 @@
clock-names = "apb", "ir";
resets = <_ccu RST_APB0_IR>;
interrupts = ;
-   reg = <0x01f02000 0x40>;
+   reg = <0x01f02000 0x400>;
status = "disabled";
};
 
-- 
2.11.0

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[linux-sunxi] [RESEND PATCH v5 0/6] IR support for A83T

2018-02-13 Thread Philipp Rossak
This patch series adds support for the sunxi A83T ir module and enhances 
the sunxi-ir driver. Right now the base clock frequency for the ir driver
is a hard coded define and is set to 8 MHz.
This works for the most common ir receivers. On the Sinovoip Bananapi M3 
the ir receiver needs, a 3 MHz base clock frequency to work without
problems with this driver.

This patch series adds support for an optinal property that makes it able
to override the default base clock frequency and enables the ir interface 
on the a83t and the Bananapi M3.

changes since v4:
* rename cir pin from cir_pins to r_cir_pin
* drop unit-adress from r_cir_pin
* add a83t compatible to the cir node
* move muxing options to dtsi
* rename cir label and reorder it in the bananpim3.dts file

changes since v3:
* collecting all acks & reviewd by
* fixed typos

changes since v2:
* reorder cir pin (alphabetical)
* fix typo in documentation

changes since v1:
* fix typos, reword Documentation
* initialize 'b_clk_freq' to 'SUNXI_IR_BASE_CLK' & remove if statement
* change dev_info() to dev_dbg()
* change naming to cir* in dts/dtsi
* Added acked Ackedi-by to related patch
* use whole memory block instead of registers needed + fix for h3/h5

changes since rfc:
* The property is now optinal. If the property is not available in 
  the dtb the driver uses the default base clock frequency.
* the driver prints out the the selected base clock frequency.
* changed devicetree property from base-clk-frequency to clock-frequency

Regards,
Philipp

Philipp Rossak (6):
  media: rc: update sunxi-ir driver to get base clock frequency from
devicetree
  media: dt: bindings: Update binding documentation for sunxi IR
controller
  arm: dts: sun8i: a83t: Add the cir pin for the A83T
  arm: dts: sun8i: a83t: Add support for the cir interface
  arm: dts: sun8i: a83t: bananapi-m3: Enable IR controller
  arm: dts: sun8i: h3-h5: ir register size should be the whole memory
block

 Documentation/devicetree/bindings/media/sunxi-ir.txt |  3 +++
 arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts |  5 +
 arch/arm/boot/dts/sun8i-a83t.dtsi| 18 ++
 arch/arm/boot/dts/sunxi-h3-h5.dtsi   |  2 +-
 drivers/media/rc/sunxi-cir.c | 19 +++
 5 files changed, 38 insertions(+), 9 deletions(-)

-- 
2.11.0

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[linux-sunxi] [PATCH v2] rtc: ac100: Fix ac100 determine rate bug

2018-02-13 Thread Philipp Rossak
This patch fixes a bug, that prevents the Allwinner A83T and the A80
from a successful boot. You can find the shortend trace below:

Unable to handle kernel NULL pointer dereference at virtual address

pgd = (ptrval)
[] *pgd=
Internal error: Oops: 5 [#1] SMP ARM
Modules linked in:
CPU: 0 PID: 49 Comm: kworker/0:1 Not tainted 4.15.0-10190-gb89e32ccd1be #2
Hardware name: Allwinner sun8i Family
Workqueue: events deferred_probe_work_func
PC is at clk_hw_get_rate+0x0/0x34
LR is at ac100_clkout_determine_rate+0x48/0x19c

[ ... ]

(clk_hw_get_rate) from (ac100_clkout_determine_rate+0x48/0x19c)
(ac100_clkout_determine_rate) from  (clk_core_set_rate_nolock+0x3c/0x1a0)
(clk_core_set_rate_nolock) from (clk_set_rate+0x30/0x88)
(clk_set_rate) from (of_clk_set_defaults+0x200/0x364)
(of_clk_set_defaults) from (platform_drv_probe+0x18/0xb0)

To fix that bug, we first check if the return of the
clk_hw_get_parent_by_index is non zero. If it is zero we skip that
clock parent.

The BUG report could be found here: https://lkml.org/lkml/2018/2/10/198

Fixes: 04940631b8d2 ("rtc: ac100: Add clk output support")

Signed-off-by: Philipp Rossak <embe...@gmail.com>
---

Changes in v2:
* add tag Fixes: ... to commit message
* add comment to if statement why we are doing this check

 drivers/rtc/rtc-ac100.c | 12 +++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/rtc/rtc-ac100.c b/drivers/rtc/rtc-ac100.c
index 8ff9dc3fe5bf..ba73201d8cc1 100644
--- a/drivers/rtc/rtc-ac100.c
+++ b/drivers/rtc/rtc-ac100.c
@@ -183,7 +183,17 @@ static int ac100_clkout_determine_rate(struct clk_hw *hw,
 
for (i = 0; i < num_parents; i++) {
struct clk_hw *parent = clk_hw_get_parent_by_index(hw, i);
-   unsigned long tmp, prate = clk_hw_get_rate(parent);
+   unsigned long tmp, prate;
+
+   /*
+* We purposefully left open the possibility to use the clock
+* from the codec side but it is not implemented right now.
+* Thus we need to check if the parent exists.
+*/
+   if (!parent)
+   continue;
+
+   prate = clk_hw_get_rate(parent);
 
tmp = ac100_clkout_round_rate(hw, req->rate, prate);
 
-- 
2.11.0

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[linux-sunxi] Re: BUG: A31s Not booting anymore

2018-02-13 Thread Philipp Rossak



On 13.02.2018 03:59, Chen-Yu Tsai wrote:

On Tue, Feb 13, 2018 at 9:25 AM, Philipp Rossak <embe...@gmail.com> wrote:



On 12.02.2018 19:21, Philipp Rossak wrote:


Hey,

When I try to boot my A31s (Bananapi M2) u-boot is showing only Starting
kernel ... . After enabling the earlyprintk I could capture this log: [1].

After reverting those 5 commits from Chen-Yu I was able to boot again:


clk: sunxi-ng: Support fixed post-dividers on NM style clocks
7d333ef1cc1b8c8951f3a2c41f6406e2295d8be9

clk: sunxi-ng: sun8i: a83t: Add /2 fixed post divider to audio PLL
10e6eb4f2c5b35ae71c9bc0db83d74238719b453

clk: sunxi-ng: sun8i: a83t: Use sigma-delta modulation for audio PLL
e952ca3c6b2ffdfbf9618e4bd3e9aad1ff3f5eb4

clk: sunxi-ng: Support fixed post-dividers on MP style clocks
946797aa3f08e2f6f5992f3ec2be44791e9b9260

clk: sunxi-ng: sun50i: a64: Add 2x fixed post-divider to MMC module clocks
83fe3be4d1974f5f50c5e2039a1609f4960e8579


I allready tried to fix it with making them save against zero:

if (cmp->common.features & CCU_FEATURE_FIXED_POSTDIV && \
  cmp->fixed_post_div with)
 rate *= cmp->fixed_post_div;

But that didn't help.

Any ideas?

Regards,
Philipp

[1]: https://pastebin.com/64Fzzqvg



It took me some time, but I have now a few more infos:

Right now the code breaks at this point here [1], with this clock [2].
If we have a look now at the clock config [3], we see here a table which is
an u8 array and also a fixed_predivs struct.


The u8 array is for mapping the parents from the index in the parents
array to the actual register value you listed below.

How are you figuring out which clock is triggering this? Because that
is not even the right type of clock. The backtrace you posted shows
the error occurring in a DIV or M type clock, not the MP type you
are pointing to.

Could you add some noisy printk calls to the sunxi_ccu_probe()
function in drivers/clk/sunxi-ng/ccu_common.c so it's much clearer
which clock is failing?


Thats what I basically did to find out which clock is failing. This here 
are the changes I'm doing [1]  and thats the dirty log [2]. It fails at 
clock NR 155 which is this one [3] mentioned before.







If we have a look at the function call where it breaks [4], shouldn't the
table be a clk_div_table struct instead of an u8?


The table argument is an option. Did you go through how the sunxi-ng driver
calls this function? As mentioned above, you are looking at the wrong thing.

Thanks
ChenYu


I followed the failing call to this function (through the clock driver). 
As you can see I added an additional printk statement to see where it fails.


Regards,
Philipp




The a31s is the only board where we have this combination of a fixed_predivs
and a table.

Philipp


Related Clock source register A31s:

: OSC24MHz/750=32KHz
0001: LOSC
0010: OSC24MHz
0011: /
0100: /
0101: /
0110: /
0111: /
1000: /
1001: /
1010: /
1011: AXICLK/4
1100: /
1101: AHB1CLK/4
1110: /
: /


[1]:
http://lxr.bootlin.com/linux/v4.16-rc1/source/drivers/clk/clk-divider.c#L89

[2]:
http://lxr.bootlin.com/linux/v4.16-rc1/source/drivers/clk/sunxi-ng/ccu-sun6i-a31.c#L1137

[3]:
http://lxr.bootlin.com/linux/v4.16-rc1/source/drivers/clk/sunxi-ng/ccu-sun6i-a31.c#L749

[4]:
http://lxr.bootlin.com/linux/v4.16-rc1/source/drivers/clk/clk-divider.c#L93



[1]: https://pastebin.com/tvDunAWq
[2]: https://pastebin.com/SBn2VQLu
[3]: 
http://lxr.bootlin.com/linux/v4.16-rc1/source/include/dt-bindings/clock/sun6i-a31-ccu.h#L187


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[linux-sunxi] Re: BUG: A31s Not booting anymore

2018-02-12 Thread Philipp Rossak



On 12.02.2018 19:21, Philipp Rossak wrote:

Hey,

When I try to boot my A31s (Bananapi M2) u-boot is showing only Starting 
kernel ... . After enabling the earlyprintk I could capture this log: [1].


After reverting those 5 commits from Chen-Yu I was able to boot again:


clk: sunxi-ng: Support fixed post-dividers on NM style clocks
7d333ef1cc1b8c8951f3a2c41f6406e2295d8be9

clk: sunxi-ng: sun8i: a83t: Add /2 fixed post divider to audio PLL
10e6eb4f2c5b35ae71c9bc0db83d74238719b453

clk: sunxi-ng: sun8i: a83t: Use sigma-delta modulation for audio PLL
e952ca3c6b2ffdfbf9618e4bd3e9aad1ff3f5eb4

clk: sunxi-ng: Support fixed post-dividers on MP style clocks
946797aa3f08e2f6f5992f3ec2be44791e9b9260

clk: sunxi-ng: sun50i: a64: Add 2x fixed post-divider to MMC module clocks
83fe3be4d1974f5f50c5e2039a1609f4960e8579


I allready tried to fix it with making them save against zero:

if (cmp->common.features & CCU_FEATURE_FIXED_POSTDIV && \
     cmp->fixed_post_div with)
    rate *= cmp->fixed_post_div;

But that didn't help.

Any ideas?

Regards,
Philipp

[1]: https://pastebin.com/64Fzzqvg


It took me some time, but I have now a few more infos:

Right now the code breaks at this point here [1], with this clock [2].
If we have a look now at the clock config [3], we see here a table which 
is an u8 array and also a fixed_predivs struct.


If we have a look at the function call where it breaks [4], shouldn't 
the table be a clk_div_table struct instead of an u8?


The a31s is the only board where we have this combination of a 
fixed_predivs and a table.


Philipp


Related Clock source register A31s:

: OSC24MHz/750=32KHz
0001: LOSC
0010: OSC24MHz
0011: /
0100: /
0101: /
0110: /
0111: /
1000: /
1001: /
1010: /
1011: AXICLK/4
1100: /
1101: AHB1CLK/4
1110: /
: /


[1]: 
http://lxr.bootlin.com/linux/v4.16-rc1/source/drivers/clk/clk-divider.c#L89


[2]: 
http://lxr.bootlin.com/linux/v4.16-rc1/source/drivers/clk/sunxi-ng/ccu-sun6i-a31.c#L1137


[3]: 
http://lxr.bootlin.com/linux/v4.16-rc1/source/drivers/clk/sunxi-ng/ccu-sun6i-a31.c#L749


[4]: 
http://lxr.bootlin.com/linux/v4.16-rc1/source/drivers/clk/clk-divider.c#L93


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[linux-sunxi] BUG: A31s Not booting anymore

2018-02-12 Thread Philipp Rossak

Hey,

When I try to boot my A31s (Bananapi M2) u-boot is showing only Starting 
kernel ... . After enabling the earlyprintk I could capture this log: [1].


After reverting those 5 commits from Chen-Yu I was able to boot again:


clk: sunxi-ng: Support fixed post-dividers on NM style clocks
7d333ef1cc1b8c8951f3a2c41f6406e2295d8be9

clk: sunxi-ng: sun8i: a83t: Add /2 fixed post divider to audio PLL
10e6eb4f2c5b35ae71c9bc0db83d74238719b453

clk: sunxi-ng: sun8i: a83t: Use sigma-delta modulation for audio PLL
e952ca3c6b2ffdfbf9618e4bd3e9aad1ff3f5eb4

clk: sunxi-ng: Support fixed post-dividers on MP style clocks
946797aa3f08e2f6f5992f3ec2be44791e9b9260

clk: sunxi-ng: sun50i: a64: Add 2x fixed post-divider to MMC module clocks
83fe3be4d1974f5f50c5e2039a1609f4960e8579


I allready tried to fix it with making them save against zero:

if (cmp->common.features & CCU_FEATURE_FIXED_POSTDIV && \
cmp->fixed_post_div with)
   rate *= cmp->fixed_post_div;

But that didn't help.

Any ideas?

Regards,
Philipp

[1]: https://pastebin.com/64Fzzqvg

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[linux-sunxi] Re: [PATCH v5 0/6] IR support for A83T

2018-02-12 Thread Philipp Rossak


On 30.01.2018 18:46, Philipp Rossak wrote:

This patch series adds support for the sunxi A83T ir module and enhances
the sunxi-ir driver. Right now the base clock frequency for the ir driver
is a hard coded define and is set to 8 MHz.
This works for the most common ir receivers. On the Sinovoip Bananapi M3
the ir receiver needs, a 3 MHz base clock frequency to work without
problems with this driver.

This patch series adds support for an optinal property that makes it able
to override the default base clock frequency and enables the ir interface
on the a83t and the Bananapi M3.

changes since v4:
* rename cir pin from cir_pins to r_cir_pin
* drop unit-adress from r_cir_pin
* add a83t compatible to the cir node
* move muxing options to dtsi
* rename cir label and reorder it in the bananpim3.dts file

changes since v3:
* collecting all acks & reviewd by
* fixed typos

changes since v2:
* reorder cir pin (alphabetical)
* fix typo in documentation

changes since v1:
* fix typos, reword Documentation
* initialize 'b_clk_freq' to 'SUNXI_IR_BASE_CLK' & remove if statement
* change dev_info() to dev_dbg()
* change naming to cir* in dts/dtsi
* Added acked Ackedi-by to related patch
* use whole memory block instead of registers needed + fix for h3/h5

changes since rfc:
* The property is now optinal. If the property is not available in
   the dtb the driver uses the default base clock frequency.
* the driver prints out the the selected base clock frequency.
* changed devicetree property from base-clk-frequency to clock-frequency

Regards,
Philipp

Philipp Rossak (6):
   media: rc: update sunxi-ir driver to get base clock frequency from
 devicetree
   media: dt: bindings: Update binding documentation for sunxi IR
 controller
   arm: dts: sun8i: a83t: Add the cir pin for the A83T
   arm: dts: sun8i: a83t: Add support for the cir interface
   arm: dts: sun8i: a83t: bananapi-m3: Enable IR controller
   arm: dts: sun8i: h3-h5: ir register size should be the whole memory
 block

  Documentation/devicetree/bindings/media/sunxi-ir.txt |  3 +++
  arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts |  5 +
  arch/arm/boot/dts/sun8i-a83t.dtsi| 18 ++
  arch/arm/boot/dts/sunxi-h3-h5.dtsi   |  2 +-
  drivers/media/rc/sunxi-cir.c | 19 +++
  5 files changed, 38 insertions(+), 9 deletions(-)



Hey,

RC1 is now out, thus I would like to ask you to have a look at this 
patch series again. Some patches still miss an acked-by. It would be 
nice if we could schedule this for v4.17.


Thanks,
Philipp


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[linux-sunxi] Re: [PATCH 1/3] arm: dts: sun6i: a31s: bpi-m2: update mmc supply nodes

2018-02-11 Thread Philipp Rossak
Am Freitag, den 09.02.2018, 18:52 +0100 schrieb Philipp Rossak:
> This patch updates the vmmc-supply properties on the mmc0 and mmc2
> node to use the allready existent regulators.
> We can now remove the sunxi-common-regulators.dtsi include since we
> don't need it anymore.
> 
> Signed-off-by: Philipp Rossak <embe...@gmail.com>
> ---
>  arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts | 5 ++---
>  1 file changed, 2 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts
> b/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts
> index 51e6f1d21c32..a8d86211c8f3 100644
> --- a/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts
> +++ b/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts
> @@ -42,7 +42,6 @@
>  
>  /dts-v1/;
>  #include "sun6i-a31s.dtsi"
> -#include "sunxi-common-regulators.dtsi"
>  #include 
>  
>  / {
> @@ -118,7 +117,7 @@
>   {
>   pinctrl-names = "default";
>   pinctrl-0 = <_pins_a>, <_cd_pin_bpi_m2>;
> - vmmc-supply = <_vcc3v0>;
> + vmmc-supply = <_dcdc1>;
>   bus-width = <4>;
>   cd-gpios = < 0 4 GPIO_ACTIVE_HIGH>; /* PA4 */
>   cd-inverted;
> @@ -132,7 +131,7 @@
>   {
>   pinctrl-names = "default";
>   pinctrl-0 = <_pins_a>;
> - vmmc-supply = <_vcc3v0>;
> + vmmc-supply = <_dcdc1>;
^^
this here is wrong! this should be _aldo1
>   mmc-pwrseq = <_pwrseq>;
>   bus-width = <4>;
>   non-removable;

Philipp

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[linux-sunxi] Re: [PATCH 0/3] Fix broken bananapi m2 devicetree/regulators

2018-02-11 Thread Philipp Rossak
Am Sonntag, den 11.02.2018, 10:55 +0300 schrieb Sergey Suloev:
> On 02/11/2018 01:07 AM, Philipp Rossak wrote:
> > 
> > 
> > On 10.02.2018 22:08, Sergey Suloev wrote:
> > > On 02/11/2018 12:01 AM, Philipp Rossak wrote:
> > > > Hey Sergey,
> > > > 
> > > > Thanks for mentioning, but I think the problem has nothing to
> > > > do 
> > > > with those patches. I tested them with the v4.15.0 Kernel since
> > > > this 
> > > > is the last stable release and we are right now in the merging
> > > > window.
> > > > 
> > > > I tested the latest mainline, without those patches and the
> > > > kernel 
> > > > is not booting (I can't see any uart output).
> > > > 
> > > > Thanks,
> > > > Philipp
> > > > 
> > > > On 10.02.2018 14:56, Sergey Suloev wrote:
> > > > > On 02/09/2018 08:52 PM, Philipp Rossak wrote:
> > > > > > This patchseries fixes the bananapi m1 devicetree, to be
> > > > > > able to 
> > > > > > boot again.
> > > > > > The first two patches update/improve the devicetree and the
> > > > > > last 
> > > > > > patch adds
> > > > > > all missing regulators.
> > > > > > 
> > > > > > Regards,
> > > > > > Philipp
> > > > > > 
> > > > > > Philipp Rossak (3):
> > > > > >    arm: dts: sun6i: a31s: bpi-m2: update mmc supply nodes
> > > > > >    arm: dts: sun6i: a31s: bpi-m2: improve pmic properties
> > > > > >    arm: dts: sun6i: a31s: fix: bpi-m2: add missing
> > > > > > regulators
> > > > > > 
> > > > > >   arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts | 70 
> > > > > > +++-
> > > > > >   1 file changed, 67 insertions(+), 3 deletions(-)
> > > > > > 
> > > > > 
> > > > > patches are not working
> > > > > 
> > > > > Thanks
> > > > > 
> > > 
> > > same problem, but after applying the patches my device is till
> > > hanging.
> > > 
> > > 
> > 
> > Can you please share a bootlog? Here is mine [1]. As you can see
> > I'm 
> > able to boot.
> > I build it with this branch [2]. For testing you should replace
> > the 
> > dtb and the uImage/zImage
> > 
> > Philipp
> > 
> > 
> > [1]: https://pastebin.com/mVjv3LDf
> > [2]: 
> > https://github.com/embed-3d/linux/tree/testing/bpi-m2-regulator-tes
> > t-2
> 
> My dmesg is very similar to yours unless it hangs on the last line
> [1]. 
> For this test I used kernel from tag v4.15 with no additional
> patching.
> 
> [1] https://pastebin.com/3a6bk5Dk
> 
> 

For me it looks like you have a different kernel and also an different
dtb that you patch! And you are applying also a fixup script.
These patches should be applied on top of linux mainline. 

fixup script:
Applying kernel provided DT fixup script (sun6i-a31s-fixup.scr)


Linux versions:
4.15.0-3-g1bbe5edde691   vs   4.15.0-sunxi-dirty

In addition to that you are also booting into fb/hdmi.

If you use my branch (uImage and dtb) and replace the current boot.cmd
with this (to get the boot.scr you need to use mkimage) it should work:

setenv bootargs console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootwait
panic=10
load mmc 0:1 0x4300 ${fdtfile} || load mmc 0:1 0x4300
boot/${fdtfile}
load mmc 0:1 0x4200 uImage || load mmc 0:1 0x4200 boot/uImage
bootm 0x4200 - 0x4300

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[linux-sunxi] [BUG]: A83T - AC100 gets the wrong number of parents

2018-02-10 Thread Philipp Rossak
Hey,

When I boot my A83T I get the following bootlog [1].

After some debugging, I found out that the function call:
clk_hw_get_num_parents() returns 2. After a look in the devicetree I
found out that this value should be 1, since we only have one parent
clock [3].
Setting the variable num_parents to 1 fixes the problem, but this is no
soultion.

Regards,
Philipp



[1]: https://pastebin.com/5c7hxjsS
[2]: http://lxr.bootlin.com/linux/v4.15/source/drivers/rtc/rtc-ac100.c#
L180
[3]: http://lxr.bootlin.com/linux/v4.15/source/arch/arm/boot/dts/sun8i-
a83t-bananapi-m3.dts#L159

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[linux-sunxi] Re: [PATCH 0/3] Fix broken bananapi m2 devicetree/regulators

2018-02-10 Thread Philipp Rossak



On 10.02.2018 22:08, Sergey Suloev wrote:

On 02/11/2018 12:01 AM, Philipp Rossak wrote:

Hey Sergey,

Thanks for mentioning, but I think the problem has nothing to do with 
those patches. I tested them with the v4.15.0 Kernel since this is the 
last stable release and we are right now in the merging window.


I tested the latest mainline, without those patches and the kernel is 
not booting (I can't see any uart output).


Thanks,
Philipp

On 10.02.2018 14:56, Sergey Suloev wrote:

On 02/09/2018 08:52 PM, Philipp Rossak wrote:
This patchseries fixes the bananapi m1 devicetree, to be able to 
boot again.
The first two patches update/improve the devicetree and the last 
patch adds

all missing regulators.

Regards,
Philipp

Philipp Rossak (3):
   arm: dts: sun6i: a31s: bpi-m2: update mmc supply nodes
   arm: dts: sun6i: a31s: bpi-m2: improve pmic properties
   arm: dts: sun6i: a31s: fix: bpi-m2: add missing regulators

  arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts | 70 
+++-

  1 file changed, 67 insertions(+), 3 deletions(-)


patches are not working

Thanks


same problem, but after applying the patches my device is till hanging.


Can you please share a bootlog? Here is mine [1]. As you can see I'm 
able to boot.
I build it with this branch [2]. For testing you should replace the dtb 
and the uImage/zImage


Philipp


[1]: https://pastebin.com/mVjv3LDf
[2]: https://github.com/embed-3d/linux/tree/testing/bpi-m2-regulator-test-2

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[linux-sunxi] Re: [PATCH 0/3] Fix broken bananapi m2 devicetree/regulators

2018-02-10 Thread Philipp Rossak

Hey Sergey,

Thanks for mentioning, but I think the problem has nothing to do with 
those patches. I tested them with the v4.15.0 Kernel since this is the 
last stable release and we are right now in the merging window.


I tested the latest mainline, without those patches and the kernel is 
not booting (I can't see any uart output).


Thanks,
Philipp

On 10.02.2018 14:56, Sergey Suloev wrote:

On 02/09/2018 08:52 PM, Philipp Rossak wrote:
This patchseries fixes the bananapi m1 devicetree, to be able to boot 
again.
The first two patches update/improve the devicetree and the last patch 
adds

all missing regulators.

Regards,
Philipp

Philipp Rossak (3):
   arm: dts: sun6i: a31s: bpi-m2: update mmc supply nodes
   arm: dts: sun6i: a31s: bpi-m2: improve pmic properties
   arm: dts: sun6i: a31s: fix: bpi-m2: add missing regulators

  arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts | 70 
+++-

  1 file changed, 67 insertions(+), 3 deletions(-)


patches are not working

Thanks



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[linux-sunxi] [PATCH 1/3] arm: dts: sun6i: a31s: bpi-m2: update mmc supply nodes

2018-02-09 Thread Philipp Rossak
This patch updates the vmmc-supply properties on the mmc0 and mmc2
node to use the allready existent regulators.
We can now remove the sunxi-common-regulators.dtsi include since we
don't need it anymore.

Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
 arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts 
b/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts
index 51e6f1d21c32..a8d86211c8f3 100644
--- a/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts
+++ b/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts
@@ -42,7 +42,6 @@
 
 /dts-v1/;
 #include "sun6i-a31s.dtsi"
-#include "sunxi-common-regulators.dtsi"
 #include 
 
 / {
@@ -118,7 +117,7 @@
  {
pinctrl-names = "default";
pinctrl-0 = <_pins_a>, <_cd_pin_bpi_m2>;
-   vmmc-supply = <_vcc3v0>;
+   vmmc-supply = <_dcdc1>;
bus-width = <4>;
cd-gpios = < 0 4 GPIO_ACTIVE_HIGH>; /* PA4 */
cd-inverted;
@@ -132,7 +131,7 @@
  {
pinctrl-names = "default";
pinctrl-0 = <_pins_a>;
-   vmmc-supply = <_vcc3v0>;
+   vmmc-supply = <_dcdc1>;
mmc-pwrseq = <_pwrseq>;
bus-width = <4>;
non-removable;
-- 
2.11.0

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[linux-sunxi] [PATCH 0/3] Fix broken bananapi m2 devicetree/regulators

2018-02-09 Thread Philipp Rossak
This patchseries fixes the bananapi m1 devicetree, to be able to boot again.
The first two patches update/improve the devicetree and the last patch adds
all missing regulators.

Regards,
Philipp

Philipp Rossak (3):
  arm: dts: sun6i: a31s: bpi-m2: update mmc supply nodes
  arm: dts: sun6i: a31s: bpi-m2: improve pmic properties
  arm: dts: sun6i: a31s: fix: bpi-m2: add missing regulators

 arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts | 70 +++-
 1 file changed, 67 insertions(+), 3 deletions(-)

-- 
2.11.0

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[linux-sunxi] [PATCH 2/3] arm: dts: sun6i: a31s: bpi-m2: improve pmic properties

2018-02-09 Thread Philipp Rossak
The eldoin is supplied from the dcdc1 regulator. The N_VBUSEN pin is
connected to an external power regulator (SY6280AAC).
With this commit we update the pmic binding properties to support
those features.

Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
 arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts 
b/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts
index a8d86211c8f3..556528386858 100644
--- a/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts
+++ b/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts
@@ -162,6 +162,8 @@
reg = <0x68>;
interrupt-parent = <_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+   eldoin-supply = <_dcdc1>;
+   x-powers,drive-vbus-en;
};
 };
 
-- 
2.11.0

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[linux-sunxi] [PATCH 3/3] arm: dts: sun6i: a31s: fix: bpi-m2: add missing regulators

2018-02-09 Thread Philipp Rossak
This patch fixes a bootproblem with the Bananapi M2 board. Since there
are some regulators missing we add them right now. Those values come
from the schematic, below you can find a small overview:

* reg_aldo1:  3,3V, powers the wifi
* reg_aldo2:  2,5V, powers the IO of the RTL8211E
* reg_aldo3:  3,3V, powers the audio

* reg_dldo1:  3,0V, powers the RTL8211E
* reg_dldo2:  2,8V, powers the analog part of the csi
* reg_dldo3:  3,3V, powers misc
* reg_eldo1:  1,8V, powers the csi
* reg_ldo_io1:1,8V, powers the gpio

* reg_dc5ldo: needs to be always on

Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
 arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts | 56 
 1 file changed, 56 insertions(+)

diff --git a/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts 
b/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts
index 51e6f1d21c32..01fcfe0649ad 100644
--- a/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts
+++ b/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts
@@ -99,6 +99,7 @@
pinctrl-0 = <_pins_rgmii_a>, <_phy_reset_pin_bpi_m2>;
phy = <>;
phy-mode = "rgmii";
+   phy-supply = <_dldo1>;
snps,reset-gpio = < 0 21 GPIO_ACTIVE_HIGH>; /* PA21 */
snps,reset-active-low;
snps,reset-delays-us = <0 1 3>;
@@ -193,7 +194,28 @@
 
 #include "axp22x.dtsi"
 
+_aldo1 {
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   regulator-name = "vcc-wifi";
+};
+
+_aldo2 {
+   regulator-always-on;
+   regulator-min-microvolt = <250>;
+   regulator-max-microvolt = <250>;
+   regulator-name = "vcc-gmac";
+};
+
+_aldo3 {
+   regulator-always-on;
+   regulator-min-microvolt = <300>;
+   regulator-max-microvolt = <300>;
+   regulator-name = "avcc";
+};
+
 _dc5ldo {
+   regulator-always-on;
regulator-min-microvolt = <70>;
regulator-max-microvolt = <132>;
regulator-name = "vdd-cpus";
@@ -233,6 +255,40 @@
regulator-name = "vcc-dram";
 };
 
+_dldo1 {
+   regulator-min-microvolt = <300>;
+   regulator-max-microvolt = <300>;
+   regulator-name = "vcc-mac";
+};
+
+_dldo2 {
+   regulator-min-microvolt = <280>;
+   regulator-max-microvolt = <280>;
+   regulator-name = "avdd-csi";
+};
+
+_dldo3 {
+   regulator-always-on;
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   regulator-name = "vcc-pb";
+};
+
+_eldo1 {
+   regulator-min-microvolt = <180>;
+   regulator-max-microvolt = <180>;
+   regulator-name = "vdd-csi";
+   status = "okay";
+};
+
+_ldo_io1 {
+   regulator-always-on;
+   regulator-min-microvolt = <180>;
+   regulator-max-microvolt = <180>;
+   regulator-name = "vcc-pm-cpus";
+   status = "okay";
+};
+
  {
pinctrl-names = "default";
pinctrl-0 = <_pins_a>;
-- 
2.11.0

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[linux-sunxi] Re: [PATCH v2 07/16] iio: adc: sun4i-gpadc-iio: rework: support nvmem calibration data

2018-02-02 Thread Philipp Rossak





/* prevents concurrent reads of temperature and ADC */
struct mutexmutex;
struct thermal_zone_device  *tzd;
@@ -561,6 +569,9 @@ static int sun4i_gpadc_probe_dt(struct platform_device 
*pdev,
struct resource *mem;
void __iomem *base;
int ret;
+   struct nvmem_cell *cell;
+   ssize_t cell_size;
+   u64 *cell_data;
info->data = of_device_get_match_data(>dev);
if (!info->data)
@@ -575,6 +586,39 @@ static int sun4i_gpadc_probe_dt(struct platform_device 
*pdev,
if (IS_ERR(base))
return PTR_ERR(base);
+   info->has_calibration_data[0] = false;
+   info->has_calibration_data[1] = false;
+
+   if (!info->data->supports_nvmem)
+   goto no_nvmem;
+
+   cell = nvmem_cell_get(>dev, "calibration");
+   if (IS_ERR(cell)) {
+   if (PTR_ERR(cell) == -EPROBE_DEFER)
+   return PTR_ERR(cell);
+   goto no_nvmem;


goto considered evil ? :)


this was a suggestion from Jonatan in version one, to make the code better
readable.


Isn't

if (info->data->supports_nvmem && IS_ERR(cell = nvmem_cell_get()))

pretty much the same thing?

Maxime


I would say :

if (info->data->supports_nvmem && !IS_ERR(cell = nvmem_cell_get())) is

the same.
This would require an else if statement like this:

else if (info->data->supports_nvmem && PTR_ERR(cell) == -EPROBE_DEFER)
return PTR_ERR(cell);

to avoid errors if the thermal sensor is probed before the sid driver.

Philipp

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[linux-sunxi] Re: [PATCH v2 09/16] iio: adc: sun4i-gpadc-iio: add support for H3 thermal sensor

2018-02-02 Thread Philipp Rossak



On 31.01.2018 20:23, Quentin Schulz wrote:

Hi Philipp,

On Mon, Jan 29, 2018 at 12:29:12AM +0100, Philipp Rossak wrote:

This patch adds support for the H3 ths sensor.

The H3 supports interrupts. The interrupt is configured to update the
the sensor values every second. The calibration data is writen at the
begin of the init process.

Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
  drivers/iio/adc/sun4i-gpadc-iio.c | 86 +++
  include/linux/mfd/sun4i-gpadc.h   | 22 ++
  2 files changed, 108 insertions(+)

diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c 
b/drivers/iio/adc/sun4i-gpadc-iio.c
index b7b5451226b0..8196203d65fe 100644
--- a/drivers/iio/adc/sun4i-gpadc-iio.c
+++ b/drivers/iio/adc/sun4i-gpadc-iio.c
@@ -61,6 +61,9 @@ struct sun4i_gpadc_iio;
  static int sun4i_gpadc_sample_start(struct sun4i_gpadc_iio *info);
  static int sun4i_gpadc_sample_end(struct sun4i_gpadc_iio *info);
  
+static int sunxi_ths_sample_start(struct sun4i_gpadc_iio *info);

+static int sunxi_ths_sample_end(struct sun4i_gpadc_iio *info);
+


We try to avoid using the generic sunxi prefix.


  struct gpadc_data {
int temp_offset;
int temp_scale;
@@ -71,6 +74,10 @@ struct gpadc_data {
unsigned inttemp_data[MAX_SENSOR_COUNT];
int (*sample_start)(struct sun4i_gpadc_iio *info);
int (*sample_end)(struct sun4i_gpadc_iio *info);
+   u32 ctrl0_map;
+   u32 ctrl2_map;
+   u32 sensor_en_map;
+   u32 filter_map;
u32 irq_clear_map;
u32 irq_control_map;
boolhas_bus_clk;
@@ -138,6 +145,31 @@ static const struct gpadc_data sun8i_a33_gpadc_data = {
.support_irq = false,
  };
  
+static const struct gpadc_data sun8i_h3_ths_data = {

+   .temp_offset = -1791,
+   .temp_scale = -121,
+   .temp_data = {SUN8I_H3_THS_TDATA0, 0, 0, 0},
+   .sample_start = sunxi_ths_sample_start,
+   .sample_end = sunxi_ths_sample_end,
+   .has_bus_clk = true,
+   .has_bus_rst = true,
+   .has_mod_clk = true,
+   .sensor_count = 1,
+   .supports_nvmem = true,
+   .support_irq = true,
+   .ctrl0_map = SUN4I_GPADC_CTRL0_T_ACQ(0xff),
+   .ctrl2_map = SUN8I_H3_THS_ACQ1(0x3f),
+   .sensor_en_map = SUN8I_H3_THS_TEMP_SENSE_EN0,
+   .filter_map = SUN4I_GPADC_CTRL3_FILTER_EN |
+   SUN4I_GPADC_CTRL3_FILTER_TYPE(0x2),
+   .irq_clear_map = SUN8I_H3_THS_INTS_ALARM_INT_0 |
+   SUN8I_H3_THS_INTS_SHUT_INT_0   |
+   SUN8I_H3_THS_INTS_TDATA_IRQ_0  |
+   SUN8I_H3_THS_INTS_ALARM_OFF_0,
+   .irq_control_map = SUN8I_H3_THS_INTC_TDATA_IRQ_EN0 |
+   SUN8I_H3_THS_TEMP_PERIOD(0x7),


 From what I've understood, ACQ regs are basically clock dividers. We
should make a better job at explaining it :)



I agree, I will add this in the next version in the commit message.


+};
+
  struct sun4i_gpadc_iio {
struct iio_dev  *indio_dev;
struct completion   completion;
@@ -462,6 +494,16 @@ static int sun4i_gpadc_sample_end(struct sun4i_gpadc_iio 
*info)
return 0;
  }
  
+static int sunxi_ths_sample_end(struct sun4i_gpadc_iio *info)

+{
+   /* Disable ths interrupt */
+   regmap_write(info->regmap, SUN8I_H3_THS_INTC, 0x0);
+   /* Disable temperature sensor */
+   regmap_write(info->regmap, SUN8I_H3_THS_CTRL2, 0x0);
+
+   return 0;
+}
+
  static int sun4i_gpadc_runtime_suspend(struct device *dev)
  {
struct sun4i_gpadc_iio *info = iio_priv(dev_get_drvdata(dev));
@@ -473,6 +515,17 @@ static int sun4i_gpadc_runtime_suspend(struct device *dev)
return info->data->sample_end(info);
  }
  
+static void sunxi_calibrate(struct sun4i_gpadc_iio *info)

+{
+   if (info->has_calibration_data[0])
+   regmap_write(info->regmap, SUNXI_THS_CDATA_0_1,
+   info->calibration_data[0]);
+
+   if (info->has_calibration_data[1])
+   regmap_write(info->regmap, SUNXI_THS_CDATA_2_3,
+   info->calibration_data[1]);
+}
+
  static int sun4i_gpadc_sample_start(struct sun4i_gpadc_iio *info)
  {
/* clkin = 6MHz */
@@ -492,6 +545,35 @@ static int sun4i_gpadc_sample_start(struct sun4i_gpadc_iio 
*info)
return 0;
  }
  
+static int sunxi_ths_sample_start(struct sun4i_gpadc_iio *info)

+{
+   u32 value;
+   sunxi_calibrate(info);
+
+   if (info->data->ctrl0_map)
+   regmap_write(info->regmap, SUN8I_H3_THS_CTRL0,
+   info->data->ctrl0_map);
+
+   regmap_write(info->regmap, SUN8I_H3_THS_CTRL2,
+   info->data->ctrl2_map);
+
+   regmap_write(info->regmap, SUN8I_H3_THS_STAT,
+   info->data->irq

[linux-sunxi] Re: [PATCH v2 08/16] iio: adc: sun4i-gpadc-iio: rework: add interrupt support

2018-02-02 Thread Philipp Rossak



On 31.01.2018 20:07, Quentin Schulz wrote:

Hi Philipp,

On Mon, Jan 29, 2018 at 12:29:11AM +0100, Philipp Rossak wrote:

This patch rewors the driver to support interrupts for the thermal part
of the sensor.

This is only available for the newer sensor (currently H3 and A83T).
The interrupt will be trigerd on data available and triggers the update
for the thermal sensors. All newer sensors have different amount of
sensors and different interrupts for each device the reset of the
interrupts need to be done different

For the newer sensors is the autosuspend disabled.

Signed-off-by: Philipp Rossak <embe...@gmail.com>
Acked-by: Jonathan  Cameron <jonathan.came...@huawei.com>
---
  drivers/iio/adc/sun4i-gpadc-iio.c | 60 +++
  include/linux/mfd/sun4i-gpadc.h   |  2 ++
  2 files changed, 56 insertions(+), 6 deletions(-)

diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c 
b/drivers/iio/adc/sun4i-gpadc-iio.c
index 74eeb5cd5218..b7b5451226b0 100644
--- a/drivers/iio/adc/sun4i-gpadc-iio.c
+++ b/drivers/iio/adc/sun4i-gpadc-iio.c
@@ -71,11 +71,14 @@ struct gpadc_data {
unsigned inttemp_data[MAX_SENSOR_COUNT];
int (*sample_start)(struct sun4i_gpadc_iio *info);
int (*sample_end)(struct sun4i_gpadc_iio *info);
+   u32 irq_clear_map;
+   u32 irq_control_map;


I would say to use a regmap_irq_chip for controlling IRQs.


Sounds good for me! I will rework that in the next version.

boolhas_bus_clk;
boolhas_bus_rst;
boolhas_mod_clk;
int sensor_count;
boolsupports_nvmem;
+   boolsupport_irq;
  };
  
  static const struct gpadc_data sun4i_gpadc_data = {

@@ -90,6 +93,7 @@ static const struct gpadc_data sun4i_gpadc_data = {
.sample_end = sun4i_gpadc_sample_end,
.sensor_count = 1,
.supports_nvmem = false,
+   .support_irq = false,


False is the default, no need to set support_irq.

[...]


  struct sun4i_gpadc_iio {
@@ -332,6 +339,11 @@ static int sun4i_gpadc_temp_read(struct iio_dev 
*indio_dev, int *val,
return 0;
}
  
+	if (info->data->support_irq) {

+   regmap_read(info->regmap, info->data->temp_data[sensor], val);
+   return 0;
+   }
+


Maybe you could define a new thermal_zone_of_device_ops for these new
thermal sensors? That way, you don't even need the boolean support_irq.


Sounds good for me! I will rework that in the next version.


return sun4i_gpadc_read(indio_dev, 0, val, info->temp_data_irq);
  }
  
@@ -429,6 +441,17 @@ static irqreturn_t sun4i_gpadc_fifo_data_irq_handler(int irq, void *dev_id)

return IRQ_HANDLED;
  }
  
+static irqreturn_t sunxi_irq_thread(int irq, void *data)


I think we're trying to avoid sunxi mentions but rather using the name
of the first IP (in term of product release, not support) using this
function.


+{
+   struct sun4i_gpadc_iio *info = data;
+
+   regmap_write(info->regmap, SUN8I_H3_THS_STAT, 
info->data->irq_clear_map);
+


Will be handled by regmap_irq_chip.
[...]

-   info->no_irq = true;
+   if (info->data->support_irq) {
+   /* only the new versions of ths support right now irqs */
+   irq = platform_get_irq(pdev, 0);
+   if (irq < 0) {
+   dev_err(>dev, "failed to get IRQ: %d\n", irq);
+   return irq;
+   }
+
+   ret = devm_request_threaded_irq(>dev, irq, NULL,
+   sunxi_irq_thread, IRQF_ONESHOT,
+   dev_name(>dev), info);
+   if (ret)
+   return ret;
+
+   } else
+   info->no_irq = true;
+


That's a bit funny to have two booleans named no_irq and support_irq :)

I know this looks very funny. I thought this would be better to keep, to 
_not_ break anything. Since I will rework the whole driver and integrate 
the mfd part I hope I can remove both.



indio_dev->num_channels = ARRAY_SIZE(sun8i_a33_gpadc_channels);
indio_dev->channels = sun8i_a33_gpadc_channels;
  
@@ -789,11 +829,13 @@ static int sun4i_gpadc_probe(struct platform_device *pdev)

if (ret)
return ret;
  
-	pm_runtime_set_autosuspend_delay(>dev,

-SUN4I_GPADC_AUTOSUSPEND_DELAY);
-   pm_runtime_use_autosuspend(>dev);
-   pm_runtime_set_suspended(>dev);
-   pm_runtime_enable(>dev);
+   if (!info->data->support_irq) {
+   pm_runtime_set_autosuspend_delay(>dev,
+SUN4I_GPADC_AUTOSUSPEND_DELAY);
+   pm_runtime_use_autosuspend(>dev);
+   pm_runtime_set_suspended(>dev);
+   pm_run

[linux-sunxi] Re: [PATCH v2 06/16] iio: adc: sun4i-gpadc-iio: rework: support multiple sensors

2018-02-02 Thread Philipp Rossak



On 31.01.2018 19:42, Quentin Schulz wrote:

Hi Philipp,

On Mon, Jan 29, 2018 at 12:29:09AM +0100, Philipp Rossak wrote:

For adding newer sensor some basic rework of the code is necessary.

This patch reworks the driver to be able to handle more than one
thermal sensor. Newer SoC like the A80 have 4 thermal sensors.
Because of this the maximal sensor count value was set to 4.

The sensor_id value is set during sensor registration and is for each
registered sensor indiviual. This makes it able to differntiate the
sensors when the value is read from the register.

In function sun4i_gpadc_read_raw(), the sensor number of the ths sensor
was directly set to 0 (sun4i_gpadc_temp_read(x,x,0)). This selects
in the temp_read function automatically sensor 0. A check for the
sensor_id is here not required since the old sensors only have one
thermal sensor. In addition to that is the sun4i_gpadc_read_raw()
function only used by the "older" sensors (before A33) where the
thermal sensor was a cobination of an adc and a thermal sensor.

Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
  drivers/iio/adc/sun4i-gpadc-iio.c | 36 +++-
  include/linux/mfd/sun4i-gpadc.h   |  3 +++
  2 files changed, 26 insertions(+), 13 deletions(-)

diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c 
b/drivers/iio/adc/sun4i-gpadc-iio.c
index 51ec0104d678..ac9ad2f8232f 100644
--- a/drivers/iio/adc/sun4i-gpadc-iio.c
+++ b/drivers/iio/adc/sun4i-gpadc-iio.c
@@ -67,12 +67,13 @@ struct gpadc_data {
unsigned inttp_adc_select;
unsigned int(*adc_chan_select)(unsigned int chan);
unsigned intadc_chan_mask;
-   unsigned inttemp_data;
+   unsigned inttemp_data[MAX_SENSOR_COUNT];
int (*sample_start)(struct sun4i_gpadc_iio *info);
int (*sample_end)(struct sun4i_gpadc_iio *info);
boolhas_bus_clk;
boolhas_bus_rst;
boolhas_mod_clk;
+   int sensor_count;
  };
  


I've noticed that for H3, A83T, A64 (at least), if DATA reg of sensor 0
is e.g. 0x80, DATA reg of sensor N is at 0x80 + 0x04 * N.

Is that verified for other SoCs? Does anyone have some input on this?

We could then just use temp_data as the DATA reg "base" and increment by
0x4 depending on the sensor id instead of using a fixed-size array.



This sounds like a good idea! I will add this to the next version.

I can verify this with a table, I created during development. I will 
upload it during the weekend here: [1]




  static const struct gpadc_data sun4i_gpadc_data = {
@@ -82,9 +83,10 @@ static const struct gpadc_data sun4i_gpadc_data = {
.tp_adc_select = SUN4I_GPADC_CTRL1_TP_ADC_SELECT,
.adc_chan_select = _gpadc_chan_select,
.adc_chan_mask = SUN4I_GPADC_CTRL1_ADC_CHAN_MASK,
-   .temp_data = SUN4I_GPADC_TEMP_DATA,
+   .temp_data = {SUN4I_GPADC_TEMP_DATA, 0, 0, 0},
.sample_start = sun4i_gpadc_sample_start,
.sample_end = sun4i_gpadc_sample_end,
+   .sensor_count = 1,


If the solution above is not desirable/possible, could we use something
like:

unsigned int sun4i_temp_data[] = {SUN4I_GPADC_TEMP_DATA,};

static const struct gpadc_data sun4i_gpadc_data = {
.temp_data = _temp_data,
.sensor_count = ARRAY_SIZE(sun4i_temp_data),
};

That avoids 1) inconsistencies between the array size and the array
itself, 2) does not require to pad the array with zeroes.

[...]


@@ -745,9 +752,12 @@ static int sun4i_gpadc_probe(struct platform_device *pdev)
pm_runtime_enable(>dev);
  
  	if (IS_ENABLED(CONFIG_THERMAL_OF)) {

-   info->tzd = thermal_zone_of_sensor_register(info->sensor_device,
-   0, info,
-   _ts_tz_ops);
+   for (i = 0; i < info->data->sensor_count; i++) {
+   info->sensor_id = i;
+   info->tzd = thermal_zone_of_sensor_register(
+   info->sensor_device,
+   i, info, _ts_tz_ops);
+   }


As Maxime said, this does not work.

One way would be to have a new structure being:
struct sun4i_sensor_info {
struct sun4i_gpadc_iio  *info;
unsigned intsensor_id;
};

Or since we only use the iio_dev within the sun4i_gpadc_iio in the
.get_temp function, we may replace info by struct iio_dev *indio_dev
above.

Quentin

I will have a closer look on this next week, when I start to work on the 
next version..


Thanks,
Philipp

[1]: http://linux-sunxi.org/Thermal_Sensor

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[linux-sunxi] Re: [PATCH v2 04/16] iio: adc: sun4i-gpadc-iio: rework: sampling start/end code readout reg

2018-01-31 Thread Philipp Rossak



On 31.01.2018 18:51, Quentin Schulz wrote:

Hi Philipp,

On Mon, Jan 29, 2018 at 12:29:07AM +0100, Philipp Rossak wrote:

For adding newer sensor some basic rework of the code is necessary.

This commit reworks the code and allows the sampling start/end code and
the position of value readout register to be altered. Later the start/end
functions will be used to configure the ths and start/stop the
sampling.

Signed-off-by: Icenowy Zheng <icen...@aosc.io>
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
  drivers/iio/adc/sun4i-gpadc-iio.c | 44 ++-
  1 file changed, 39 insertions(+), 5 deletions(-)

diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c 
b/drivers/iio/adc/sun4i-gpadc-iio.c
index 03804ff9c006..db57d9fffe48 100644
--- a/drivers/iio/adc/sun4i-gpadc-iio.c
+++ b/drivers/iio/adc/sun4i-gpadc-iio.c
@@ -49,6 +49,15 @@ static unsigned int sun6i_gpadc_chan_select(unsigned int 
chan)
return SUN6I_GPADC_CTRL1_ADC_CHAN_SELECT(chan);
  }
  
+struct sun4i_gpadc_iio;

+
+/*
+ * Prototypes for these functions, which enable these functions to be
+ * referenced in gpadc_data structures.
+ */


Comment not needed.


+static int sun4i_gpadc_sample_start(struct sun4i_gpadc_iio *info);
+static int sun4i_gpadc_sample_end(struct sun4i_gpadc_iio *info);
+
  struct gpadc_data {
int temp_offset;
int temp_scale;
@@ -56,6 +65,9 @@ struct gpadc_data {
unsigned inttp_adc_select;
unsigned int(*adc_chan_select)(unsigned int chan);
unsigned intadc_chan_mask;
+   unsigned inttemp_data;


Does not really have anything to do with sample_start/end. I would have
made a different commit for it.

Otherwise,
Reviewed-by: Quentin Schulz <quentin.sch...@free-electrons.com>

Quentin



Ok I will split this.

Thanks,
Philipp

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[linux-sunxi] Re: [PATCH v2 01/16] dt-bindings: update the Allwinner GPADC device tree binding for H3 & A83T

2018-01-31 Thread Philipp Rossak



On 31.01.2018 18:40, Quentin Schulz wrote:

Hi Philipp,

On Mon, Jan 29, 2018 at 12:29:04AM +0100, Philipp Rossak wrote:

Allwinner H3 features a thermal sensor like the one in A33, but has its
register re-arranged, the clock divider moved to CCU (originally the
clock divider is in ADC) and added a pair of bus clock and reset.

Allwinner A83T features a thermal sensor similar to the H3, the ths clock,
the bus clock and the reset was removed from the CCU. The THS in A83T
has a clock that is directly connected and runs with 24 MHz.

Update the binding document to cover H3 and A83T.

Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
  .../devicetree/bindings/mfd/sun4i-gpadc.txt| 50 --
  1 file changed, 47 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt 
b/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt
index 86dd8191b04c..22df0c5c23d4 100644
--- a/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt
+++ b/Documentation/devicetree/bindings/mfd/sun4i-gpadc.txt
@@ -4,12 +4,35 @@ The Allwinner SoCs all have an ADC that can also act as a 
thermal sensor
  and sometimes as a touchscreen controller.
  
  Required properties:

-  - compatible: "allwinner,sun8i-a33-ths",
+  - compatible: must contain one of the following compatibles:
+   - "allwinner,sun8i-a33-ths"
+   - "allwinner,sun8i-h3-ths"
+   - "allwinner,sun8i-a83t-ths"
- reg: mmio address range of the chip,
-  - #thermal-sensor-cells: shall be 0,
+  - #thermal-sensor-cells: shall be 0 or 1,


Well, thermal-sensor-cells is either 0 or 1 :)

Better to point to the documentation describing this
thermal-sensor-cells IMHO.



I agree, I will change this in the next version.


- #io-channel-cells: shall be 0,
  
-Example:

+Required properties for the following compatibles:
+   - "allwinner,sun8i-h3-ths"
+   - "allwinner,sun8i-a83t-ths"
+  - interrupts: the sampling interrupt of the ADC,
+
+Required properties for the following compatibles:
+   - "allwinner,sun8i-h3-ths"
+  - clocks: the bus clock and the input clock of the ADC,
+  - clock-names: should be "bus" and "mod",
+  - resets: the bus reset of the ADC,
+
+Optional properties for the following compatibles:
+   - "allwinner,sun8i-h3-ths"
+  - nvmem-cells: A phandle to the calibration data provided by a nvmem device.
+   If unspecified default values shall be used. The size should
+   be 0x2 * sensorcount.


"twice the number of sensors" ?



As already mentioned in an other answers, this here is not correct.
I got somehow a wrong information or mixed something up. For H5, H3, 
A83T and A64 the thermal sensor calibration data is always 64 bit wide 
and placed on the eFuse address  0x34 [1].



+  - nvmem-cell-names: Should be "calibration".
+
+Details see: bindings/nvmem/nvmem.txt
+
+Example for A33:
ths: ths@1c25000 {
compatible = "allwinner,sun8i-a33-ths";
reg = <0x01c25000 0x100>;
@@ -17,6 +40,27 @@ Example:
#io-channel-cells = <0>;
};
  
+Example for H3:

+   ths: thermal-sensor@1c25000 {
+   compatible = "allwinner,sun8i-h3-ths";
+   reg = <0x01c25000 0x400>;
+   clocks = < CLK_BUS_THS>, < CLK_THS>;
+   clock-names = "bus", "mod";
+   resets = < RST_BUS_THS>;
+   interrupts = ;
+   #thermal-sensor-cells = <0>;
+   #io-channel-cells = <0>;
+   };
+
+Example for A83T:
+   ths: thermal-sensor@1f04000 {
+   compatible = "allwinner,sun8i-a83t-ths";
+   reg = <0x01f04000 0x100>;
+   interrupts = ;
+   #thermal-sensor-cells = <1>;
+   #io-channel-cells = <0>;
+   };
+


Aside from Maxime's comment on how we would like to refactor GPADC/THS,
I'm not sure we really want an example for each an every thermal sensor
supported.

Quentin

I agree we don't want to have an example for every sensor, but I think 
at least those two are interesting, since one has 3 sensors and no 
clocks, and one has 1 sensor and clocks.


Thanks,
Philipp

[1]: http://linux-sunxi.org/SID_Register_Guide#eFUSE

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[linux-sunxi] [PATCH v5 1/6] media: rc: update sunxi-ir driver to get base clock frequency from devicetree

2018-01-30 Thread Philipp Rossak
This patch updates the sunxi-ir driver to set the base clock frequency from
devicetree.

This is necessary since there are different ir receivers on the
market, that operate with different frequencies. So this value could be
set if the attached ir receiver needs a different base clock frequency,
than the default 8 MHz.

Signed-off-by: Philipp Rossak <embe...@gmail.com>
Reviewed-by: Andi Shyti <andi.sh...@samsung.com>
Acked-by: Sean Young <s...@mess.org>
---
 drivers/media/rc/sunxi-cir.c | 19 +++
 1 file changed, 11 insertions(+), 8 deletions(-)

diff --git a/drivers/media/rc/sunxi-cir.c b/drivers/media/rc/sunxi-cir.c
index 97f367b446c4..f500cea228a9 100644
--- a/drivers/media/rc/sunxi-cir.c
+++ b/drivers/media/rc/sunxi-cir.c
@@ -72,12 +72,8 @@
 /* CIR_REG register idle threshold */
 #define REG_CIR_ITHR(val)(((val) << 8) & (GENMASK(15, 8)))
 
-/* Required frequency for IR0 or IR1 clock in CIR mode */
+/* Required frequency for IR0 or IR1 clock in CIR mode (default) */
 #define SUNXI_IR_BASE_CLK 800
-/* Frequency after IR internal divider  */
-#define SUNXI_IR_CLK  (SUNXI_IR_BASE_CLK / 64)
-/* Sample period in ns */
-#define SUNXI_IR_SAMPLE   (10ul / SUNXI_IR_CLK)
 /* Noise threshold in samples  */
 #define SUNXI_IR_RXNOISE  1
 /* Idle Threshold in samples */
@@ -122,7 +118,8 @@ static irqreturn_t sunxi_ir_irq(int irqno, void *dev_id)
/* for each bit in fifo */
dt = readb(ir->base + SUNXI_IR_RXFIFO_REG);
rawir.pulse = (dt & 0x80) != 0;
-   rawir.duration = ((dt & 0x7f) + 1) * SUNXI_IR_SAMPLE;
+   rawir.duration = ((dt & 0x7f) + 1) *
+ir->rc->rx_resolution;
ir_raw_event_store_with_filter(ir->rc, );
}
}
@@ -148,6 +145,7 @@ static int sunxi_ir_probe(struct platform_device *pdev)
struct device_node *dn = dev->of_node;
struct resource *res;
struct sunxi_ir *ir;
+   u32 b_clk_freq = SUNXI_IR_BASE_CLK;
 
ir = devm_kzalloc(dev, sizeof(struct sunxi_ir), GFP_KERNEL);
if (!ir)
@@ -172,6 +170,9 @@ static int sunxi_ir_probe(struct platform_device *pdev)
return PTR_ERR(ir->clk);
}
 
+   /* Base clock frequency (optional) */
+   of_property_read_u32(dn, "clock-frequency", _clk_freq);
+
/* Reset (optional) */
ir->rst = devm_reset_control_get_optional_exclusive(dev, NULL);
if (IS_ERR(ir->rst))
@@ -180,11 +181,12 @@ static int sunxi_ir_probe(struct platform_device *pdev)
if (ret)
return ret;
 
-   ret = clk_set_rate(ir->clk, SUNXI_IR_BASE_CLK);
+   ret = clk_set_rate(ir->clk, b_clk_freq);
if (ret) {
dev_err(dev, "set ir base clock failed!\n");
goto exit_reset_assert;
}
+   dev_dbg(dev, "set base clock frequency to %d Hz.\n", b_clk_freq);
 
if (clk_prepare_enable(ir->apb_clk)) {
dev_err(dev, "try to enable apb_ir_clk failed\n");
@@ -225,7 +227,8 @@ static int sunxi_ir_probe(struct platform_device *pdev)
ir->rc->map_name = ir->map_name ?: RC_MAP_EMPTY;
ir->rc->dev.parent = dev;
ir->rc->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;
-   ir->rc->rx_resolution = SUNXI_IR_SAMPLE;
+   /* Frequency after IR internal divider with sample period in ns */
+   ir->rc->rx_resolution = (10ul / (b_clk_freq / 64));
ir->rc->timeout = MS_TO_NS(SUNXI_IR_TIMEOUT);
ir->rc->driver_name = SUNXI_IR_DEV;
 
-- 
2.11.0

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[linux-sunxi] [PATCH v5 0/6] IR support for A83T

2018-01-30 Thread Philipp Rossak
This patch series adds support for the sunxi A83T ir module and enhances 
the sunxi-ir driver. Right now the base clock frequency for the ir driver
is a hard coded define and is set to 8 MHz.
This works for the most common ir receivers. On the Sinovoip Bananapi M3 
the ir receiver needs, a 3 MHz base clock frequency to work without
problems with this driver.

This patch series adds support for an optinal property that makes it able
to override the default base clock frequency and enables the ir interface 
on the a83t and the Bananapi M3.

changes since v4:
* rename cir pin from cir_pins to r_cir_pin
* drop unit-adress from r_cir_pin
* add a83t compatible to the cir node
* move muxing options to dtsi
* rename cir label and reorder it in the bananpim3.dts file

changes since v3:
* collecting all acks & reviewd by
* fixed typos

changes since v2:
* reorder cir pin (alphabetical)
* fix typo in documentation

changes since v1:
* fix typos, reword Documentation
* initialize 'b_clk_freq' to 'SUNXI_IR_BASE_CLK' & remove if statement
* change dev_info() to dev_dbg()
* change naming to cir* in dts/dtsi
* Added acked Ackedi-by to related patch
* use whole memory block instead of registers needed + fix for h3/h5

changes since rfc:
* The property is now optinal. If the property is not available in 
  the dtb the driver uses the default base clock frequency.
* the driver prints out the the selected base clock frequency.
* changed devicetree property from base-clk-frequency to clock-frequency

Regards,
Philipp

Philipp Rossak (6):
  media: rc: update sunxi-ir driver to get base clock frequency from
devicetree
  media: dt: bindings: Update binding documentation for sunxi IR
controller
  arm: dts: sun8i: a83t: Add the cir pin for the A83T
  arm: dts: sun8i: a83t: Add support for the cir interface
  arm: dts: sun8i: a83t: bananapi-m3: Enable IR controller
  arm: dts: sun8i: h3-h5: ir register size should be the whole memory
block

 Documentation/devicetree/bindings/media/sunxi-ir.txt |  3 +++
 arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts |  5 +
 arch/arm/boot/dts/sun8i-a83t.dtsi| 18 ++
 arch/arm/boot/dts/sunxi-h3-h5.dtsi   |  2 +-
 drivers/media/rc/sunxi-cir.c | 19 +++
 5 files changed, 38 insertions(+), 9 deletions(-)

-- 
2.11.0

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[linux-sunxi] [PATCH v5 3/6] arm: dts: sun8i: a83t: Add the cir pin for the A83T

2018-01-30 Thread Philipp Rossak
The CIR Pin of the A83T is located at PL12.

Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 7f4955a5fab7..f7f78a27e21d 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -716,6 +716,11 @@
interrupt-controller;
#interrupt-cells = <3>;
 
+   r_cir_pin: r-cir-pin {
+   pins = "PL12";
+   function = "s_cir_rx";
+   };
+
r_rsb_pins: r-rsb-pins {
pins = "PL0", "PL1";
function = "s_rsb";
-- 
2.11.0

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[linux-sunxi] [PATCH v5 4/6] arm: dts: sun8i: a83t: Add support for the cir interface

2018-01-30 Thread Philipp Rossak
The cir interface is like on the H3 located at 0x01f02000 and is exactly
the same. This patch adds support for the ir interface on the A83T.

Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 13 +
 1 file changed, 13 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index f7f78a27e21d..1e04a5cfd32d 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -704,6 +704,19 @@
#reset-cells = <1>;
};
 
+   r_cir: ir@1f02000 {
+   compatible = "allwinner,sun8i-a83t-ir",
+"allwinner,sun5i-a13-ir";
+   clocks = <_ccu CLK_APB0_IR>, <_ccu CLK_IR>;
+   clock-names = "apb", "ir";
+   resets = <_ccu RST_APB0_IR>;
+   interrupts = ;
+   reg = <0x01f02000 0x400>;
+   pinctrl-names = "default";
+   pinctrl-0 = <_cir_pin>;
+   status = "disabled";
+   };
+
r_pio: pinctrl@1f02c00 {
compatible = "allwinner,sun8i-a83t-r-pinctrl";
reg = <0x01f02c00 0x400>;
-- 
2.11.0

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[linux-sunxi] [PATCH v5 5/6] arm: dts: sun8i: a83t: bananapi-m3: Enable IR controller

2018-01-30 Thread Philipp Rossak
The Bananapi M3 has an onboard IR receiver.
This enables the onboard IR receiver subnode.
Unlike the other IR receivers this one needs a base clock frequency
of 300 Hz (3 MHz), to be able to work.

Signed-off-by: Philipp Rossak <embe...@gmail.com>
Acked-by: Chen-Yu Tsai <w...@csie.org>
---
 arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts 
b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
index 6550bf0e594b..26c015fd4f4d 100644
--- a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
@@ -145,6 +145,11 @@
status = "okay";
 };
 
+_cir {
+   clock-frequency = <300>;
+   status = "okay";
+};
+
 _rsb {
status = "okay";
 
-- 
2.11.0

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[linux-sunxi] [PATCH v5 6/6] arm: dts: sun8i: h3-h5: ir register size should be the whole memory block

2018-01-30 Thread Philipp Rossak
The size of the register should be the size of the whole memory block,
not just the registers, that are needed.

Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
 arch/arm/boot/dts/sunxi-h3-h5.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi 
b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index 7a83b15225c7..22f6e126b8df 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -712,7 +712,7 @@
clock-names = "apb", "ir";
resets = <_ccu RST_APB0_IR>;
interrupts = ;
-   reg = <0x01f02000 0x40>;
+   reg = <0x01f02000 0x400>;
status = "disabled";
};
 
-- 
2.11.0

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[linux-sunxi] [PATCH v4 3/6] arm: dts: sun8i: a83t: Add the cir pin for the A83T

2018-01-29 Thread Philipp Rossak
The CIR Pin of the A83T is located at PL12.

Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index de5119a2a91c..06e96db7c41a 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -617,6 +617,11 @@
interrupt-controller;
#interrupt-cells = <3>;
 
+   cir_pins: cir-pins@0 {
+   pins = "PL12";
+   function = "s_cir_rx";
+   };
+
r_rsb_pins: r-rsb-pins {
pins = "PL0", "PL1";
function = "s_rsb";
-- 
2.11.0

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[linux-sunxi] [PATCH v5 5/6] arm: dts: sun8i: a83t: bananapi-m3: Enable IR controller

2018-01-29 Thread Philipp Rossak
The Bananapi M3 has an onboard IR receiver.
This enables the onboard IR receiver subnode.
Unlike the other IR receivers this one needs a base clock frequency
of 300 Hz (3 MHz), to be able to work.

Signed-off-by: Philipp Rossak <embe...@gmail.com>
Acked-by: Chen-Yu Tsai <w...@csie.org>
---
 arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts 
b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
index 6550bf0e594b..ffc6445fd281 100644
--- a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
@@ -82,6 +82,13 @@
};
 };
 
+ {
+   pinctrl-names = "default";
+   pinctrl-0 = <_pins>;
+   clock-frequency = <300>;
+   status = "okay";
+};
+
  {
/* Terminus Tech FE 1.1s 4-port USB 2.0 hub here */
status = "okay";
-- 
2.11.0

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[linux-sunxi] [PATCH v4 1/6] media: rc: update sunxi-ir driver to get base clock frequency from devicetree

2018-01-29 Thread Philipp Rossak
This patch updates the sunxi-ir driver to set the base clock frequency from
devicetree.

This is necessary since there are different ir receivers on the
market, that operate with different frequencies. So this value could be
set if the attached ir receiver needs a different base clock frequency,
than the default 8 MHz.

Signed-off-by: Philipp Rossak <embe...@gmail.com>
Reviewed-by: Andi Shyti <andi.sh...@samsung.com>
Acked-by: Sean Young <s...@mess.org>
---
 drivers/media/rc/sunxi-cir.c | 19 +++
 1 file changed, 11 insertions(+), 8 deletions(-)

diff --git a/drivers/media/rc/sunxi-cir.c b/drivers/media/rc/sunxi-cir.c
index 97f367b446c4..f500cea228a9 100644
--- a/drivers/media/rc/sunxi-cir.c
+++ b/drivers/media/rc/sunxi-cir.c
@@ -72,12 +72,8 @@
 /* CIR_REG register idle threshold */
 #define REG_CIR_ITHR(val)(((val) << 8) & (GENMASK(15, 8)))
 
-/* Required frequency for IR0 or IR1 clock in CIR mode */
+/* Required frequency for IR0 or IR1 clock in CIR mode (default) */
 #define SUNXI_IR_BASE_CLK 800
-/* Frequency after IR internal divider  */
-#define SUNXI_IR_CLK  (SUNXI_IR_BASE_CLK / 64)
-/* Sample period in ns */
-#define SUNXI_IR_SAMPLE   (10ul / SUNXI_IR_CLK)
 /* Noise threshold in samples  */
 #define SUNXI_IR_RXNOISE  1
 /* Idle Threshold in samples */
@@ -122,7 +118,8 @@ static irqreturn_t sunxi_ir_irq(int irqno, void *dev_id)
/* for each bit in fifo */
dt = readb(ir->base + SUNXI_IR_RXFIFO_REG);
rawir.pulse = (dt & 0x80) != 0;
-   rawir.duration = ((dt & 0x7f) + 1) * SUNXI_IR_SAMPLE;
+   rawir.duration = ((dt & 0x7f) + 1) *
+ir->rc->rx_resolution;
ir_raw_event_store_with_filter(ir->rc, );
}
}
@@ -148,6 +145,7 @@ static int sunxi_ir_probe(struct platform_device *pdev)
struct device_node *dn = dev->of_node;
struct resource *res;
struct sunxi_ir *ir;
+   u32 b_clk_freq = SUNXI_IR_BASE_CLK;
 
ir = devm_kzalloc(dev, sizeof(struct sunxi_ir), GFP_KERNEL);
if (!ir)
@@ -172,6 +170,9 @@ static int sunxi_ir_probe(struct platform_device *pdev)
return PTR_ERR(ir->clk);
}
 
+   /* Base clock frequency (optional) */
+   of_property_read_u32(dn, "clock-frequency", _clk_freq);
+
/* Reset (optional) */
ir->rst = devm_reset_control_get_optional_exclusive(dev, NULL);
if (IS_ERR(ir->rst))
@@ -180,11 +181,12 @@ static int sunxi_ir_probe(struct platform_device *pdev)
if (ret)
return ret;
 
-   ret = clk_set_rate(ir->clk, SUNXI_IR_BASE_CLK);
+   ret = clk_set_rate(ir->clk, b_clk_freq);
if (ret) {
dev_err(dev, "set ir base clock failed!\n");
goto exit_reset_assert;
}
+   dev_dbg(dev, "set base clock frequency to %d Hz.\n", b_clk_freq);
 
if (clk_prepare_enable(ir->apb_clk)) {
dev_err(dev, "try to enable apb_ir_clk failed\n");
@@ -225,7 +227,8 @@ static int sunxi_ir_probe(struct platform_device *pdev)
ir->rc->map_name = ir->map_name ?: RC_MAP_EMPTY;
ir->rc->dev.parent = dev;
ir->rc->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;
-   ir->rc->rx_resolution = SUNXI_IR_SAMPLE;
+   /* Frequency after IR internal divider with sample period in ns */
+   ir->rc->rx_resolution = (10ul / (b_clk_freq / 64));
ir->rc->timeout = MS_TO_NS(SUNXI_IR_TIMEOUT);
ir->rc->driver_name = SUNXI_IR_DEV;
 
-- 
2.11.0

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[linux-sunxi] [PATCH v4 0/6] arm: sunxi: IR support for A83T

2018-01-29 Thread Philipp Rossak
This patch series adds support for the sunxi A83T ir module and enhances 
the sunxi-ir driver. Right now the base clock frequency for the ir driver
is a hard coded define and is set to 8 MHz.
This works for the most common ir receivers. On the Sinovoip Bananapi M3 
the ir receiver needs, a 3 MHz base clock frequency to work without
problems with this driver.

This patch series adds support for an optinal property that makes it able
to override the default base clock frequency and enables the ir interface 
on the a83t and the Bananapi M3.

In general this is a resend of the v3 Patchseries, but with collected acked-by
and reviewed-by and some typos fixed.

changes since v3:
* collecting all acks & reviewd by
* fixed typos

changes since v2:
* reorder cir pin (alphabetical)
* fix typo in documentation

changes since v1:
* fix typos, reword Documentation
* initialize 'b_clk_freq' to 'SUNXI_IR_BASE_CLK' & remove if statement
* change dev_info() to dev_dbg()
* change naming to cir* in dts/dtsi
* Added acked Ackedi-by to related patch
* use whole memory block instead of registers needed + fix for h3/h5

changes since rfc:
* The property is now optinal. If the property is not available in 
  the dtb the driver uses the default base clock frequency.
* the driver prints out the the selected base clock frequency.
* changed devicetree property from base-clk-frequency to clock-frequency

Regards,
Philipp


Philipp Rossak (6):
  media: rc: update sunxi-ir driver to get base clock frequency from
devicetree
  media: dt: bindings: Update binding documentation for sunxi IR
controller
  arm: dts: sun8i: a83t: Add the cir pin for the A83T
  arm: dts: sun8i: a83t: Add support for the cir interface
  arm: dts: sun8i: a83t: bananapi-m3: Enable IR controller
  arm: dts: sun8i: h3-h8: ir register size should be the whole memory
block

 Documentation/devicetree/bindings/media/sunxi-ir.txt |  3 +++
 arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts |  7 +++
 arch/arm/boot/dts/sun8i-a83t.dtsi| 15 +++
 arch/arm/boot/dts/sunxi-h3-h5.dtsi   |  2 +-
 drivers/media/rc/sunxi-cir.c | 19 +++
 5 files changed, 37 insertions(+), 9 deletions(-)

-- 
2.11.0

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[linux-sunxi] [PATCH v4 6/6] arm: dts: sun8i: h3-h8: ir register size should be the whole memory block

2018-01-29 Thread Philipp Rossak
The size of the register should be the size of the whole memory block,
not just the registers, that are needed.

Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
 arch/arm/boot/dts/sunxi-h3-h5.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi 
b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index 8d40c00d64bb..a9caeda4a574 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -674,7 +674,7 @@
clock-names = "apb", "ir";
resets = <_ccu RST_APB0_IR>;
interrupts = ;
-   reg = <0x01f02000 0x40>;
+   reg = <0x01f02000 0x400>;
status = "disabled";
};
 
-- 
2.11.0

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[linux-sunxi] [PATCH v4 2/6] media: dt: bindings: Update binding documentation for sunxi IR controller

2018-01-29 Thread Philipp Rossak
This patch updates documentation for Device-Tree bindings for sunxi IR
controller and adds the new optional property for the base clock
frequency.

Signed-off-by: Philipp Rossak <embe...@gmail.com>
Acked-by: Maxime Ripard <maxime.rip...@free-electrons.com>
Reviewed-by: Rob Herring <r...@kernel.org>
---
 Documentation/devicetree/bindings/media/sunxi-ir.txt | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/media/sunxi-ir.txt 
b/Documentation/devicetree/bindings/media/sunxi-ir.txt
index 91648c569b1e..278098987edb 100644
--- a/Documentation/devicetree/bindings/media/sunxi-ir.txt
+++ b/Documentation/devicetree/bindings/media/sunxi-ir.txt
@@ -11,6 +11,8 @@ Required properties:
 Optional properties:
 - linux,rc-map-name: see rc.txt file in the same directory.
 - resets : phandle + reset specifier pair
+- clock-frequency  : IR Receiver clock frequency, in Hertz. Defaults to 8 MHz
+if missing.
 
 Example:
 
@@ -18,6 +20,7 @@ ir0: ir@1c21800 {
compatible = "allwinner,sun4i-a10-ir";
clocks = <_gates 6>, <_clk>;
clock-names = "apb", "ir";
+   clock-frequency = <300>;
resets = <_rst 1>;
interrupts = <0 5 1>;
reg = <0x01C21800 0x40>;
-- 
2.11.0

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[linux-sunxi] [PATCH v4 4/6] arm: dts: sun8i: a83t: Add support for the cir interface

2018-01-29 Thread Philipp Rossak
The cir interface is like on the H3 located at 0x01f02000 and is exactly
the same. This patch adds support for the ir interface on the A83T.

Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi 
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 06e96db7c41a..ddc0d592107f 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -605,6 +605,16 @@
#reset-cells = <1>;
};
 
+   cir: cir@01f02000 {
+   compatible = "allwinner,sun5i-a13-ir";
+   clocks = <_ccu CLK_APB0_IR>, <_ccu CLK_IR>;
+   clock-names = "apb", "ir";
+   resets = <_ccu RST_APB0_IR>;
+   interrupts = ;
+   reg = <0x01f02000 0x400>;
+   status = "disabled";
+   };
+
r_pio: pinctrl@1f02c00 {
compatible = "allwinner,sun8i-a83t-r-pinctrl";
reg = <0x01f02c00 0x400>;
-- 
2.11.0

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[linux-sunxi] Re: [PATCH v2 07/16] iio: adc: sun4i-gpadc-iio: rework: support nvmem calibration data

2018-01-29 Thread Philipp Rossak



On 29.01.2018 10:40, Maxime Ripard wrote:

On Mon, Jan 29, 2018 at 12:29:10AM +0100, Philipp Rossak wrote:

This patch reworks the driver to support nvmem calibration cells.
The driver checks if the nvmem calibration is supported and reads out
the nvmem.

Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
  drivers/iio/adc/sun4i-gpadc-iio.c | 44 +++
  1 file changed, 44 insertions(+)

diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c 
b/drivers/iio/adc/sun4i-gpadc-iio.c
index ac9ad2f8232f..74eeb5cd5218 100644
--- a/drivers/iio/adc/sun4i-gpadc-iio.c
+++ b/drivers/iio/adc/sun4i-gpadc-iio.c
@@ -27,6 +27,7 @@
  #include 
  #include 
  #include 
+#include 
  #include 
  #include 
  #include 
@@ -74,6 +75,7 @@ struct gpadc_data {
boolhas_bus_rst;
boolhas_mod_clk;
int sensor_count;
+   boolsupports_nvmem;


I think you should add some documentation along with all the fields
you're adding.


ok I will add more informations in the next version into the commit message.




  };
  
  static const struct gpadc_data sun4i_gpadc_data = {

@@ -87,6 +89,7 @@ static const struct gpadc_data sun4i_gpadc_data = {
.sample_start = sun4i_gpadc_sample_start,
.sample_end = sun4i_gpadc_sample_end,
.sensor_count = 1,
+   .supports_nvmem = false,


That's already its value if you leave it out.


  };
  
  static const struct gpadc_data sun5i_gpadc_data = {

@@ -100,6 +103,7 @@ static const struct gpadc_data sun5i_gpadc_data = {
.sample_start = sun4i_gpadc_sample_start,
.sample_end = sun4i_gpadc_sample_end,
.sensor_count = 1,
+   .supports_nvmem = false,
  };
  
  static const struct gpadc_data sun6i_gpadc_data = {

@@ -113,6 +117,7 @@ static const struct gpadc_data sun6i_gpadc_data = {
.sample_start = sun4i_gpadc_sample_start,
.sample_end = sun4i_gpadc_sample_end,
.sensor_count = 1,
+   .supports_nvmem = false,
  };
  
  static const struct gpadc_data sun8i_a33_gpadc_data = {

@@ -123,6 +128,7 @@ static const struct gpadc_data sun8i_a33_gpadc_data = {
.sample_start = sun4i_gpadc_sample_start,
.sample_end = sun4i_gpadc_sample_end,
.sensor_count = 1,
+   .supports_nvmem = false,
  };
  
  struct sun4i_gpadc_iio {

@@ -141,6 +147,8 @@ struct sun4i_gpadc_iio {
struct clk  *mod_clk;
struct reset_control*reset;
int sensor_id;
+   u32 calibration_data[2];
+   boolhas_calibration_data[2];


Why do you have two different values here?



I think my idea was too complex! I thought it would be better to check 
if calibration data was read, and is able to be written to hardware. 
those information were split per register.


I think a u64 should be fine for calibration_data. When I write the 
calibration data I can check on the sensor count and write only the 
lower 32 bits if there are less than 3 sensors.


Is this ok for you?



/* prevents concurrent reads of temperature and ADC */
struct mutexmutex;
struct thermal_zone_device  *tzd;
@@ -561,6 +569,9 @@ static int sun4i_gpadc_probe_dt(struct platform_device 
*pdev,
struct resource *mem;
void __iomem *base;
int ret;
+   struct nvmem_cell *cell;
+   ssize_t cell_size;
+   u64 *cell_data;
  
  	info->data = of_device_get_match_data(>dev);

if (!info->data)
@@ -575,6 +586,39 @@ static int sun4i_gpadc_probe_dt(struct platform_device 
*pdev,
if (IS_ERR(base))
return PTR_ERR(base);
  
+	info->has_calibration_data[0] = false;

+   info->has_calibration_data[1] = false;
+
+   if (!info->data->supports_nvmem)
+   goto no_nvmem;
+
+   cell = nvmem_cell_get(>dev, "calibration");
+   if (IS_ERR(cell)) {
+   if (PTR_ERR(cell) == -EPROBE_DEFER)
+   return PTR_ERR(cell);
+   goto no_nvmem;


goto considered evil ? :)



this was a suggestion from Jonatan in version one, to make the code 
better readable.

.

+   }
+
+   cell_data = (u64 *)nvmem_cell_read(cell, _size);
+   nvmem_cell_put(cell);
+   switch (cell_size) {
+   case 8:
+   case 6:
+   info->has_calibration_data[1] = true;
+   info->calibration_data[1] = be32_to_cpu(
+   upper_32_bits(cell_data[0]));
+   case 4:
+   case 2:
+   info->has_calibration_data[0] = true;
+   info->calibration_data[0] = be32_to_cpu(
+   lower_32_bits(cell_data[0]));


Why do you need that switch?


You are right! The calibration reg seems to be always 64 bi

[linux-sunxi] Re: [PATCH v2 01/16] dt-bindings: update the Allwinner GPADC device tree binding for H3 & A83T

2018-01-29 Thread Philipp Rossak

+Example for A33:
ths: ths@1c25000 {
compatible = "allwinner,sun8i-a33-ths";
reg = <0x01c25000 0x100>;
@@ -17,6 +40,27 @@ Example:
#io-channel-cells = <0>;
};
  
+Example for H3:

+   ths: thermal-sensor@1c25000 {
+   compatible = "allwinner,sun8i-h3-ths";
+   reg = <0x01c25000 0x400>;
+   clocks = < CLK_BUS_THS>, < CLK_THS>;
+   clock-names = "bus", "mod";
+   resets = < RST_BUS_THS>;
+   interrupts = ;
+   #thermal-sensor-cells = <0>;
+   #io-channel-cells = <0>;
+   };
+
+Example for A83T:
+   ths: thermal-sensor@1f04000 {
+   compatible = "allwinner,sun8i-a83t-ths";
+   reg = <0x01f04000 0x100>;
+   interrupts = ;
+   #thermal-sensor-cells = <1>;
+   #io-channel-cells = <0>;
+   };
+


I'm wondering if this is actually needed. We've used this convoluted
constructs to be compatible with the old driver, but I'm not sure this
is actually worth it now, and this is causing several issues, among
which:
   - We need to have a bunch of quirks to handle all the DT cases.
   - We need to have an MFD, which isn't really optimal

So I'd rather introduce a new compatible for the old SoCs, keep the
old driver around, and simplify a lot that driver code that will ease
further developments. And we can also get rid of the MFD in the
process. I discussed it with Quentin, and he was ok with it, what do
you think?

(and that would involve creating a new file for the bindings you
introduce here).

Maxime



I think this is a good idea, and the desired way to rework the driver.

To sum up what we talked on IRC:

This will end up in removing the MFD driver and moving the interrupt 
handling into the iio driver. At the end this will also simplify the IRQ 
part.


Philipp

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[linux-sunxi] Re: [PATCH v2 14/16] arm: dts: sun8i: h3: enable H3 sid controller

2018-01-29 Thread Philipp Rossak



On 29.01.2018 10:52, Maxime Ripard wrote:

On Mon, Jan 29, 2018 at 12:29:17AM +0100, Philipp Rossak wrote:

This patch enables the the sid controller in the H3. It can be used
for thermal calibration data.

Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
  arch/arm/boot/dts/sun8i-h3.dtsi | 7 +++
  1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 3f83f6a27c74..9bb5cc29fec5 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -72,6 +72,13 @@
};
};
  
+	soc {

+   sid: eeprom@1c14000 {
+   compatible = "allwinner,sun8i-h3-sid";
+   reg = <0x01c14000 0x400>;
+   };
+   };
+


Shouldn't you also use a nvmem-cells property to the THS node?

Maxime



Oh seems like I forgot that.
As related to the wiki [1] this should be 64 bit wide at the address 
0x34. I will add that in the next version.



[1]: http://linux-sunxi.org/SID_Register_Guide#eFUSE

Thanks,
Philipp

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[linux-sunxi] Re: [PATCH v2 13/16] arm: dts: sun8i: h3: add thermal zone to H3

2018-01-29 Thread Philipp Rossak



On 29.01.2018 10:50, Maxime Ripard wrote:

On Mon, Jan 29, 2018 at 12:29:16AM +0100, Philipp Rossak wrote:

This patch adds the thermal zones to the H3. We have only one sensor and
that is placed in the cpu.

Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
  arch/arm/boot/dts/sun8i-h3.dtsi | 9 +
  1 file changed, 9 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index fbb007e5798e..3f83f6a27c74 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -72,6 +72,15 @@
};
};
  
+	thermal-zones {

+   cpu-thermal {
+   /* milliseconds */
+   polling-delay-passive = <250>;
+   polling-delay = <1000>;
+   thermal-sensors = < 0>;


if the thermal-sensor-cells value is indeed 0, the phandle parsing
will be broken here.

Maxime



Ok, then I will remove the 0.

Thanks,

Philipp

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