在 2022-10-14星期五的 11:05 +0800，Icenowy Zheng写道：
> Signed-off-by: Icenowy Zheng
By the way should we have some better way to handle the placement of
environments?
> ---
> board/sunxi/board.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/board/sunxi/board.c b/b
于 2023年1月15日 GMT+08:00 上午3:56:08, Samuel Holland 写到:
>On 10/13/22 22:05, Icenowy Zheng wrote:
>> As we're going to add support for SPI NAND to this code, add code that
>> allows multiple boot attempts with different load offsets and functions.
>>
>> To kee
Signed-off-by: Icenowy Zheng
---
board/sunxi/board.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 21a2407e06..f4138573d4 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -133,6 +133,7 @@ void i2c_init_board(void)
*/
enum
Signed-off-by: Icenowy Zheng
---
arch/arm/dts/Makefile| 3 +-
arch/arm/dts/suniv-f1c100s-licheepi-nano.dts | 16 +++
arch/arm/dts/suniv-f1c100s.dtsi | 26 +
arch/arm/dts/suniv-f1c200s-popstick-v1.1.dts | 101 +++
4 files changed, 145
As we added support for SPI NAND to the existing SPL SPI codepath, route
the boot code to it when it detects the BROM loads SPL from SPI NAND, as
for SoCs with both SPI NAND and boot media indicator support, the boot
media indicator is the same for SPI NOR and NAND.
Signed-off-by: Icenowy Zheng
---
configs/popstick_defconfig | 35 +++
1 file changed, 35 insertions(+)
create mode 100644 configs/popstick_defconfig
diff --git a/configs/popstick_defconfig b/configs/popstick_defconfig
new file mode 100644
index 00..6dc21695b7
--- /dev/null
+++ b/confi
ample of PopStick, U-Boot main part is assumed to be
with 0x800 page size (which is the real situation of the W25N01 flash
used by PopStick).
Icenowy Zheng (8):
sunxi: SPL SPI: extract code for doing SPI transfer
sunxi: SPL SPI: add support for read command with 2 byte address
sunxi: SPL SPI:
To support SPI NAND flashes, more commands than Read (03h) are needed.
Extract the code for doing SPI transfer from the reading code for code
reuse.
Signed-off-by: Icenowy Zheng
---
arch/arm/mach-sunxi/spl_spi_sunxi.c | 105
1 file changed, 59 insertions(+), 46
makes it not compatible with usual 3 byte address.
Signed-off-by: Icenowy Zheng
---
arch/arm/mach-sunxi/spl_spi_sunxi.c | 20 +---
1 file changed, 13 insertions(+), 7 deletions(-)
diff --git a/arch/arm/mach-sunxi/spl_spi_sunxi.c
b/arch/arm/mach-sunxi/spl_spi_sunxi.c
index
I NOR.
Signed-off-by: Icenowy Zheng
---
arch/arm/mach-sunxi/spl_spi_sunxi.c | 58 +++--
1 file changed, 38 insertions(+), 20 deletions(-)
diff --git a/arch/arm/mach-sunxi/spl_spi_sunxi.c
b/arch/arm/mach-sunxi/spl_spi_sunxi.c
index 88c15a3ee9..21be33a23f 100644
--- a/arc
This commit adds support for booting from SPI NAND to SPL SPI code by
mimicing the behavior of boot ROM (use fixed page size and sequentially
try SPI NOR and NAND).
Signed-off-by: Icenowy Zheng
---
arch/arm/mach-sunxi/Kconfig | 16 +++
arch/arm/mach-sunxi/spl_spi_sunxi.c | 74
于 2021年8月6日 GMT+08:00 下午8:05:56, Chen-Yu Tsai 写到:
>On Fri, Aug 6, 2021 at 7:49 PM Icenowy Zheng wrote:
>>
>> 在 2021-07-22星期四的 10:16 +0200，Maxime Ripard写道：
>> > On Thu, Jul 22, 2021 at 12:55:53AM -0500, Samuel Holland wrote:
>> > > On 7/21/21 9:04 A
在 2021-07-22星期四的 10:16 +0200，Maxime Ripard写道：
> On Thu, Jul 22, 2021 at 12:55:53AM -0500, Samuel Holland wrote:
> > On 7/21/21 9:04 AM, Maxime Ripard wrote:
> > > The regulator-ramp-delay property isn't documented in the binding
> > > for
> > > the AXP806, and it's ignored by the driver. Remove tho
于 2021年7月29日 GMT+08:00 下午6:32:28, Maxime Ripard 写到:
>On Thu, Jul 29, 2021 at 04:04:10PM +0800, Icenowy Zheng wrote:
>> 在 2021-06-16星期三的 11:14 +0200，Maxime Ripard写道：
>> > Hi,
>> >
>> > On Tue, Jun 15, 2021 at 12:06:23PM +0100, Andre Przywara wrote:
&
在 2021-06-16星期三的 11:14 +0200，Maxime Ripard写道：
> Hi,
>
> On Tue, Jun 15, 2021 at 12:06:23PM +0100, Andre Przywara wrote:
> > Some newer Allwinner RTCs (for instance the one in the H616 SoC)
> > lack
> > a pin for an external 32768 Hz oscillator. As a consequence, this
> > LOSC
> > can't be selected
在 2021-07-23星期五的 16:38 +0100，Andre Przywara写道：
> Hi,
>
> another try on the basic Allwinner H616 support, now on top of 5.14-
> rc1.
>
> This time I dropped the USB support from the basic series, to split
> off
> the discussion, and simplify the core SoC support. I will post the
> USB
> series so
Hao,
Would you mind me to continue on this work? Newer Allwinner SoCs have
PWM controllers similar to the R40 one.
Yours sincerely,
Icenowy Zheng
在 2018-11-26星期一的 00:18 +0800，Hao Zhang写道：
> PWM support for allwinner sun8i R40/T3/V40 SOCs.
>
> The sun8i R40/T3/V40 PWM has 8 PWM cha
在 2021-03-02星期二的 15:19 +，Andre Przywara写道：
> On Tue, 02 Mar 2021 21:50:49 +0800
> Icenowy Zheng wrote:
>
> Hi Icenowy,
>
> > 于 2021年3月2日 GMT+08:00 下午9:40:44, Andre Przywara <
> > andre.przyw...@arm.com> 写到:
> > > On Fri, 26 Feb 2021
在 2021-03-02星期二的 15:19 +，Andre Przywara写道：
> On Tue, 02 Mar 2021 21:50:49 +0800
> Icenowy Zheng wrote:
>
> Hi Icenowy,
>
> > 于 2021年3月2日 GMT+08:00 下午9:40:44, Andre Przywara <
> > andre.przyw...@arm.com> 写到:
> > > On Fri, 26 Feb 2021
于 2021年3月2日 GMT+08:00 下午9:40:44, Andre Przywara 写到:
>On Fri, 26 Feb 2021 00:13:25 +0800
>Icenowy Zheng wrote:
>
>> Previously we do not have proper dual rank memory detection on R40
>> (because we omitted PIR_QSGATE, which does not work on R40 with our
>> configura
R40.
Similar routine can be used to detect half DQ width (which is also
detected by PIR_QSGATE on other SoCs), but it's left unimplemented
because there's no known R40 board with half DQ width now.
Signed-off-by: Icenowy Zheng
---
arch/arm/mach-sunxi/dram_sunxi
rank detection is broken on R40 now, we cannot really use it on R40
currently.
Signed-off-by: Icenowy Zheng
---
.../include/asm/arch-sunxi/dram_sunxi_dw.h| 11 ++-
arch/arm/mach-sunxi/dram_sunxi_dw.c | 94 +++
2 files changed, 82 insertions(+), 23 deletions(-)
diff
tries to access rank 1 and then check for error. It's placed at 2nd
patch because it depends on the function that calculates rank 0 size
(and rank 1 base address) introduced in PATCH 1.
Icenowy Zheng (2):
sunxi: support asymmetric dual rank DRAM on A64/R40
sunxi: enable dual rank memory o
As the original PineTab DT (which uses sun50i-a64-pinetab name) is only
for development samples, document this.
Signed-off-by: Icenowy Zheng
---
Documentation/devicetree/bindings/arm/sunxi.yaml | 2 +-
arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts | 2 +-
2 files changed, 2
PineTabs since Early Adopter batch will use a new LCD panel.
Add device tree for PineTab with the new panel.
Signed-off-by: Icenowy Zheng
---
arch/arm64/boot/dts/allwinner/Makefile| 1 +
.../sun50i-a64-pinetab-early-adopter.dts | 26 +++
2 files changed, 27
Early adopter's PineTabs (and further releases) will have a new LCD
panel different with the one that is used when in development (because
the old panel's supply discontinued).
Add a new DT compatible for it.
Signed-off-by: Icenowy Zheng
---
Documentation/devicetree/bindings/arm/sunx
在 2020-12-16星期三的 14:00 +0100，Maxime Ripard写道：
> On Tue, Dec 15, 2020 at 06:59:33AM +0800, Icenowy Zheng wrote:
> > 于 2020年12月14日 GMT+08:00 下午6:37:04, Maxime Ripard > > 写到:
> > > On Thu, Dec 10, 2020 at 04:42:32PM +0800, Icenowy Zheng wrote:
> > > > Early
于 2020年12月14日 GMT+08:00 下午6:37:04, Maxime Ripard 写到:
>On Thu, Dec 10, 2020 at 04:42:32PM +0800, Icenowy Zheng wrote:
>> Early adopters' PineTabs (and all further releases) will have a new
>LCD
>> panel different with the one that is used when in development
>(because
在 2020-12-14星期一的 01:35 +，André Przywara写道：
> On 13/12/2020 18:24, Icenowy Zheng wrote:
> > 在 2020-12-11星期五的 01:19 +，Andre Przywara写道：
> > > Newer SoCs (A100, H616) need to clear a different bit in our
> > > "unknown"
> > > PMU PHY registe
在 2020-12-11星期五的 01:19 +，Andre Przywara写道：
> Newer SoCs (A100, H616) need to clear a different bit in our
> "unknown"
> PMU PHY register.
It looks like that the unknown PHY register is PHYCTL register for each
individual PHY, and the bit that is cleared is
called SUNXI_HCI_PHY_CTRL_SIDDQ in th
在 2020-12-11星期五的 01:19 +，Andre Przywara写道：
> Hi,
>
> this is the quite expanded second version of the support series for
> the
> Allwinner H616 SoC.
> Besides many fixes for the bugs discovered by the diligent reviewers
> (many thanks for that!) this version adds some patches to support
> some
rl/sunxi/pinctrl-sun50i-h616.c
> b/drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c
> new file mode 100644
> index ..734f63eb08dd
> --- /dev/null
> +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c
> @@ -0,0 +1,549 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> +
rs/clk/sunxi-ng/ccu-sun50i-h616.c
> new file mode 100644
> index 0000..3fbb258f0354
> --- /dev/null
> +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h616.c
> @@ -0,0 +1,1134 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2020 Arm Ltd.
> + * Based on th
As the old LCD panel used by PineTab developer samples are discontinued,
there won't be furtherly any more units of the sample, and this should
be noted in the document.
Signed-off-by: Icenowy Zheng
---
Documentation/devicetree/bindings/arm/sunxi.yaml | 2 +-
1 file changed, 1 insertion(
Further released PineTabs will have a new LCD panel that is different
with the one used in developers' samples.
Add device tree for PineTab with the new panel.
Signed-off-by: Icenowy Zheng
---
arch/arm64/boot/dts/allwinner/Makefile| 1 +
.../sun50i-a64-pinetab-new-pane
Early adopters' PineTabs (and all further releases) will have a new LCD
panel different with the one that is used when in development (because
the old panel's supply discontinued).
Add a new DT compatible for it.
Signed-off-by: Icenowy Zheng
---
Documentation/devicetree/bindings/arm/
As discussed on the mailing list, here introduces a new DT for new
PineTabs.
Icenowy Zheng (3):
dt-bindings: arm: sunxi: add PineTab new panel DT binding
arm64: allwinner: dts: a64: add DT for PineTab with new LCD panel
dt-bindings: arm: sunxi: note that old PineTab compatible has old
j-$(CONFIG_PINCTRL_SUN50I_H6_R) += pinctrl-sun50i-h6-r.o
>>>>
>>>> +obj-$(CONFIG_PINCTRL_SUN50I_H616) += pinctrl-sun50i-h616.o
>>>>
>>>> obj-$(CONFIG_PINCTRL_SUN9I_A80)+=
>pinctrl-sun9i-a80.o
>>>> obj-
ine CLK_BUS_I2C1 75
> > > +#define CLK_BUS_I2C2 76
> > > +#define CLK_BUS_I2C3 77
> > > +#define CLK_BUS_I2C4 78
> > > +#define CLK_SPI0 79
> > > +#define CLK_SPI1 80
> > > +#define CLK_BUS_SPI
于 2020年12月3日 GMT+08:00 下午7:07:02, "André Przywara" 写到:
>On 02/12/2020 14:31, Icenowy Zheng wrote:
>
>Hi,
>
>> 于 2020年12月2日 GMT+08:00 下午9:54:05, Andre Przywara
> 写到:
>>> The clocks itself are identical to the H6 R-CCU, it's just that the
>
-0,0 +1,704 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +// Copyright (C) 2020 Arm Ltd.
>> +// based on the H6 dtsi, which is:
>> +// Copyright (C) 2017 Icenowy Zheng
>> +
>> +#include
>> +#include
>> +#include
>> +#include
>> +#i
file mode 100644
> index ..dcffbfdcd26b
> --- /dev/null
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
> @@ -0,0 +1,704 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +// Copyright (C) 2020 Arm Ltd.
> +// based on the H6 dtsi, which is:
> +// C
在 2020-12-02星期三的 13:54 +，Andre Przywara写道：
> The OrangePi Zero 2 is a development board with the new H616 SoC.
>
> It features the usual connectors used on those small boards, and
> comes
> with the AXP305, which seems to be compatible with the AXP805.
>
> For more details see: http://linux-s
于 2020年12月2日 GMT+08:00 下午9:54:05, Andre Przywara 写到:
>The clocks itself are identical to the H6 R-CCU, it's just that the
>H616
>has not all of them implemented (or connected).
For selective clocks, try to follow the practice of V3(s) driver?
>
>Signed-off-by: Andre Przywara
>---
> drivers/c
于 2020年11月28日 GMT+08:00 下午7:54:04, "Clément Péron" 写到:
>Hi Icenowy,
>
>On Sat, 28 Nov 2020 at 12:28, Icenowy Zheng wrote:
>>
>> 在 2020-11-28星期六的 11:38 +0100，Maxime Ripard写道：
>> > On Mon, Nov 23, 2020 at 09:10:38PM +0800, Icenowy Zheng wrote:
>> &g
urning into FEL mode, so that other payloads can be
> transferred via FEL as well.
>
> Tested on A64, H5 and H6.
>
> Signed-off-by: Andre Przywara
Tested-by: Icenowy Zheng
> ---
> arch/arm/cpu/armv8/Makefile | 2 +
> arch/arm/cpu/armv8/fel_utils.S | 78
&
在 2020-11-28星期六的 11:38 +0100，Maxime Ripard写道：
> On Mon, Nov 23, 2020 at 09:10:38PM +0800, Icenowy Zheng wrote:
> > > > > > > Okay. But I'm not satisfied with a non-public sample
> > > > > > > occupies
> > > > > > > the pi
于 2020年11月28日 GMT+08:00 上午11:09:17, Chen-Yu Tsai 写到:
>On Mon, Nov 23, 2020 at 6:22 PM Icenowy Zheng wrote:
>>
>>
>>
>> 于 2020年11月23日 GMT+08:00 上午11:37:43, Chen-Yu Tsai 写到:
>> >On Sun, Nov 22, 2020 at 8:40 AM Icenowy Zheng
>wrote:
>> >>
&
在 2020-11-25星期三的 06:59 +0800，Icenowy Zheng写道：
> The PineCube board has a RTL8189ES Wi-Fi module on board, and the
> module
> doesn't have any MAC address programmed in.
Sorry, but now I'm unsure about this.
The module seems to have MAC address programmed.
>
> Add a
The PineCube board has a RTL8189ES Wi-Fi module on board, and the module
doesn't have any MAC address programmed in.
Add a ethernet alias in the DT, thus the bootloader will then be able to
generate a MAC address into the device tree node of Wi-Fi.
Signed-off-by: Icenowy Zheng
---
arc
于 2020年11月23日 GMT+08:00 下午8:53:32, Maxime Ripard 写到:
>On Mon, Nov 23, 2020 at 07:25:47PM +0800, Icenowy Zheng wrote:
>>
>>
>> 于 2020年11月23日 GMT+08:00 下午7:15:12, Maxime Ripard
>写到:
>> >Hi!
>> >
>> >On Fri, Nov 20, 2020 at 08:51:48PM -06
于 2020年11月23日 GMT+08:00 下午7:15:12, Maxime Ripard 写到:
>Hi!
>
>On Fri, Nov 20, 2020 at 08:51:48PM -0600, Samuel Holland wrote:
>> On 11/20/20 5:30 PM, Icenowy Zheng wrote:
>> >>>>>>> +/ {
>> >>>>>>> +model = "P
于 2020年11月23日 GMT+08:00 上午11:37:43, Chen-Yu Tsai 写到:
>On Sun, Nov 22, 2020 at 8:40 AM Icenowy Zheng wrote:
>>
>> As the USB port on Lichee Pi Zero works in the OTG mode, enable the
>> EHCI/OHCI controllers for it.
>
>You should probably mention that the host contro
The PineCube board features a USB Type-A connector connected to the
SoC's USB pins.
As this is not designed for being used as a USB device, disable OTG
controller and route USB to OHCI/EHCI fixedly.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-s3-pinecube.dts
As the USB port on Lichee Pi Zero works in the OTG mode, enable the
EHCI/OHCI controllers for it.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
b/arch/arm
The USB PHY 0 on V3s SoC can also be routed to a pair of EHCI/OHCI
controllers.
Add the device nodes for the controllers.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-v3s.dtsi | 19 +++
1 file changed, 19 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi
Formerly I forgot to add EHCI/OHCI0 device nodes to V3s DTs.
This patchset adds them, and switches PineCube to use only OHCI/EHCI,
not MUSB.
Icenowy Zheng (3):
ARM: dts: sun8i: v3s: add EHCI/OHCI0 device nodes
ARM: dts: sun8i: v3s: enable EHCI/OHCI for Lichee Pi Zero
ARM: dts: sun8i: s3
于 2020年11月20日 GMT+08:00 下午11:59:39, Maxime Ripard 写到:
>On Tue, Nov 17, 2020 at 02:36:48AM +0800, Icenowy Zheng wrote:
>>
>>
>> 于 2020年11月16日 GMT+08:00 下午11:55:08, Maxime Ripard
>写到:
>> >On Tue, Nov 10, 2020 at 06:41:37PM +0800, Icenowy Zheng wrote:
>>
Currently the GIC node in V3s DTSI follows some old DT examples, and
being broken. This leads a warning at boot.
Fix this.
Fixes: f989086ccbc6 ("ARM: dts: sunxi: add dtsi file for V3s SoC")
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-v3s.dtsi | 2 +-
1 file changed, 1
MAINTAINER item and provide a defconfig.
Signed-off-by: Icenowy Zheng
---
Changes since v2:
- Add Makefile reference to DT.
Changes since v1:
- Dropped LDO3 quirk.
arch/arm/dts/Makefile | 1 +
board/sunxi/MAINTAINERS| 5 +
configs/pinecube_defconfig | 15 +++
3 files
.
Signed-off-by: Icenowy Zheng
---
Changes in v2:
- Removed LDO3 hack in U-Boot because LDO3 is kept disabled in U-Boot.
board/sunxi/MAINTAINERS| 5 +
configs/pinecube_defconfig | 15 +++
2 files changed, 20 insertions(+)
create mode 100644 configs/pinecube_defconfig
diff
于 2020年11月16日 GMT+08:00 下午11:55:08, Maxime Ripard 写到:
>On Tue, Nov 10, 2020 at 06:41:37PM +0800, Icenowy Zheng wrote:
>>
>>
>> 于 2020年11月10日 GMT+08:00 下午6:39:25, Maxime Ripard
>写到:
>> >On Sat, Nov 07, 2020 at 08:53:32PM +0800, Icenowy Zheng wrote:
>&
于 2020年11月10日 GMT+08:00 下午6:39:25, Maxime Ripard 写到:
>On Sat, Nov 07, 2020 at 08:53:32PM +0800, Icenowy Zheng wrote:
>> Some developers received PineTab samples that used an old LCD panel.
>>
>> Add device tree for these samples.
>>
>> Signed-off-by: Icenowy
jumps backward according to Ondrej Jirman.
Signed-off-by: Icenowy Zheng
---
drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 14 +-
1 file changed, 1 insertion(+), 13 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
index 6108d150a0e3..67d570e
of
PLL-CPUX dividers are behaviors of the BSP kernel.
Icenowy Zheng (2):
clk: sunxi-ng: a64: disable dividers in PLL-CPUX
clk: sunxi-ng: a64: disable mux and pll notifiers for CPUX reclocking
drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 93 ++-
1 file changed, 78
order to prevent boot-time usage of dividers (current known mainline
U-Boot implementation use m = 2), tweaking of the factors are done when
probing CCU driver.
Signed-off-by: Icenowy Zheng
---
drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 79 ++-
1 file changed, 77 insertions(
Some developers received PineTab samples that used an old LCD panel.
Add device tree for these samples.
Signed-off-by: Icenowy Zheng
---
arch/arm64/boot/dts/allwinner/Makefile| 1 +
.../dts/allwinner/sun50i-a64-pinetab-dev.dts | 28 +++
2 files changed, 29 insertions
Some developer samples of PineTab are distributed with the old and
incompatible LCD panel.
Add a device tree binding for this version of PineTab.
Signed-off-by: Icenowy Zheng
---
Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +
1 file changed, 5 insertions(+)
diff --git a
All retail PineTabs use the new panel. Devices with the old panel are
only available to several developers as sample.
Switch the main PineTab DT to use the new panel, as it should reflect
what the retail device uses. Another DT for developers' sample will be
added later.
Signed-off-by: Ic
Retail PineTabs switched to K101-IM2BYL02 panel.
This patchset tries to reflect this change, and add a DT for samples
that still have K101-IM2BA02.
Icenowy Zheng (3):
arm64: allwinner: dts: a64: pinetab: switch LCD panel to production
one
dt-bindings: arm: sunxi: add PineTab developer
于 2020年10月27日 GMT+08:00 上午2:32:30, Maxime Ripard 写到:
>On Mon, Oct 26, 2020 at 10:21:00PM +0800, Icenowy Zheng wrote:
>> PineCube is an IP camera development kit released by Pine64.
>>
>> It comes with the following compoents:
>>
>> - A mainboard with S
.
Signed-off-by: Icenowy Zheng
---
board/sunxi/MAINTAINERS| 5 +
configs/pinecube_defconfig | 17 +
2 files changed, 22 insertions(+)
create mode 100644 configs/pinecube_defconfig
diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS
index 1180b86db3
The reference design of Allwinner V3 series uses an
AXP203 or AXP209 PMIC attached to the I2C0 bus of the SoC, although the
first community-available V3s board, Lichee Pi Zero, omitted it.
Allow to introduce support for the PMIC on boards with it.
Signed-off-by: Icenowy Zheng
---
arch/arm
This commit imports device tree files that are related to Allwinner V3
series from Linux commit 3650b228f83a ("Linux 5.10-rc1").
Signed-off-by: Icenowy Zheng
---
arch/arm/dts/sun8i-s3-lichee-zero-plus.dts| 53 +++
arch/arm/dts/sun8i-s3-pinecube.dts| 235 +
A new compatible string is introduced for V3 CCU, because it has a few
extra features available.
Add the compatible string to the clock driver. As the extra features are
not touched, just share the description struct now.
Signed-off-by: Icenowy Zheng
---
drivers/clk/sunxi/clk_v3s.c | 2 ++
1
A new compatible string is introduced for V3 GPIO, because it has more
pins available than V3s.
Add the compatible string to the GPIO driver.
Signed-off-by: Icenowy Zheng
---
drivers/gpio/sunxi_gpio.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio
: Icenowy Zheng
---
arch/arm/mach-sunxi/Kconfig | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index be0822bfb7..31339ac2a1 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -253,7 +253,7
-Boot.
Finally the device tree is synchorized from Linux v5.10-rc1 (which
contains the PineCube DT) and PineCube defconfig is added.
Icenowy Zheng (6):
sunxi: add V3/S3 support
sunxi: gpio: introduce compatible string for V3 GPIO
clk: sunxi: add compatible string for V3
sunxi: allow to use
于 2020年10月26日 GMT+08:00 上午1:28:48, Andrew Lunn 写到:
>> >> 1. As the PHY chip has hardware configuration for configuring
>delays,
>> >> we should at least have a mode that respects what's set on the
>> >hardware.
>> >
>> >Yes, that is PHY_INTERFACE_MODE_NA. In DT, set the phy-mode to "".
>Or
>> >
于 2020年10月25日 GMT+08:00 下午10:36:08, Andrew Lunn 写到:
>On Sun, Oct 25, 2020 at 10:27:05PM +0800, Icenowy Zheng wrote:
>>
>>
>> 于 2020年10月25日 GMT+08:00 下午10:18:25, Andrew Lunn 写到:
>> >On Sun, Oct 25, 2020 at 04:55:56PM +0800, Icenowy Zheng wrote:
>> >>
于 2020年10月25日 GMT+08:00 下午10:18:25, Andrew Lunn 写到:
>On Sun, Oct 25, 2020 at 04:55:56PM +0800, Icenowy Zheng wrote:
>> Currently there are many boards that just set "rgmii" as phy-mode in
>the
>> device tree, and leave the hardware [TR]XDLY pins to set PHY delay
&g
y devices are
broken.
The definition of "rgmii" in the DT binding document is "RX and TX
delays are added by MAC when required", which at least literally do not
forbid the PHY to add delays.
Fixes: bbc4d71d6354 ("net: phy: realtek: fix rtl8211e rx/tx delay config")
于 2020年10月25日 GMT+08:00 上午2:30:35, "Jernej Škrabec"
写到:
>Dne sobota, 24. oktober 2020 ob 19:51:06 CEST je Icenowy Zheng
>napisal(a):
>> 在 2020-10-25星期日的 00:25 +0800，Chen-Yu Tsai写道：
>>
>> > From: Chen-Yu Tsai
>> >
>> > The Ether
在 2020-10-25星期日的 00:25 +0800，Chen-Yu Tsai写道：
> From: Chen-Yu Tsai
>
> The Ethernet PHY on the A31 Hummingbird has the RX and TX delays
> enabled on the PHY, using pull-ups on the RXDLY and TXDLY pins.
>
> Fix the phy-mode description to correct reflect this so that the
> implementation doesn't r
information from it and tweak some other magic
bits.
Signed-off-by: Icenowy Zheng
---
arch/arm/include/asm/arch-sunxi/cpu.h | 1 +
arch/arm/mach-sunxi/dram_sunxi_dw.c | 91 +--
2 files changed, 87 insertions(+), 5 deletions(-)
diff --git a/arch/arm/include/asm/arch
Add compatible string for V3s, with H3 one as fallback.
This is used in device tree now, but not standardized in DT binding.
Signed-off-by: Icenowy Zheng
---
.../bindings/sram/allwinner,sun4i-a10-system-control.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git
a/Documentation
The address and size cells infomation in CSI subnode is not necessary
(because the camera subnode has no reg property).
Drop them.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-s3-pinecube.dts | 3 ---
1 file changed, 3 deletions(-)
diff --git a/arch/arm/boot/dts/sun8i-s3
This patchset tries to fix DT schema verification errors that exist in
V3-series device trees.
The first patch drops bogus properties that is not needed in PineCube
DT, and the second one adds compatible to the binding.
Icenowy Zheng (2):
ARM: dts: sun8i: s3: drop bogus cells for CSI subnode
allwinner,sun8i-r40-system-control' was expected
>/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dt.yaml:
>system-control@1c0: compatible:0:
>'allwinner,sun50i-a64-sram-controller' was expected
>/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dt.yaml:
>syste
The CSI1 controller of V3/V3s/S3/S3L SoCs is used for parallel CSI.
As we're going to add support for Pine64 SCC board, which uses 8-bit
parallel CSI (and the MCLK output), add the pinctrl node of 8-bit
CSI and MCLK to the DTSI file.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/
module. A RGB LCD connector is reserved on the
board.
The expansion board features a TF slot, a microphone, a speaker
connector with on-board amplifier and a few IR LEDs.
Add support for the kit, with features on the main board and the
expansion board now.
Signed-off-by: Icenowy Zheng
---
arch/arm
I2C1 controller is available at PE bank, usually used for
connecting an I2C-controlled camera sensor.
Add pinctrl node for it.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-v3s.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm
Document board compatible names for Pine64 PineCube IP camera.
Signed-off-by: Icenowy Zheng
---
Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml
b/Documentation/devicetree/bindings/arm
The CSI1 controller of V3/V3s/S3/S3L SoCs is used for parallel CSI.
As we're going to add support for Pine64 SCC board, which uses 8-bit
parallel CSI (and the MCLK output), add the pinctrl node of 8-bit
CSI and MCLK to the DTSI file.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/
The UART2 RX/TX pins on Allwinner V3 series is at PB0/1, which is used
as debugging UART on some boards.
Add pinctrl node for them.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-v3s.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b
The CSI1 controller of V3/V3s/S3/S3L chips is used for parallel CSI.
Add the device tree node of it.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-v3s.dtsi | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i
The Allwinner V3/V3s/S3L/SoChip S3 Ethernet MAC and internal PHY is quite
similar to the ones on Allwinner H3, except for V3s the external MII is
not wired out.
Add ethernet support to V3/V3s/S3/S3L.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-v3.dtsi | 13
arch/arm/boot
LDO2 when LDO4
tweaking.
Icenowy Zheng (7):
ARM: dts: sun8i: V3/V3s/S3/S3L: add Ethernet support
ARM: dts: sun8i: V3/V3s/S3/S3L: add pinctrl for UART2 RX/TX
ARM: dts: sun8i: V3/V3s/S3/S3L: add CSI1 device node
ARM: dts: sun8i: V3/V3s/S3/S3L: add pinctrl for 8-bit parallel CSI
ARM: dts
: use defines for masks")
Signed-off-by: Icenowy Zheng
---
drivers/regulator/axp20x-regulator.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/regulator/axp20x-regulator.c
b/drivers/regulator/axp20x-regulator.c
index 1bacb37e8a99..cd1224182ad7 100644
---
to export
PSCI 0.1, to fix poweroff/reboot regression on Allwinner multi-core
ARMv7 SoCs.
Signed-off-by: Icenowy Zheng
---
arch/arm/cpu/armv7/Kconfig | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/cpu/armv7/Kconfig b/arch/arm/cpu/armv7/Kconfig
index 8eee801dce..60bb0a9e1e
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