[linux-sunxi] Re: Semi ad-hoc fosdem meetup.
Hi Luc, On Wed 31 Jan 24, 17:27, Luc Verhaegen wrote: > Andre had the great idea to create a bit of an informal fosdem meetup. > > We will try to get a table under the Janson building on saturday > afternoon, in the cafeteria. > > This is the area under the really big (and ancient) auditorium, where > you can usually buy coffee and sandwiches. It's a great spot for an informal meeting! Usually one of the most calm areas of FOSDEM (and often a cheat-code to get food easily). > It is tricky to find but you can plot a route on the fosdem map: > https://fosdem.org/2024/assets/campusmap-6166e45e7e736823c218c45ac65e02f5f7237111253db302da17bbaa0f4b5683.png > The J building is in the bottom middle. You can see 2 dotted lines > running to the top right of the J building, one from the H building, one > from the carpark. Both routes work. > > From 17:30 on, we will try to be there with a smallish sign adhoc taped > to the wall saying "#linux-sunxi". If this area for one reason or > another is not open (would be a first for me), or there is absolutely no > hope of occupying anything in there, one of us will be outside with the > sign and we can figure out what to do from there. > > For those that want to, we can try to figure out where to continue the > meeting over supper. Sounds good, I'll be around :) See you there! Paul -- Developer of free digital technology and hardware support. Website: https://www.paulk.fr/ Coding blog: https://code.paulk.fr/ -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/Zbt2nJPPsn4KQ_ii%40felicette. signature.asc Description: PGP signature
[linux-sunxi] Re: [PATCH v5 02/16] phy: Distinguish between Rx and Tx for MIPI D-PHY with submodes
Hi everyone,
On Fri 15 Jan 21, 21:01, Paul Kocialkowski wrote:
> As some D-PHY controllers support both Rx and Tx mode, we need a way for
> users to explicitly request one or the other. For instance, Rx mode can
> be used along with MIPI CSI-2 while Tx mode can be used with MIPI DSI.
>
> Introduce new MIPI D-PHY PHY submodes to use with PHY_MODE_MIPI_DPHY.
> The default (zero value) is kept to Tx so only the rkisp1 driver, which
> uses D-PHY in Rx mode, needs to be adapted.
I think it was Laurent who brought up on IRC that using a submode is probably
not a correct way to distinguish between Rx and Tx modes.
Thinking about it again, it feels like selecting the direction at run-time
would only be relevant if there's D-PHY hardware than can do both Tx and Rx
*and* that can be muxed to either a MIPI DSI and a CSI-2 controller at
run-time.
For the Allwinner case, the D-PHY is the same hardware for both but there will
be one instance attached to each controller, not a single shared instance.
It feels rather unlikely that a device with both MIPI DSI and CSI-2 would only
have one PHY for the two as this wouldn't allow concurrent use of the two
controllers. Even in a case where there'd be n controllers and m < n
bi-directional PHYs, it feels safe to assume that a static attribution would
be sufficient.
As a result it feels more relevant to have this distinction in device-tree
rather than via the PHY API.
What do you think?
Any suggestion on how this should be represented in device-tree?
Cheers,
Paul
> Signed-off-by: Paul Kocialkowski
> Acked-by: Helen Koike
> ---
> drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c | 3 ++-
> include/linux/phy/phy-mipi-dphy.h | 13 +
> 2 files changed, 15 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c
> b/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c
> index 2e5b57e3aedc..cab261644102 100644
> --- a/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c
> +++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c
> @@ -948,7 +948,8 @@ static int rkisp1_mipi_csi2_start(struct rkisp1_isp *isp,
>
> phy_mipi_dphy_get_default_config(pixel_clock, isp->sink_fmt->bus_width,
>sensor->lanes, cfg);
> - phy_set_mode(sensor->dphy, PHY_MODE_MIPI_DPHY);
> + phy_set_mode_ext(cdev->dphy, PHY_MODE_MIPI_DPHY,
> + PHY_MIPI_DPHY_SUBMODE_RX);
> phy_configure(sensor->dphy, );
> phy_power_on(sensor->dphy);
>
> diff --git a/include/linux/phy/phy-mipi-dphy.h
> b/include/linux/phy/phy-mipi-dphy.h
> index a877ffee845d..0f57ef46a8b5 100644
> --- a/include/linux/phy/phy-mipi-dphy.h
> +++ b/include/linux/phy/phy-mipi-dphy.h
> @@ -6,6 +6,19 @@
> #ifndef __PHY_MIPI_DPHY_H_
> #define __PHY_MIPI_DPHY_H_
>
> +/**
> + * enum phy_mipi_dphy_submode - MIPI D-PHY sub-mode
> + *
> + * A MIPI D-PHY can be used to transmit or receive data.
> + * Since some controllers can support both, the direction to enable is
> specified
> + * with the PHY sub-mode. Transmit is assumed by default with phy_set_mode.
> + */
> +
> +enum phy_mipi_dphy_submode {
> + PHY_MIPI_DPHY_SUBMODE_TX = 0,
> + PHY_MIPI_DPHY_SUBMODE_RX,
> +};
> +
> /**
> * struct phy_configure_opts_mipi_dphy - MIPI D-PHY configuration set
> *
> --
> 2.30.0
>
--
Paul Kocialkowski, Bootlin
Embedded Linux and kernel engineering
https://bootlin.com
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[linux-sunxi] Re: [PATCH v5 00/16] Allwinner MIPI CSI-2 support for A31/V3s/A83T
Hi, On Wed 26 May 21, 14:00, Hans Verkuil wrote: > Hi Paul, > > On 15/01/2021 21:01, Paul Kocialkowski wrote: > > This series introduces support for MIPI CSI-2, with the A31 controller that > > is > > found on most SoCs (A31, V3s and probably V5) as well as the A83T-specific > > controller. While the former uses the same MIPI D-PHY that is already > > supported > > for DSI, the latter embeds its own D-PHY. > > > > In order to distinguish the use of the D-PHY between Rx mode (for MIPI > > CSI-2) > > and Tx mode (for MIPI DSI), a submode is introduced for D-PHY in the PHY > > API. > > This allows adding Rx support in the A31 D-PHY driver. > > > > A few changes and fixes are applied to the A31 CSI controller driver, in > > order > > to support the MIPI CSI-2 use-case. > > Besides the compile error for patch 2/16, I also get several other compile > errors: > > drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c: In function > ‘sun6i_csi_v4l2_fwnode_init’: > ./include/media/v4l2-async.h:207:10: error: expected expression before ‘)’ > token > 207 | ((type *) \ > | ^ > drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c:790:8: note: in expansion > of macro ‘v4l2_async_notifier_add_fwnode_remote_subdev’ > 790 | ret = v4l2_async_notifier_add_fwnode_remote_subdev(>notifier, > |^~~~ > ./include/media/v4l2-async.h:207:10: error: expected expression before ‘)’ > token > 207 | ((type *) \ > | ^ > drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c:811:8: note: in expansion > of macro ‘v4l2_async_notifier_add_fwnode_remote_subdev’ > 811 | ret = v4l2_async_notifier_add_fwnode_remote_subdev(>notifier, > |^~~~ > make[5]: *** [scripts/Makefile.build:272: > drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.o] Error 1 > make[5]: *** Waiting for unfinished jobs > make[4]: *** [scripts/Makefile.build:272: > drivers/media/platform/rockchip/rkisp1/rkisp1-isp.o] Error 1 > make[3]: *** [scripts/Makefile.build:515: > drivers/media/platform/rockchip/rkisp1] Error 2 > make[3]: *** Waiting for unfinished jobs > In file included from ./include/media/v4l2-subdev.h:14, > from ./include/media/v4l2-device.h:13, > from > drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_mipi_csi2.c:19: > drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_mipi_csi2.c: In > function ‘sun8i_a83t_mipi_csi2_v4l2_setup’: > ./include/media/v4l2-async.h:207:10: error: expected expression before ‘)’ > token > 207 | ((type *) \ > | ^ > drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_mipi_csi2.c:495:8: > note: in expansion of macro > ‘v4l2_async_notifier_add_fwnode_remote_subdev’ > 495 | ret = v4l2_async_notifier_add_fwnode_remote_subdev(notifier, handle, > |^~~~ > In file included from ./include/media/v4l2-subdev.h:14, > from ./include/media/v4l2-device.h:13, > from > drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.c:18: > drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.c: In function > ‘sun6i_mipi_csi2_v4l2_setup’: > ./include/media/v4l2-async.h:207:10: error: expected expression before ‘)’ > token > 207 | ((type *) \ > | ^ > drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.c:437:8: note: > in expansion of macro ‘v4l2_async_notifier_add_fwnode_remote_subdev’ > 437 | ret = v4l2_async_notifier_add_fwnode_remote_subdev(notifier, handle, > |^~~~ > > Can you rebase this series? Thanks for letting me know, I'll look into this for the next iteration. > I also need Acked-by's for patches 1-3 from one of the PHY maintainers, but as > you mentioned this might need to change as well. > > Was there a reason why I haven't looked at this before? It's quite an old > series, > usually I don't wait for so long. If it was because I was really slow, then I > apologize and please kick me sooner if you see a review like this take so > long. I'm not sure, but Sakari definitely went over previous interations and made various comments,so the series definitely hasn't gone unreviewed! To be honest I also lost momentum on this but I'll be trying to finalize the series soon, once the discussion on rx/tx handling has concluded. Cheers, Paul > > Regards, > > Hans > > > > > Changes since v4: > > - Added patch to stop using v4l2_async_notifier_pa
[linux-sunxi] Re: [PATCH v5 02/16] phy: Distinguish between Rx and Tx for MIPI D-PHY with submodes
Hi,
On Wed 26 May 21, 13:50, Hans Verkuil wrote:
> On 15/01/2021 21:01, Paul Kocialkowski wrote:
> > As some D-PHY controllers support both Rx and Tx mode, we need a way for
> > users to explicitly request one or the other. For instance, Rx mode can
> > be used along with MIPI CSI-2 while Tx mode can be used with MIPI DSI.
> >
> > Introduce new MIPI D-PHY PHY submodes to use with PHY_MODE_MIPI_DPHY.
> > The default (zero value) is kept to Tx so only the rkisp1 driver, which
> > uses D-PHY in Rx mode, needs to be adapted.
> >
> > Signed-off-by: Paul Kocialkowski
> > Acked-by: Helen Koike
> > ---
> > drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c | 3 ++-
> > include/linux/phy/phy-mipi-dphy.h | 13 +
> > 2 files changed, 15 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c
> > b/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c
> > index 2e5b57e3aedc..cab261644102 100644
> > --- a/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c
> > +++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c
> > @@ -948,7 +948,8 @@ static int rkisp1_mipi_csi2_start(struct rkisp1_isp
> > *isp,
> >
> > phy_mipi_dphy_get_default_config(pixel_clock, isp->sink_fmt->bus_width,
> > sensor->lanes, cfg);
> > - phy_set_mode(sensor->dphy, PHY_MODE_MIPI_DPHY);
> > + phy_set_mode_ext(cdev->dphy, PHY_MODE_MIPI_DPHY,
> > +PHY_MIPI_DPHY_SUBMODE_RX);
>
> drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c: In function
> ‘rkisp1_mipi_csi2_start’:
> drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c:951:19: error: ‘cdev’
> undeclared (first use in this function)
> 951 | phy_set_mode_ext(cdev->dphy, PHY_MODE_MIPI_DPHY,
> | ^~~~
>
> Huh?
Oh wow that's quite shameful. Apologies here.
Note that I'll rebase/respin this series. I also remember that it wasn't very
consensual (on IRC) to use a submode to indicate rx vs tx mode and that
specifying that in the deivce-tree would be a better fit.
Cheers,
Paul
> Regards,
>
> Hans
>
> > phy_configure(sensor->dphy, );
> > phy_power_on(sensor->dphy);
> >
> > diff --git a/include/linux/phy/phy-mipi-dphy.h
> > b/include/linux/phy/phy-mipi-dphy.h
> > index a877ffee845d..0f57ef46a8b5 100644
> > --- a/include/linux/phy/phy-mipi-dphy.h
> > +++ b/include/linux/phy/phy-mipi-dphy.h
> > @@ -6,6 +6,19 @@
> > #ifndef __PHY_MIPI_DPHY_H_
> > #define __PHY_MIPI_DPHY_H_
> >
> > +/**
> > + * enum phy_mipi_dphy_submode - MIPI D-PHY sub-mode
> > + *
> > + * A MIPI D-PHY can be used to transmit or receive data.
> > + * Since some controllers can support both, the direction to enable is
> > specified
> > + * with the PHY sub-mode. Transmit is assumed by default with phy_set_mode.
> > + */
> > +
> > +enum phy_mipi_dphy_submode {
> > + PHY_MIPI_DPHY_SUBMODE_TX = 0,
> > + PHY_MIPI_DPHY_SUBMODE_RX,
> > +};
> > +
> > /**
> > * struct phy_configure_opts_mipi_dphy - MIPI D-PHY configuration set
> > *
> >
>
--
Paul Kocialkowski, Bootlin
Embedded Linux and kernel engineering
https://bootlin.com
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[linux-sunxi] [PATCH v5 16/16] MAINTAINERS: Add entry for the Allwinner A83T MIPI CSI-2 bridge
Add myself as maintainer of the A83T MIPI CSI-2 bridge media driver. Signed-off-by: Paul Kocialkowski --- MAINTAINERS | 8 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index a41c41f6387c..af8095085f0f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -718,6 +718,14 @@ T: git git://linuxtv.org/media_tree.git F: Documentation/devicetree/bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml F: drivers/media/platform/sunxi/sun6i-mipi-csi2/ +ALLWINNER A83T MIPI CSI-2 BRIDGE +M: Paul Kocialkowski +L: linux-me...@vger.kernel.org +S: Maintained +T: git git://linuxtv.org/media_tree.git +F: Documentation/devicetree/bindings/media/allwinner,sun8i-a83t-mipi-csi2.yaml +F: drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/ + ALLWINNER CPUFREQ DRIVER M: Yangtao Li L: linux...@vger.kernel.org -- 2.30.0 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/20210115200141.1397785-17-paul.kocialkowski%40bootlin.com.
[linux-sunxi] [PATCH v5 15/16] ARM: dts: sun8i: a83t: Add MIPI CSI-2 controller node
MIPI CSI-2 is supported on the A83T with a dedicated controller that
covers both the protocol and D-PHY. It can be connected to the CSI
interface as a V4L2 subdev through the fwnode graph.
This is not done by default since connecting the bridge without a
subdev attached to it will cause a failure on the CSI driver.
Signed-off-by: Paul Kocialkowski
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 26 ++
1 file changed, 26 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index c010b27fdb6a..d6d55c12b995 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -1066,6 +1066,32 @@ csi_in: port {
};
};
+ mipi_csi2: csi@1cb1000 {
+ compatible = "allwinner,sun8i-a83t-mipi-csi2";
+ reg = <0x01cb1000 0x1000>;
+ interrupts = ;
+ clocks = < CLK_BUS_CSI>,
+< CLK_CSI_SCLK>,
+< CLK_MIPI_CSI>,
+< CLK_CSI_MISC>;
+ clock-names = "bus", "mod", "mipi", "misc";
+ resets = < RST_BUS_CSI>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mipi_csi2_in: port@0 {
+ reg = <0>;
+ };
+
+ mipi_csi2_out: port@1 {
+ reg = <1>;
+ };
+ };
+ };
+
hdmi: hdmi@1ee {
compatible = "allwinner,sun8i-a83t-dw-hdmi";
reg = <0x01ee 0x1>;
--
2.30.0
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[linux-sunxi] [PATCH v5 14/16] media: sunxi: Add support for the A83T MIPI CSI-2 controller
The A83T supports MIPI CSI-2 with a composite controller, covering both the protocol logic and the D-PHY implementation. This controller seems to be found on the A83T only and probably was abandoned since. This implementation splits the protocol and D-PHY registers and uses the PHY framework internally. The D-PHY is not registered as a standalone PHY driver since it cannot be used with any other controller. There are a few notable points about the controller: - The initialisation sequence involes writing specific magic init values that do not seem to make any particular sense given the concerned register fields; - Interrupts appear to be hitting regardless of the interrupt mask registers, which can cause a serious flood when transmission errors occur. Only 8-bit and 10-bit Bayer formats are currently supported. While up to 4 internal channels to the CSI controller exist, only one is currently supported by this implementation. This work is based on the first version of the driver submitted by Kévin L'hôpital, which was adapted to mainline from the Allwinner BSP. This version integrates MIPI CSI-2 support as a standalone V4L2 subdev instead of merging it in the sun6i-csi driver. It was tested on a Banana Pi M3 board with an OV8865 sensor in a 4-lane configuration. Signed-off-by: Paul Kocialkowski Acked-by: Maxime Ripard --- drivers/media/platform/sunxi/Kconfig | 1 + drivers/media/platform/sunxi/Makefile | 1 + .../sunxi/sun8i-a83t-mipi-csi2/Kconfig| 11 + .../sunxi/sun8i-a83t-mipi-csi2/Makefile | 4 + .../sun8i-a83t-mipi-csi2/sun8i_a83t_dphy.c| 92 +++ .../sun8i-a83t-mipi-csi2/sun8i_a83t_dphy.h| 39 + .../sun8i_a83t_mipi_csi2.c| 666 ++ .../sun8i_a83t_mipi_csi2.h| 197 ++ 8 files changed, 1011 insertions(+) create mode 100644 drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/Kconfig create mode 100644 drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/Makefile create mode 100644 drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_dphy.c create mode 100644 drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_dphy.h create mode 100644 drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_mipi_csi2.c create mode 100644 drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_mipi_csi2.h diff --git a/drivers/media/platform/sunxi/Kconfig b/drivers/media/platform/sunxi/Kconfig index 9684e07454ad..db4c07be7e4c 100644 --- a/drivers/media/platform/sunxi/Kconfig +++ b/drivers/media/platform/sunxi/Kconfig @@ -3,3 +3,4 @@ source "drivers/media/platform/sunxi/sun4i-csi/Kconfig" source "drivers/media/platform/sunxi/sun6i-csi/Kconfig" source "drivers/media/platform/sunxi/sun6i-mipi-csi2/Kconfig" +source "drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/Kconfig" diff --git a/drivers/media/platform/sunxi/Makefile b/drivers/media/platform/sunxi/Makefile index 887a7cae8fca..9aa01cb01883 100644 --- a/drivers/media/platform/sunxi/Makefile +++ b/drivers/media/platform/sunxi/Makefile @@ -3,5 +3,6 @@ obj-y += sun4i-csi/ obj-y += sun6i-csi/ obj-y += sun6i-mipi-csi2/ +obj-y += sun8i-a83t-mipi-csi2/ obj-y += sun8i-di/ obj-y += sun8i-rotate/ diff --git a/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/Kconfig b/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/Kconfig new file mode 100644 index ..60e7a9c41065 --- /dev/null +++ b/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/Kconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-only +config VIDEO_SUN8I_A83T_MIPI_CSI2 + tristate "Allwinner A83T MIPI CSI-2 Controller and D-PHY Driver" + depends on ARCH_SUNXI || COMPILE_TEST + depends on PM && COMMON_CLK && VIDEO_V4L2 + select REGMAP_MMIO + select MEDIA_CONTROLLER + select VIDEO_V4L2_SUBDEV_API + select V4L2_FWNODE + help + Support for the Allwinner A83T MIPI CSI-2 Controller and D-PHY. diff --git a/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/Makefile b/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/Makefile new file mode 100644 index ..1427d15a879a --- /dev/null +++ b/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only +sun8i-a83t-mipi-csi2-y += sun8i_a83t_mipi_csi2.o sun8i_a83t_dphy.o + +obj-$(CONFIG_VIDEO_SUN8I_A83T_MIPI_CSI2) += sun8i-a83t-mipi-csi2.o diff --git a/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_dphy.c b/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_dphy.c new file mode 100644 index ..c380065eb7c9 --- /dev/null +++ b/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_dphy.c @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 Bootlin + * Author: Paul Kocialkowski + */
[linux-sunxi] [PATCH v5 13/16] dt-bindings: media: Add A83T MIPI CSI-2 bindings documentation
This introduces YAML bindings documentation for the A83T MIPI CSI-2
controller.
Signed-off-by: Paul Kocialkowski
Reviewed-by: Rob Herring
---
.../media/allwinner,sun8i-a83t-mipi-csi2.yaml | 147 ++
1 file changed, 147 insertions(+)
create mode 100644
Documentation/devicetree/bindings/media/allwinner,sun8i-a83t-mipi-csi2.yaml
diff --git
a/Documentation/devicetree/bindings/media/allwinner,sun8i-a83t-mipi-csi2.yaml
b/Documentation/devicetree/bindings/media/allwinner,sun8i-a83t-mipi-csi2.yaml
new file mode 100644
index ..e607fae7d85e
--- /dev/null
+++
b/Documentation/devicetree/bindings/media/allwinner,sun8i-a83t-mipi-csi2.yaml
@@ -0,0 +1,147 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/allwinner,sun8i-a83t-mipi-csi2.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Allwinner A83T MIPI CSI-2 Device Tree Bindings
+
+maintainers:
+ - Paul Kocialkowski
+
+properties:
+ compatible:
+const: allwinner,sun8i-a83t-mipi-csi2
+
+ reg:
+maxItems: 1
+
+ interrupts:
+maxItems: 1
+
+ clocks:
+items:
+ - description: Bus Clock
+ - description: Module Clock
+ - description: MIPI-specific Clock
+ - description: Misc CSI Clock
+
+ clock-names:
+items:
+ - const: bus
+ - const: mod
+ - const: mipi
+ - const: misc
+
+ resets:
+maxItems: 1
+
+ # See ./video-interfaces.txt for details
+ ports:
+type: object
+
+properties:
+ port@0:
+type: object
+description: Input port, connect to a MIPI CSI-2 sensor
+
+properties:
+ reg:
+const: 0
+
+ endpoint:
+type: object
+
+properties:
+ remote-endpoint: true
+
+ clock-lanes:
+maxItems: 1
+
+ data-lanes:
+minItems: 1
+maxItems: 4
+
+required:
+ - data-lanes
+ - remote-endpoint
+
+required:
+ - endpoint
+
+additionalProperties: false
+
+ port@1:
+type: object
+description: Output port, connect to a CSI controller
+
+properties:
+ reg:
+const: 1
+
+ endpoint:
+type: object
+
+properties:
+ remote-endpoint: true
+
+required:
+ - remote-endpoint
+
+required:
+ - endpoint
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - resets
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+#include
+#include
+
+mipi_csi2: csi@1cb1000 {
+compatible = "allwinner,sun8i-a83t-mipi-csi2";
+reg = <0x01cb1000 0x1000>;
+interrupts = ;
+clocks = < CLK_BUS_CSI>,
+ < CLK_CSI_SCLK>,
+ < CLK_MIPI_CSI>,
+ < CLK_CSI_MISC>;
+clock-names = "bus", "mod", "mipi", "misc";
+resets = < RST_BUS_CSI>;
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+mipi_csi2_in: port@0 {
+reg = <0>;
+
+mipi_csi2_in_ov8865: endpoint {
+data-lanes = <1 2 3 4>;
+
+remote-endpoint = <_out_mipi_csi2>;
+};
+};
+
+mipi_csi2_out: port@1 {
+reg = <1>;
+
+mipi_csi2_out_csi: endpoint {
+remote-endpoint = <_in_mipi_csi2>;
+};
+};
+};
+};
+
+...
--
2.30.0
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[linux-sunxi] [PATCH v5 12/16] MAINTAINERS: Add entry for the Allwinner A31 MIPI CSI-2 bridge
Add myself as maintainer of the A31 MIPI CSI-2 bridge media driver. Signed-off-by: Paul Kocialkowski --- MAINTAINERS | 8 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 57f9e3047227..a41c41f6387c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -710,6 +710,14 @@ T: git git://linuxtv.org/media_tree.git F: Documentation/devicetree/bindings/media/allwinner,sun4i-a10-csi.yaml F: drivers/media/platform/sunxi/sun4i-csi/ +ALLWINNER A31 MIPI CSI-2 BRIDGE +M: Paul Kocialkowski +L: linux-me...@vger.kernel.org +S: Maintained +T: git git://linuxtv.org/media_tree.git +F: Documentation/devicetree/bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml +F: drivers/media/platform/sunxi/sun6i-mipi-csi2/ + ALLWINNER CPUFREQ DRIVER M: Yangtao Li L: linux...@vger.kernel.org -- 2.30.0 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/20210115200141.1397785-13-paul.kocialkowski%40bootlin.com.
[linux-sunxi] [PATCH v5 11/16] ARM: dts: sun8i: v3s: Add nodes for MIPI CSI-2 support
MIPI CSI-2 is supported on the V3s with an A31-based MIPI CSI-2 bridge
controller. The controller uses a separate D-PHY, which is the same
that is otherwise used for MIPI DSI, but used in Rx mode.
On the V3s, the CSI0 controller is dedicated to MIPI CSI-2 as it does
not have access to any parallel interface pins.
Add all the necessary nodes (CSI0, MIPI CSI-2 bridge and D-PHY) to
support the MIPI CSI-2 interface.
Note that a fwnode graph link is created between CSI0 and MIPI CSI-2
even when no sensor is connected. This will result in a probe failure
for the controller as long as no sensor is connected but this is fine
since no other interface is available.
Signed-off-by: Paul Kocialkowski
---
arch/arm/boot/dts/sun8i-v3s.dtsi | 68
1 file changed, 68 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi
index f8f19d8fa795..7eae0295ba73 100644
--- a/arch/arm/boot/dts/sun8i-v3s.dtsi
+++ b/arch/arm/boot/dts/sun8i-v3s.dtsi
@@ -530,6 +530,31 @@ spi0: spi@1c68000 {
#size-cells = <0>;
};
+ csi0: camera@1cb {
+ compatible = "allwinner,sun8i-v3s-csi";
+ reg = <0x01cb 0x1000>;
+ interrupts = ;
+ clocks = < CLK_BUS_CSI>,
+< CLK_CSI1_SCLK>,
+< CLK_DRAM_CSI>;
+ clock-names = "bus", "mod", "ram";
+ resets = < RST_BUS_CSI>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <1>;
+
+ csi0_in_mipi_csi2: endpoint {
+ remote-endpoint =
<_csi2_out_csi0>;
+ };
+ };
+ };
+ };
+
csi1: camera@1cb4000 {
compatible = "allwinner,sun8i-v3s-csi";
reg = <0x01cb4000 0x3000>;
@@ -552,5 +577,48 @@ gic: interrupt-controller@1c81000 {
#interrupt-cells = <3>;
interrupts = ;
};
+
+ mipi_csi2: csi@1cb1000 {
+ compatible = "allwinner,sun8i-v3s-mipi-csi2",
+"allwinner,sun6i-a31-mipi-csi2";
+ reg = <0x01cb1000 0x1000>;
+ interrupts = ;
+ clocks = < CLK_BUS_CSI>,
+< CLK_CSI1_SCLK>;
+ clock-names = "bus", "mod";
+ resets = < RST_BUS_CSI>;
+ status = "disabled";
+
+ phys = <>;
+ phy-names = "dphy";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mipi_csi2_in: port@0 {
+ reg = <0>;
+ };
+
+ mipi_csi2_out: port@1 {
+ reg = <1>;
+
+ mipi_csi2_out_csi0: endpoint {
+ remote-endpoint =
<_in_mipi_csi2>;
+ };
+ };
+ };
+ };
+
+ dphy: d-phy@1cb2000 {
+ compatible = "allwinner,sun6i-a31-mipi-dphy";
+ reg = <0x01cb2000 0x1000>;
+ clocks = < CLK_BUS_CSI>,
+< CLK_MIPI_CSI>;
+ clock-names = "bus", "mod";
+ resets = < RST_BUS_CSI>;
+ status = "disabled";
+ #phy-cells = <0>;
+ };
};
};
--
2.30.0
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[linux-sunxi] [PATCH v5 10/16] media: sunxi: Add support for the A31 MIPI CSI-2 controller
The A31 MIPI CSI-2 controller is a dedicated MIPI CSI-2 bridge
found on Allwinner SoCs such as the A31 and V3/V3s.
It is a standalone block, connected to the CSI controller on one side
and to the MIPI D-PHY block on the other. It has a dedicated address
space, interrupt line and clock.
It is represented as a V4L2 subdev to the CSI controller and takes a
MIPI CSI-2 sensor as its own subdev, all using the fwnode graph and
media controller API.
Only 8-bit and 10-bit Bayer formats are currently supported.
While up to 4 internal channels to the CSI controller exist, only one
is currently supported by this implementation.
Signed-off-by: Paul Kocialkowski
Acked-by: Maxime Ripard
---
drivers/media/platform/sunxi/Kconfig | 1 +
drivers/media/platform/sunxi/Makefile | 1 +
.../platform/sunxi/sun6i-mipi-csi2/Kconfig| 12 +
.../platform/sunxi/sun6i-mipi-csi2/Makefile | 4 +
.../sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.c | 600 ++
.../sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.h | 117
6 files changed, 735 insertions(+)
create mode 100644 drivers/media/platform/sunxi/sun6i-mipi-csi2/Kconfig
create mode 100644 drivers/media/platform/sunxi/sun6i-mipi-csi2/Makefile
create mode 100644
drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.c
create mode 100644
drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.h
diff --git a/drivers/media/platform/sunxi/Kconfig
b/drivers/media/platform/sunxi/Kconfig
index 7151cc249afa..9684e07454ad 100644
--- a/drivers/media/platform/sunxi/Kconfig
+++ b/drivers/media/platform/sunxi/Kconfig
@@ -2,3 +2,4 @@
source "drivers/media/platform/sunxi/sun4i-csi/Kconfig"
source "drivers/media/platform/sunxi/sun6i-csi/Kconfig"
+source "drivers/media/platform/sunxi/sun6i-mipi-csi2/Kconfig"
diff --git a/drivers/media/platform/sunxi/Makefile
b/drivers/media/platform/sunxi/Makefile
index fc537c9f5ca9..887a7cae8fca 100644
--- a/drivers/media/platform/sunxi/Makefile
+++ b/drivers/media/platform/sunxi/Makefile
@@ -2,5 +2,6 @@
obj-y += sun4i-csi/
obj-y += sun6i-csi/
+obj-y += sun6i-mipi-csi2/
obj-y += sun8i-di/
obj-y += sun8i-rotate/
diff --git a/drivers/media/platform/sunxi/sun6i-mipi-csi2/Kconfig
b/drivers/media/platform/sunxi/sun6i-mipi-csi2/Kconfig
new file mode 100644
index ..47f1bb0779a8
--- /dev/null
+++ b/drivers/media/platform/sunxi/sun6i-mipi-csi2/Kconfig
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-only
+config VIDEO_SUN6I_MIPI_CSI2
+ tristate "Allwinner A31 MIPI CSI-2 Controller Driver"
+ depends on ARCH_SUNXI || COMPILE_TEST
+ depends on PM && COMMON_CLK && VIDEO_V4L2
+ select REGMAP_MMIO
+ select PHY_SUN6I_MIPI_DPHY
+ select MEDIA_CONTROLLER
+ select VIDEO_V4L2_SUBDEV_API
+ select V4L2_FWNODE
+ help
+ Support for the Allwinner A31 MIPI CSI-2 Controller.
diff --git a/drivers/media/platform/sunxi/sun6i-mipi-csi2/Makefile
b/drivers/media/platform/sunxi/sun6i-mipi-csi2/Makefile
new file mode 100644
index ..14e4e03818b5
--- /dev/null
+++ b/drivers/media/platform/sunxi/sun6i-mipi-csi2/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+sun6i-mipi-csi2-y += sun6i_mipi_csi2.o
+
+obj-$(CONFIG_VIDEO_SUN6I_MIPI_CSI2) += sun6i-mipi-csi2.o
diff --git a/drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.c
b/drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.c
new file mode 100644
index ..69186f0c35c2
--- /dev/null
+++ b/drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.c
@@ -0,0 +1,600 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 Bootlin
+ * Author: Paul Kocialkowski
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "sun6i_mipi_csi2.h"
+
+#define MODULE_NAME"sun6i-mipi-csi2"
+
+static const u32 sun6i_mipi_csi2_mbus_codes[] = {
+ MEDIA_BUS_FMT_SBGGR8_1X8,
+ MEDIA_BUS_FMT_SGBRG8_1X8,
+ MEDIA_BUS_FMT_SGRBG8_1X8,
+ MEDIA_BUS_FMT_SRGGB8_1X8,
+ MEDIA_BUS_FMT_SBGGR10_1X10,
+ MEDIA_BUS_FMT_SGBRG10_1X10,
+ MEDIA_BUS_FMT_SGRBG10_1X10,
+ MEDIA_BUS_FMT_SRGGB10_1X10,
+};
+
+/* Video */
+
+static int sun6i_mipi_csi2_s_stream(struct v4l2_subdev *subdev, int on)
+{
+ struct sun6i_mipi_csi2_video *video =
+ sun6i_mipi_csi2_subdev_video(subdev);
+ struct sun6i_mipi_csi2_dev *cdev = sun6i_mipi_csi2_video_dev(video);
+ struct v4l2_subdev *remote_subdev = video->remote_subdev;
+ struct v4l2_fwnode_bus_mipi_csi2 *bus_mipi_csi2 =
+ >endpoint.bus.mipi_csi2;
+ union phy_configure_opts dphy_opts = { 0 };
+ struct phy_configure_opts_mipi_dphy *dphy_cfg = _opts.mipi_dphy;
+ struct regmap *regmap = cdev->regmap;
+
[linux-sunxi] [PATCH v5 09/16] dt-bindings: media: Add A31 MIPI CSI-2 bindings documentation
This introduces YAML bindings documentation for the A31 MIPI CSI-2
controller.
Signed-off-by: Paul Kocialkowski
Reviewed-by: Maxime Ripard
Reviewed-by: Rob Herring
---
.../media/allwinner,sun6i-a31-mipi-csi2.yaml | 156 ++
1 file changed, 156 insertions(+)
create mode 100644
Documentation/devicetree/bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml
diff --git
a/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml
b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml
new file mode 100644
index ..309336b93a87
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml
@@ -0,0 +1,156 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/allwinner,sun6i-a31-mipi-csi2.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Allwinner A31 MIPI CSI-2 Device Tree Bindings
+
+maintainers:
+ - Paul Kocialkowski
+
+properties:
+ compatible:
+oneOf:
+ - const: allwinner,sun6i-a31-mipi-csi2
+ - items:
+ - const: allwinner,sun8i-v3s-mipi-csi2
+ - const: allwinner,sun6i-a31-mipi-csi2
+
+ reg:
+maxItems: 1
+
+ interrupts:
+maxItems: 1
+
+ clocks:
+items:
+ - description: Bus Clock
+ - description: Module Clock
+
+ clock-names:
+items:
+ - const: bus
+ - const: mod
+
+ phys:
+maxItems: 1
+description: MIPI D-PHY
+
+ phy-names:
+items:
+ - const: dphy
+
+ resets:
+maxItems: 1
+
+ # See ./video-interfaces.txt for details
+ ports:
+type: object
+
+properties:
+ port@0:
+type: object
+description: Input port, connect to a MIPI CSI-2 sensor
+
+properties:
+ reg:
+const: 0
+
+ endpoint:
+type: object
+
+properties:
+ remote-endpoint: true
+
+ data-lanes:
+minItems: 1
+maxItems: 4
+
+required:
+ - data-lanes
+ - remote-endpoint
+
+required:
+ - endpoint
+
+additionalProperties: false
+
+ port@1:
+type: object
+description: Output port, connect to a CSI controller
+
+properties:
+ reg:
+const: 1
+
+ endpoint:
+type: object
+
+properties:
+ remote-endpoint: true
+
+required:
+ - remote-endpoint
+
+required:
+ - endpoint
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - phys
+ - phy-names
+ - resets
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+#include
+#include
+
+mipi_csi2: csi@1cb1000 {
+compatible = "allwinner,sun8i-v3s-mipi-csi2",
+ "allwinner,sun6i-a31-mipi-csi2";
+reg = <0x01cb1000 0x1000>;
+interrupts = ;
+clocks = < CLK_BUS_CSI>,
+ < CLK_CSI1_SCLK>;
+clock-names = "bus", "mod";
+resets = < RST_BUS_CSI>;
+
+phys = <>;
+phy-names = "dphy";
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+mipi_csi2_in: port@0 {
+reg = <0>;
+
+mipi_csi2_in_ov5648: endpoint {
+data-lanes = <1 2 3 4>;
+
+remote-endpoint = <_out_mipi_csi2>;
+};
+};
+
+mipi_csi2_out: port@1 {
+reg = <1>;
+
+mipi_csi2_out_csi0: endpoint {
+remote-endpoint = <_in_mipi_csi2>;
+};
+};
+};
+};
+
+...
--
2.30.0
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[linux-sunxi] [PATCH v5 08/16] media: sun6i-csi: Add support for MIPI CSI-2 bridge input
The A31 CSI controller supports a MIPI CSI-2 bridge input, which has
its own dedicated port in the fwnode graph.
Support for this input is added with this change:
- two pads are defined for the media entity instead of one
and only one needs to be connected at a time;
- the pads currently match the fwnode graph representation;
- links are created between our pads and the subdevs for each
interface and are no longer immutable so that userspace can select
which interface to use in case both are bound to a subdev;
- fwnode endpoints are parsed and stored for each interface;
- the active subdev (and fwnode endpoint) is retrieved when validating
the media link at stream on time and cleared at stream off;
- an error is raised if both links are active at the same time;
- the MIPI interface bit is set if the MIPI CSI-2 bridge endpoint is
active.
In the future, the media entity representation might evolve to:
- distinguish the internal parallel bridge and data formatter;
- represent each of the 4 internal channels that can exist between
the parallel bridge (for BT656 time-multiplex) and MIPI CSI-2
(internal channels can be mapped to virtual channels);
- connect the controller's output to the ISP instead of its
DMA engine.
Finally note that the MIPI CSI-2 bridges should not be linked in
the fwnode graph unless they have a sensor subdev attached.
Signed-off-by: Paul Kocialkowski
Acked-by: Maxime Ripard
---
.../platform/sunxi/sun6i-csi/sun6i_csi.c | 111 +++---
.../platform/sunxi/sun6i-csi/sun6i_csi.h | 9 +-
.../platform/sunxi/sun6i-csi/sun6i_video.c| 57 +
.../platform/sunxi/sun6i-csi/sun6i_video.h| 7 +-
4 files changed, 137 insertions(+), 47 deletions(-)
diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
index d06028f42534..55cac91f8282 100644
--- a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
+++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
@@ -49,6 +49,7 @@ static inline struct sun6i_csi_dev *sun6i_csi_to_dev(struct
sun6i_csi *csi)
/* TODO add 10&12 bit YUV, RGB support */
bool sun6i_csi_is_format_supported(struct sun6i_csi *csi,
+ struct v4l2_fwnode_endpoint *endpoint,
u32 pixformat, u32 mbus_code)
{
struct sun6i_csi_dev *sdev = sun6i_csi_to_dev(csi);
@@ -58,9 +59,9 @@ bool sun6i_csi_is_format_supported(struct sun6i_csi *csi,
* 8bit and 16bit bus width.
* Identify the media bus format from device tree.
*/
- if ((sdev->csi.v4l2_ep.bus_type == V4L2_MBUS_PARALLEL
-|| sdev->csi.v4l2_ep.bus_type == V4L2_MBUS_BT656)
-&& sdev->csi.v4l2_ep.bus.parallel.bus_width == 16) {
+ if ((endpoint->bus_type == V4L2_MBUS_PARALLEL ||
+endpoint->bus_type == V4L2_MBUS_BT656) &&
+ endpoint->bus.parallel.bus_width == 16) {
switch (pixformat) {
case V4L2_PIX_FMT_HM12:
case V4L2_PIX_FMT_NV12:
@@ -373,7 +374,7 @@ static enum csi_input_seq get_csi_input_seq(struct
sun6i_csi_dev *sdev,
static void sun6i_csi_setup_bus(struct sun6i_csi_dev *sdev)
{
- struct v4l2_fwnode_endpoint *endpoint = >csi.v4l2_ep;
+ struct v4l2_fwnode_endpoint *endpoint = sdev->csi.video.source_endpoint;
struct sun6i_csi *csi = >csi;
unsigned char bus_width;
u32 flags;
@@ -459,6 +460,9 @@ static void sun6i_csi_setup_bus(struct sun6i_csi_dev *sdev)
if (flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
cfg |= CSI_IF_CFG_CLK_POL_FALLING_EDGE;
break;
+ case V4L2_MBUS_CSI2_DPHY:
+ cfg |= CSI_IF_CFG_MIPI_IF_MIPI;
+ break;
default:
dev_warn(sdev->dev, "Unsupported bus type: %d\n",
endpoint->bus_type);
@@ -636,11 +640,11 @@ void sun6i_csi_set_stream(struct sun6i_csi *csi, bool
enable)
* Media Controller and V4L2
*/
static int sun6i_csi_link_entity(struct sun6i_csi *csi,
+struct media_pad *sink_pad,
struct media_entity *entity,
-struct fwnode_handle *fwnode)
+struct fwnode_handle *fwnode, bool enabled)
{
struct media_entity *sink;
- struct media_pad *sink_pad;
int src_pad_index;
int ret;
@@ -654,14 +658,12 @@ static int sun6i_csi_link_entity(struct sun6i_csi *csi,
src_pad_index = ret;
sink = >video.vdev.entity;
- sink_pad = >video.pad;
dev_dbg(csi->dev, "creating %s:%u -> %s:%u link\n",
entity->name, src_pad_index, sink->name, sink_pad->index);
ret = media_create_pad_link(entity, src_pad_index, sink,
[linux-sunxi] [PATCH v5 07/16] dt-bindings: media: sun6i-a31-csi: Add MIPI CSI-2 input port
The A31 CSI controller supports two distinct input interfaces:
parallel and an external MIPI CSI-2 bridge. The parallel interface
is often connected to a set of hardware pins while the MIPI CSI-2
bridge is an internal FIFO-ish link. As a result, these two inputs
are distinguished as two different ports.
Note that only one of the two may be present on a controller instance.
For example, the V3s has one controller dedicated to MIPI-CSI2 and one
dedicated to parallel.
Update the binding with an explicit ports node that holds two distinct
port nodes: one for parallel input and one for MIPI CSI-2.
This is backward-compatible with the single-port approach that was
previously taken for representing the parallel interface port, which
stays enumerated as fwnode port 0.
Note that additional ports may be added in the future, especially to
support feeding the CSI controller's output to the ISP.
Signed-off-by: Paul Kocialkowski
Reviewed-by: Rob Herring
Acked-by: Maxime Ripard
---
.../media/allwinner,sun6i-a31-csi.yaml| 88 ---
1 file changed, 75 insertions(+), 13 deletions(-)
diff --git
a/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-csi.yaml
b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-csi.yaml
index 1fd9b5532a21..77ded77505e9 100644
--- a/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-csi.yaml
+++ b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-csi.yaml
@@ -67,6 +67,62 @@ properties:
additionalProperties: false
+ ports:
+type: object
+
+properties:
+ port@0:
+type: object
+description: Parallel input port, connect to a parallel sensor
+
+properties:
+ reg:
+const: 0
+
+ endpoint:
+type: object
+
+properties:
+ remote-endpoint: true
+
+ bus-width:
+enum: [ 8, 10, 12, 16 ]
+
+ pclk-sample: true
+ hsync-active: true
+ vsync-active: true
+
+required:
+ - bus-width
+ - remote-endpoint
+
+required:
+ - endpoint
+
+additionalProperties: false
+
+ port@1:
+type: object
+description: MIPI CSI-2 bridge input port
+
+properties:
+ reg:
+const: 1
+
+ endpoint:
+type: object
+
+properties:
+ remote-endpoint: true
+
+required:
+ - remote-endpoint
+
+required:
+ - endpoint
+
+additionalProperties: false
+
required:
- compatible
- reg
@@ -95,19 +151,25 @@ examples:
"ram";
resets = < RST_BUS_CSI>;
-port {
-/* Parallel bus endpoint */
-csi1_ep: endpoint {
-remote-endpoint = <_ep>;
-bus-width = <16>;
-
-/*
- * If hsync-active/vsync-active are missing,
- * embedded BT.656 sync is used.
- */
- hsync-active = <0>; /* Active low */
- vsync-active = <0>; /* Active low */
- pclk-sample = <1>; /* Rising */
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+port@0 {
+reg = <0>;
+/* Parallel bus endpoint */
+csi1_ep: endpoint {
+remote-endpoint = <_ep>;
+bus-width = <16>;
+
+/*
+ * If hsync-active/vsync-active are missing,
+ * embedded BT.656 sync is used.
+ */
+ hsync-active = <0>; /* Active low */
+ vsync-active = <0>; /* Active low */
+ pclk-sample = <1>; /* Rising */
+};
};
};
};
--
2.30.0
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[linux-sunxi] [PATCH v5 06/16] media: sun6i-csi: Only configure the interface data width for parallel
Bits related to the interface data width are only applicable to the
parallel interface and are irrelevant when the CSI controller is taking
input from the MIPI CSI-2 controller.
In prevision of adding support for this case, set these bits
conditionally so there is no ambiguity. The conditional block is
moved around before the interlaced conditional block for nicer code
symmetry (conditional blocks first) while at it.
Co-developed-by: Kévin L'hôpital
Signed-off-by: Kévin L'hôpital
Signed-off-by: Paul Kocialkowski
Acked-by: Maxime Ripard
---
.../platform/sunxi/sun6i-csi/sun6i_csi.c | 42 +++
1 file changed, 25 insertions(+), 17 deletions(-)
diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
index 1a11a6174a17..d06028f42534 100644
--- a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
+++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
@@ -378,8 +378,13 @@ static void sun6i_csi_setup_bus(struct sun6i_csi_dev *sdev)
unsigned char bus_width;
u32 flags;
u32 cfg;
+ bool input_parallel = false;
bool input_interlaced = false;
+ if (endpoint->bus_type == V4L2_MBUS_PARALLEL ||
+ endpoint->bus_type == V4L2_MBUS_BT656)
+ input_parallel = true;
+
if (csi->config.field == V4L2_FIELD_INTERLACED
|| csi->config.field == V4L2_FIELD_INTERLACED_TB
|| csi->config.field == V4L2_FIELD_INTERLACED_BT)
@@ -395,6 +400,26 @@ static void sun6i_csi_setup_bus(struct sun6i_csi_dev *sdev)
CSI_IF_CFG_HREF_POL_MASK | CSI_IF_CFG_FIELD_MASK |
CSI_IF_CFG_SRC_TYPE_MASK);
+ if (input_parallel) {
+ switch (bus_width) {
+ case 8:
+ cfg |= CSI_IF_CFG_IF_DATA_WIDTH_8BIT;
+ break;
+ case 10:
+ cfg |= CSI_IF_CFG_IF_DATA_WIDTH_10BIT;
+ break;
+ case 12:
+ cfg |= CSI_IF_CFG_IF_DATA_WIDTH_12BIT;
+ break;
+ case 16: /* No need to configure DATA_WIDTH for 16bit */
+ break;
+ default:
+ dev_warn(sdev->dev, "Unsupported bus width: %u\n",
+bus_width);
+ break;
+ }
+ }
+
if (input_interlaced)
cfg |= CSI_IF_CFG_SRC_TYPE_INTERLACED;
else
@@ -440,23 +465,6 @@ static void sun6i_csi_setup_bus(struct sun6i_csi_dev *sdev)
break;
}
- switch (bus_width) {
- case 8:
- cfg |= CSI_IF_CFG_IF_DATA_WIDTH_8BIT;
- break;
- case 10:
- cfg |= CSI_IF_CFG_IF_DATA_WIDTH_10BIT;
- break;
- case 12:
- cfg |= CSI_IF_CFG_IF_DATA_WIDTH_12BIT;
- break;
- case 16: /* No need to configure DATA_WIDTH for 16bit */
- break;
- default:
- dev_warn(sdev->dev, "Unsupported bus width: %u\n", bus_width);
- break;
- }
-
regmap_write(sdev->regmap, CSI_IF_CFG_REG, cfg);
}
--
2.30.0
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[linux-sunxi] [PATCH v5 05/16] media: sun6i-csi: Use common V4L2 format info for storage bpp
V4L2 has a common helper which can be used for calculating the number
of stored bits per pixels of a given (stored) image format.
Use the helper-returned structure instead of our own switch/case list.
Note that a few formats are not in that list so we keep them as
special cases.
The custom switch/case was also wrong concerning 10/12-bit Bayer
formats, which are aligned to 16 bits in memory. Using the common
helper fixes it.
Fixes: 5cc7522d8965 ("media: sun6i: Add support for Allwinner CSI V3s")
Signed-off-by: Paul Kocialkowski
Acked-by: Maxime Ripard
---
.../platform/sunxi/sun6i-csi/sun6i_csi.h | 55 +++
1 file changed, 20 insertions(+), 35 deletions(-)
diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.h
b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.h
index 7f3389c70794..7cd23cd74685 100644
--- a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.h
+++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.h
@@ -87,53 +87,38 @@ void sun6i_csi_update_buf_addr(struct sun6i_csi *csi,
dma_addr_t addr);
*/
void sun6i_csi_set_stream(struct sun6i_csi *csi, bool enable);
-/* get bpp form v4l2 pixformat */
+/* get memory storage bpp from v4l2 pixformat */
static inline int sun6i_csi_get_bpp(unsigned int pixformat)
{
+ const struct v4l2_format_info *info;
+ unsigned int i;
+ int bpp = 0;
+
+ /* Handle special cases unknown to V4L2 format info first. */
switch (pixformat) {
- case V4L2_PIX_FMT_SBGGR8:
- case V4L2_PIX_FMT_SGBRG8:
- case V4L2_PIX_FMT_SGRBG8:
- case V4L2_PIX_FMT_SRGGB8:
case V4L2_PIX_FMT_JPEG:
return 8;
- case V4L2_PIX_FMT_SBGGR10:
- case V4L2_PIX_FMT_SGBRG10:
- case V4L2_PIX_FMT_SGRBG10:
- case V4L2_PIX_FMT_SRGGB10:
- return 10;
- case V4L2_PIX_FMT_SBGGR12:
- case V4L2_PIX_FMT_SGBRG12:
- case V4L2_PIX_FMT_SGRBG12:
- case V4L2_PIX_FMT_SRGGB12:
case V4L2_PIX_FMT_HM12:
- case V4L2_PIX_FMT_NV12:
- case V4L2_PIX_FMT_NV21:
- case V4L2_PIX_FMT_YUV420:
- case V4L2_PIX_FMT_YVU420:
return 12;
- case V4L2_PIX_FMT_YUYV:
- case V4L2_PIX_FMT_YVYU:
- case V4L2_PIX_FMT_UYVY:
- case V4L2_PIX_FMT_VYUY:
- case V4L2_PIX_FMT_NV16:
- case V4L2_PIX_FMT_NV61:
- case V4L2_PIX_FMT_YUV422P:
- case V4L2_PIX_FMT_RGB565:
case V4L2_PIX_FMT_RGB565X:
return 16;
- case V4L2_PIX_FMT_RGB24:
- case V4L2_PIX_FMT_BGR24:
- return 24;
- case V4L2_PIX_FMT_RGB32:
- case V4L2_PIX_FMT_BGR32:
- return 32;
- default:
+ }
+
+ info = v4l2_format_info(pixformat);
+ if (!info) {
WARN(1, "Unsupported pixformat: 0x%x\n", pixformat);
- break;
+ return 0;
+ }
+
+ for (i = 0; i < info->comp_planes; i++) {
+ unsigned int hdiv = (i == 0) ? 1 : info->hdiv;
+ unsigned int vdiv = (i == 0) ? 1 : info->vdiv;
+
+ /* We return bits per pixel while V4L2 format info is bytes. */
+ bpp += 8 * info->bpp[i] / hdiv / vdiv;
}
- return 0;
+ return bpp;
}
#endif /* __SUN6I_CSI_H__ */
--
2.30.0
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[linux-sunxi] [PATCH v5 04/16] media: sun6i-csi: Stop using the deprecated fwnode endpoint parser
The v4l2_async_notifier_parse_fwnode_endpoints helper is getting
deprecated in favor of explicit parsing of the endpoints.
Implement it instead of using this deprecated function.
Since this was the last user of the helper, it should now be safe to
remove.
Signed-off-by: Paul Kocialkowski
---
.../platform/sunxi/sun6i-csi/sun6i_csi.c | 69 ---
.../platform/sunxi/sun6i-csi/sun6i_csi.h | 1 +
2 files changed, 44 insertions(+), 26 deletions(-)
diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
index c3b2f27b99d2..1a11a6174a17 100644
--- a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
+++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
@@ -693,28 +693,6 @@ static const struct v4l2_async_notifier_operations
sun6i_csi_async_ops = {
.complete = sun6i_subdev_notify_complete,
};
-static int sun6i_csi_fwnode_parse(struct device *dev,
- struct v4l2_fwnode_endpoint *vep,
- struct v4l2_async_subdev *asd)
-{
- struct sun6i_csi *csi = dev_get_drvdata(dev);
-
- if (vep->base.port || vep->base.id) {
- dev_warn(dev, "Only support a single port with one endpoint\n");
- return -ENOTCONN;
- }
-
- switch (vep->bus_type) {
- case V4L2_MBUS_PARALLEL:
- case V4L2_MBUS_BT656:
- csi->v4l2_ep = *vep;
- return 0;
- default:
- dev_err(dev, "Unsupported media bus type\n");
- return -ENOTCONN;
- }
-}
-
static void sun6i_csi_v4l2_cleanup(struct sun6i_csi *csi)
{
media_device_unregister(>media_dev);
@@ -726,6 +704,48 @@ static void sun6i_csi_v4l2_cleanup(struct sun6i_csi *csi)
media_device_cleanup(>media_dev);
}
+static int sun6i_csi_v4l2_fwnode_init(struct sun6i_csi *csi)
+{
+ struct v4l2_fwnode_endpoint *endpoint = NULL;
+ struct fwnode_handle *handle = NULL;
+ int ret;
+
+ /* Parallel */
+
+ endpoint = >v4l2_ep;
+ handle = fwnode_graph_get_endpoint_by_id(dev_fwnode(csi->dev), 0, 0,
+FWNODE_GRAPH_ENDPOINT_NEXT);
+ if (!handle)
+ return 0;
+
+ ret = v4l2_fwnode_endpoint_parse(handle, endpoint);
+ if (ret)
+ goto error;
+
+ if (endpoint->bus_type != V4L2_MBUS_PARALLEL &&
+ endpoint->bus_type != V4L2_MBUS_BT656) {
+ dev_err(csi->dev, "Unsupported parallel media bus type\n");
+ ret = -ENOTCONN;
+ goto error;
+ }
+
+ ret = v4l2_async_notifier_add_fwnode_remote_subdev(>notifier,
+ handle,
+ >subdev);
+ if (ret)
+ goto error;
+
+ fwnode_handle_put(handle);
+
+ return 0;
+
+error:
+ if (handle)
+ fwnode_handle_put(handle);
+
+ return ret;
+}
+
static int sun6i_csi_v4l2_init(struct sun6i_csi *csi)
{
int ret;
@@ -760,10 +780,7 @@ static int sun6i_csi_v4l2_init(struct sun6i_csi *csi)
if (ret)
goto unreg_v4l2;
- ret = v4l2_async_notifier_parse_fwnode_endpoints(csi->dev,
->notifier,
-sizeof(struct
v4l2_async_subdev),
-
sun6i_csi_fwnode_parse);
+ ret = sun6i_csi_v4l2_fwnode_init(csi);
if (ret)
goto clean_video;
diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.h
b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.h
index c626821aaedb..7f3389c70794 100644
--- a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.h
+++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.h
@@ -38,6 +38,7 @@ struct sun6i_csi {
struct v4l2_device v4l2_dev;
struct media_device media_dev;
+ struct v4l2_async_subdevsubdev;
struct v4l2_async_notifier notifier;
/* video port settings */
--
2.30.0
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[linux-sunxi] [PATCH v5 03/16] phy: allwinner: phy-sun6i-mipi-dphy: Support D-PHY Rx mode for MIPI CSI-2
The Allwinner A31 D-PHY supports both Rx and Tx modes. While the latter
is already supported and used for MIPI DSI this adds support for the
former, to be used with MIPI CSI-2.
This implementation is inspired by Allwinner's V3s Linux SDK
implementation, which was used as a documentation base.
Signed-off-by: Paul Kocialkowski
Acked-by: Maxime Ripard
---
drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 164 +++-
1 file changed, 160 insertions(+), 4 deletions(-)
diff --git a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
index f0bc87d654d4..326383e72528 100644
--- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
+++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
@@ -24,6 +24,14 @@
#define SUN6I_DPHY_TX_CTL_REG 0x04
#define SUN6I_DPHY_TX_CTL_HS_TX_CLK_CONT BIT(28)
+#define SUN6I_DPHY_RX_CTL_REG 0x08
+#define SUN6I_DPHY_RX_CTL_EN_DBC BIT(31)
+#define SUN6I_DPHY_RX_CTL_RX_CLK_FORCE BIT(24)
+#define SUN6I_DPHY_RX_CTL_RX_D3_FORCE BIT(23)
+#define SUN6I_DPHY_RX_CTL_RX_D2_FORCE BIT(22)
+#define SUN6I_DPHY_RX_CTL_RX_D1_FORCE BIT(21)
+#define SUN6I_DPHY_RX_CTL_RX_D0_FORCE BIT(20)
+
#define SUN6I_DPHY_TX_TIME0_REG0x10
#define SUN6I_DPHY_TX_TIME0_HS_TRAIL(n)(((n) & 0xff) << 24)
#define SUN6I_DPHY_TX_TIME0_HS_PREPARE(n) (((n) & 0xff) << 16)
@@ -44,12 +52,29 @@
#define SUN6I_DPHY_TX_TIME4_HS_TX_ANA1(n) (((n) & 0xff) << 8)
#define SUN6I_DPHY_TX_TIME4_HS_TX_ANA0(n) ((n) & 0xff)
+#define SUN6I_DPHY_RX_TIME0_REG0x30
+#define SUN6I_DPHY_RX_TIME0_HS_RX_SYNC(n) (((n) & 0xff) << 24)
+#define SUN6I_DPHY_RX_TIME0_HS_RX_CLK_MISS(n) (((n) & 0xff) << 16)
+#define SUN6I_DPHY_RX_TIME0_LP_RX(n) (((n) & 0xff) << 8)
+
+#define SUN6I_DPHY_RX_TIME1_REG0x34
+#define SUN6I_DPHY_RX_TIME1_RX_DLY(n) (((n) & 0xfff) << 20)
+#define SUN6I_DPHY_RX_TIME1_LP_RX_ULPS_WP(n) ((n) & 0xf)
+
+#define SUN6I_DPHY_RX_TIME2_REG0x38
+#define SUN6I_DPHY_RX_TIME2_HS_RX_ANA1(n) (((n) & 0xff) << 8)
+#define SUN6I_DPHY_RX_TIME2_HS_RX_ANA0(n) ((n) & 0xff)
+
+#define SUN6I_DPHY_RX_TIME3_REG0x40
+#define SUN6I_DPHY_RX_TIME3_LPRST_DLY(n) (((n) & 0x) << 16)
+
#define SUN6I_DPHY_ANA0_REG0x4c
#define SUN6I_DPHY_ANA0_REG_PWSBIT(31)
#define SUN6I_DPHY_ANA0_REG_DMPC BIT(28)
#define SUN6I_DPHY_ANA0_REG_DMPD(n)(((n) & 0xf) << 24)
#define SUN6I_DPHY_ANA0_REG_SLV(n) (((n) & 7) << 12)
#define SUN6I_DPHY_ANA0_REG_DEN(n) (((n) & 0xf) << 8)
+#define SUN6I_DPHY_ANA0_REG_SFB(n) (((n) & 3) << 2)
#define SUN6I_DPHY_ANA1_REG0x50
#define SUN6I_DPHY_ANA1_REG_VTTMODEBIT(31)
@@ -92,6 +117,8 @@ struct sun6i_dphy {
struct phy *phy;
struct phy_configure_opts_mipi_dphy config;
+
+ int submode;
};
static int sun6i_dphy_init(struct phy *phy)
@@ -105,6 +132,18 @@ static int sun6i_dphy_init(struct phy *phy)
return 0;
}
+static int sun6i_dphy_set_mode(struct phy *phy, enum phy_mode mode, int
submode)
+{
+ struct sun6i_dphy *dphy = phy_get_drvdata(phy);
+
+ if (mode != PHY_MODE_MIPI_DPHY)
+ return -EINVAL;
+
+ dphy->submode = submode;
+
+ return 0;
+}
+
static int sun6i_dphy_configure(struct phy *phy, union phy_configure_opts
*opts)
{
struct sun6i_dphy *dphy = phy_get_drvdata(phy);
@@ -119,9 +158,8 @@ static int sun6i_dphy_configure(struct phy *phy, union
phy_configure_opts *opts)
return 0;
}
-static int sun6i_dphy_power_on(struct phy *phy)
+static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy)
{
- struct sun6i_dphy *dphy = phy_get_drvdata(phy);
u8 lanes_mask = GENMASK(dphy->config.lanes - 1, 0);
regmap_write(dphy->regs, SUN6I_DPHY_TX_CTL_REG,
@@ -211,12 +249,129 @@ static int sun6i_dphy_power_on(struct phy *phy)
return 0;
}
+static int sun6i_dphy_rx_power_on(struct sun6i_dphy *dphy)
+{
+ /* Physical clock rate is actually half of symbol rate with DDR. */
+ unsigned long mipi_symbol_rate = dphy->config.hs_clk_rate;
+ unsigned long dphy_clk_rate;
+ unsigned int rx_dly;
+ unsigned int lprst_dly;
+ u32 value;
+
+ dphy_clk_rate = clk_get_rate(dphy->mod_clk);
+ if (!dphy_clk_rate)
+ return -EINVAL;
+
+ /* Hardcoded timing parameters from the Allwinner BSP. */
+ regmap_write(dphy->regs, SUN6I_DPHY_RX_TIME0_REG,
+SUN6I_DPHY_RX_TIME0_HS_RX_SYNC(255) |
+SUN6I_DPHY_RX_TIME0_HS_RX_CLK_MISS(255) |
+SUN6I
[linux-sunxi] [PATCH v5 02/16] phy: Distinguish between Rx and Tx for MIPI D-PHY with submodes
As some D-PHY controllers support both Rx and Tx mode, we need a way for
users to explicitly request one or the other. For instance, Rx mode can
be used along with MIPI CSI-2 while Tx mode can be used with MIPI DSI.
Introduce new MIPI D-PHY PHY submodes to use with PHY_MODE_MIPI_DPHY.
The default (zero value) is kept to Tx so only the rkisp1 driver, which
uses D-PHY in Rx mode, needs to be adapted.
Signed-off-by: Paul Kocialkowski
Acked-by: Helen Koike
---
drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c | 3 ++-
include/linux/phy/phy-mipi-dphy.h | 13 +
2 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c
b/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c
index 2e5b57e3aedc..cab261644102 100644
--- a/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c
+++ b/drivers/media/platform/rockchip/rkisp1/rkisp1-isp.c
@@ -948,7 +948,8 @@ static int rkisp1_mipi_csi2_start(struct rkisp1_isp *isp,
phy_mipi_dphy_get_default_config(pixel_clock, isp->sink_fmt->bus_width,
sensor->lanes, cfg);
- phy_set_mode(sensor->dphy, PHY_MODE_MIPI_DPHY);
+ phy_set_mode_ext(cdev->dphy, PHY_MODE_MIPI_DPHY,
+PHY_MIPI_DPHY_SUBMODE_RX);
phy_configure(sensor->dphy, );
phy_power_on(sensor->dphy);
diff --git a/include/linux/phy/phy-mipi-dphy.h
b/include/linux/phy/phy-mipi-dphy.h
index a877ffee845d..0f57ef46a8b5 100644
--- a/include/linux/phy/phy-mipi-dphy.h
+++ b/include/linux/phy/phy-mipi-dphy.h
@@ -6,6 +6,19 @@
#ifndef __PHY_MIPI_DPHY_H_
#define __PHY_MIPI_DPHY_H_
+/**
+ * enum phy_mipi_dphy_submode - MIPI D-PHY sub-mode
+ *
+ * A MIPI D-PHY can be used to transmit or receive data.
+ * Since some controllers can support both, the direction to enable is
specified
+ * with the PHY sub-mode. Transmit is assumed by default with phy_set_mode.
+ */
+
+enum phy_mipi_dphy_submode {
+ PHY_MIPI_DPHY_SUBMODE_TX = 0,
+ PHY_MIPI_DPHY_SUBMODE_RX,
+};
+
/**
* struct phy_configure_opts_mipi_dphy - MIPI D-PHY configuration set
*
--
2.30.0
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[linux-sunxi] [PATCH v5 01/16] docs: phy: Add a part about PHY mode and submode
Besides giving pointers to the relevant functions for PHY mode and submode configuration, this clarifies the need to set them before powering on the PHY. Signed-off-by: Paul Kocialkowski Reviewed-by: Maxime Ripard --- Documentation/driver-api/phy/phy.rst | 18 ++ 1 file changed, 18 insertions(+) diff --git a/Documentation/driver-api/phy/phy.rst b/Documentation/driver-api/phy/phy.rst index 8fc1ce0bb905..6cbc72707a49 100644 --- a/Documentation/driver-api/phy/phy.rst +++ b/Documentation/driver-api/phy/phy.rst @@ -195,3 +195,21 @@ DeviceTree Binding The documentation for PHY dt binding can be found @ Documentation/devicetree/bindings/phy/phy-bindings.txt + +PHY Mode and Submode + + +Once a reference to a PHY is obtained by a controller, the PHY can be configured +to a PHY mode and submode. PHY modes are described in the `phy_mode` enum while +submodes are specific to the selected PHY mode. + +Mode and submode configuration is done by calling:: + + int phy_set_mode_ext(struct phy *phy, enum phy_mode mode, int submode); + +If no submode is to be configured, users can call:: + + int phy_set_mode(struct phy *phy, enum phy_mode mode); + +The PHY mode and submode must not be configured after the PHY has already been +powered on. -- 2.30.0 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/20210115200141.1397785-2-paul.kocialkowski%40bootlin.com.
[linux-sunxi] [PATCH v5 00/16] Allwinner MIPI CSI-2 support for A31/V3s/A83T
ling: OK Codec ioctls (Input 0): test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported) test VIDIOC_G_ENC_INDEX: OK (Not Supported) test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported) Buffer ioctls (Input 0): test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK fail: v4l2-test-buffers.cpp(755): q.export_bufs(node, q.g_type()) test VIDIOC_EXPBUF: FAIL test Requests: OK (Not Supported) Total for sun6i-video device /dev/video0: 45, Succeeded: 44, Failed: 1, Warnings: 1 # sun6i-csi + sun8i-a83t-mipi-csi2 + ov8865 v4l2-compliance SHA: not available, 32 bits Compliance test for sun6i-video device /dev/video0: Driver Info: Driver name : sun6i-video Card type: sun6i-csi Bus info : platform:camera Driver version : 5.10.0 Capabilities : 0x8421 Video Capture Streaming Extended Pix Format Device Capabilities Device Caps : 0x0421 Video Capture Streaming Extended Pix Format Media Driver Info: Driver name : sun6i-csi Model: Allwinner Video Capture Device Serial : Bus info : platform:1cb.camera Media version: 5.10.0 Hardware revision: 0x (0) Driver version : 5.10.0 Interface Info: ID : 0x0304 Type : V4L Video Entity Info: ID : 0x0001 (1) Name : sun6i-csi Function : V4L2 I/O Pad 0x0102 : 0: Sink Pad 0x0103 : 1: Sink Link 0x020d: from remote pad 0x108 of entity 'sun8i-a83t-mipi-csi2': Data, Enabled Required ioctls: test MC information (see 'Media Driver Info' above): OK warn: v4l2-compliance.cpp(633): media bus_info 'platform:1cb.camera' differs from V4L2 bus_info 'platform:camera' test VIDIOC_QUERYCAP: OK Allow for multiple opens: test second /dev/video0 open: OK warn: v4l2-compliance.cpp(633): media bus_info 'platform:1cb.camera' differs from V4L2 bus_info 'platform:camera' test VIDIOC_QUERYCAP: OK test VIDIOC_G/S_PRIORITY: OK test for unlimited opens: OK Debug ioctls: test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported) test VIDIOC_LOG_STATUS: OK Input ioctls: test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported) test VIDIOC_G/S_FREQUENCY: OK (Not Supported) test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported) test VIDIOC_ENUMAUDIO: OK (Not Supported) test VIDIOC_G/S/ENUMINPUT: OK test VIDIOC_G/S_AUDIO: OK (Not Supported) Inputs: 1 Audio Inputs: 0 Tuners: 0 Output ioctls: test VIDIOC_G/S_MODULATOR: OK (Not Supported) test VIDIOC_G/S_FREQUENCY: OK (Not Supported) test VIDIOC_ENUMAUDOUT: OK (Not Supported) test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported) test VIDIOC_G/S_AUDOUT: OK (Not Supported) Outputs: 0 Audio Outputs: 0 Modulators: 0 Input/Output configuration ioctls: test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported) test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported) test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported) test VIDIOC_G/S_EDID: OK (Not Supported) Control ioctls (Input 0): warn: v4l2-test-controls.cpp(92): Exposure: (max - min) % step != 0 warn: v4l2-test-controls.cpp(92): Gain: (max - min) % step != 0 warn: v4l2-test-controls.cpp(92): Exposure: (max - min) % step != 0 warn: v4l2-test-controls.cpp(92): Gain: (max - min) % step != 0 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK test VIDIOC_QUERYCTRL: OK test VIDIOC_G/S_CTRL: OK test VIDIOC_G/S/TRY_EXT_CTRLS: OK test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK test VIDIOC_G/S_JPEGCOMP: OK (Not Supported) Standard Controls: 11 Private Controls: 0 Format ioctls (Input 0): test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK test VIDIOC_G/S_PARM: OK (Not Supported) test VIDIOC_G_FBUF: OK (Not Supported) test VIDIOC_G_FMT: OK test VIDIOC_TRY_FMT: OK test VIDIOC_S_FMT: OK test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported) test Cropping: OK (Not Supported) test Composing: OK (Not Supported) test Scaling: OK Codec ioctls (Input 0): test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported) test VIDIOC_G_ENC_INDEX: OK (Not Supported) test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported) Buffer ioctls (Input 0): test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK test VIDIOC_EXPBUF: OK test Requests: OK (Not Supported) Total for sun6i-video device /dev/video0: 45, Succeeded: 45, Failed: 0, Warnings: 6
Re: [linux-sunxi] [PATCH v4 09/15] media: sunxi: Add support for the A31 MIPI CSI-2 controller
Hey Ezequiel,
On Mon 11 Jan 21, 15:21, Ezequiel Garcia wrote:
> Salut Paul,
>
> Just a minor comment about the v4l2 async API.
>
> On Thu, 31 Dec 2020 at 11:30, Paul Kocialkowski
> wrote:
> >
> > The A31 MIPI CSI-2 controller is a dedicated MIPI CSI-2 bridge
> > found on Allwinner SoCs such as the A31 and V3/V3s.
> >
> > It is a standalone block, connected to the CSI controller on one side
> > and to the MIPI D-PHY block on the other. It has a dedicated address
> > space, interrupt line and clock.
> >
> > It is represented as a V4L2 subdev to the CSI controller and takes a
> > MIPI CSI-2 sensor as its own subdev, all using the fwnode graph and
> > media controller API.
> >
> > Only 8-bit and 10-bit Bayer formats are currently supported.
> > While up to 4 internal channels to the CSI controller exist, only one
> > is currently supported by this implementation.
> >
> > Signed-off-by: Paul Kocialkowski
> > ---
> > drivers/media/platform/sunxi/Kconfig | 1 +
> > drivers/media/platform/sunxi/Makefile | 1 +
> > .../platform/sunxi/sun6i-mipi-csi2/Kconfig| 12 +
> > .../platform/sunxi/sun6i-mipi-csi2/Makefile | 4 +
> > .../sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.c | 590 ++
> > .../sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.h | 117
> > 6 files changed, 725 insertions(+)
> > create mode 100644 drivers/media/platform/sunxi/sun6i-mipi-csi2/Kconfig
> > create mode 100644 drivers/media/platform/sunxi/sun6i-mipi-csi2/Makefile
> > create mode 100644
> > drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.c
> > create mode 100644
> > drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.h
> >
> [..]
> > +static int sun6i_mipi_csi2_v4l2_setup(struct sun6i_mipi_csi2_dev *cdev)
> > +{
> > + struct sun6i_mipi_csi2_video *video = >video;
> > + struct v4l2_subdev *subdev = >subdev;
> > + struct v4l2_async_notifier *notifier = >notifier;
> > + struct fwnode_handle *handle;
> > + struct v4l2_fwnode_endpoint *endpoint;
> > + struct v4l2_async_subdev *subdev_async;
> > + int ret;
> > +
> > + /* Subdev */
> > +
> > + v4l2_subdev_init(subdev, _mipi_csi2_subdev_ops);
> > + subdev->dev = cdev->dev;
> > + subdev->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
> > + strscpy(subdev->name, MODULE_NAME, sizeof(subdev->name));
> > + v4l2_set_subdevdata(subdev, cdev);
> > +
> > + /* Entity */
> > +
> > + subdev->entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
> > + subdev->entity.ops = _mipi_csi2_entity_ops;
> > +
> > + /* Pads */
> > +
> > + video->pads[0].flags = MEDIA_PAD_FL_SINK;
> > + video->pads[1].flags = MEDIA_PAD_FL_SOURCE;
> > +
> > + ret = media_entity_pads_init(>entity, 2, video->pads);
> > + if (ret)
> > + return ret;
> > +
> > + /* Endpoint */
> > +
> > + handle = fwnode_graph_get_endpoint_by_id(dev_fwnode(cdev->dev), 0,
> > 0,
> > +
> > FWNODE_GRAPH_ENDPOINT_NEXT);
> > + if (!handle) {
> > + ret = -ENODEV;
> > + goto error_media_entity;
> > + }
> > +
> > + endpoint = >endpoint;
> > + endpoint->bus_type = V4L2_MBUS_CSI2_DPHY;
> > +
> > + ret = v4l2_fwnode_endpoint_parse(handle, endpoint);
> > + fwnode_handle_put(handle);
>
> I think the _put should be...
>
> > + if (ret)
> > + goto error_media_entity;
> > +
> > + /* Notifier */
> > +
> > + v4l2_async_notifier_init(notifier);
> > +
> > + subdev_async = >subdev_async;
> > + ret = v4l2_async_notifier_add_fwnode_remote_subdev(notifier, handle,
> > + subdev_async);
>
> ... here. See for instance drivers/media/platform/rcar-vin/rcar-csi2.c.
>
> (Unless I've missed something, of course).
I think you're right, the reference is obtained at
fwnode_graph_get_endpoint_by_id and should be held when passing handle to
v4l2_async_notifier_add_fwnode_remote_subdev since it will be used to get
a reference to the remote port.
Good catch and thanks for the review!
Paul
--
Paul Kocialkowski, Bootlin
Embedded Linux and kernel engineering
https://bootlin.com
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[linux-sunxi] Re: [PATCH v4 09/15] media: sunxi: Add support for the A31 MIPI CSI-2 controller
Hi Samuel,
On Sat 09 Jan 21, 16:24, Samuel Holland wrote:
> On 12/31/20 8:29 AM, Paul Kocialkowski wrote:
> > The A31 MIPI CSI-2 controller is a dedicated MIPI CSI-2 bridge
> > found on Allwinner SoCs such as the A31 and V3/V3s.
> >
> > It is a standalone block, connected to the CSI controller on one side
> > and to the MIPI D-PHY block on the other. It has a dedicated address
> > space, interrupt line and clock.
> >
> > It is represented as a V4L2 subdev to the CSI controller and takes a
> > MIPI CSI-2 sensor as its own subdev, all using the fwnode graph and
> > media controller API.
> >
> > Only 8-bit and 10-bit Bayer formats are currently supported.
> > While up to 4 internal channels to the CSI controller exist, only one
> > is currently supported by this implementation.
> >
> > Signed-off-by: Paul Kocialkowski
> > ---
> > drivers/media/platform/sunxi/Kconfig | 1 +
> > drivers/media/platform/sunxi/Makefile | 1 +
> > .../platform/sunxi/sun6i-mipi-csi2/Kconfig| 12 +
> > .../platform/sunxi/sun6i-mipi-csi2/Makefile | 4 +
> > .../sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.c | 590 ++
> > .../sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.h | 117
> > 6 files changed, 725 insertions(+)
> > create mode 100644 drivers/media/platform/sunxi/sun6i-mipi-csi2/Kconfig
> > create mode 100644 drivers/media/platform/sunxi/sun6i-mipi-csi2/Makefile
> > create mode 100644
> > drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.c
> > create mode 100644
> > drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.h
> >
> > diff --git a/drivers/media/platform/sunxi/Kconfig
> > b/drivers/media/platform/sunxi/Kconfig
> > index 7151cc249afa..9684e07454ad 100644
> > --- a/drivers/media/platform/sunxi/Kconfig
> > +++ b/drivers/media/platform/sunxi/Kconfig
> > @@ -2,3 +2,4 @@
> >
> > source "drivers/media/platform/sunxi/sun4i-csi/Kconfig"
> > source "drivers/media/platform/sunxi/sun6i-csi/Kconfig"
> > +source "drivers/media/platform/sunxi/sun6i-mipi-csi2/Kconfig"
> > diff --git a/drivers/media/platform/sunxi/Makefile
> > b/drivers/media/platform/sunxi/Makefile
> > index fc537c9f5ca9..887a7cae8fca 100644
> > --- a/drivers/media/platform/sunxi/Makefile
> > +++ b/drivers/media/platform/sunxi/Makefile
> > @@ -2,5 +2,6 @@
> >
> > obj-y += sun4i-csi/
> > obj-y += sun6i-csi/
> > +obj-y += sun6i-mipi-csi2/
> > obj-y += sun8i-di/
> > obj-y += sun8i-rotate/
> > diff --git a/drivers/media/platform/sunxi/sun6i-mipi-csi2/Kconfig
> > b/drivers/media/platform/sunxi/sun6i-mipi-csi2/Kconfig
> > new file mode 100644
> > index ..47f1bb0779a8
> > --- /dev/null
> > +++ b/drivers/media/platform/sunxi/sun6i-mipi-csi2/Kconfig
> > @@ -0,0 +1,12 @@
> > +# SPDX-License-Identifier: GPL-2.0-only
> > +config VIDEO_SUN6I_MIPI_CSI2
> > + tristate "Allwinner A31 MIPI CSI-2 Controller Driver"
> > + depends on ARCH_SUNXI || COMPILE_TEST
> > + depends on PM && COMMON_CLK && VIDEO_V4L2
> > + select REGMAP_MMIO
> > + select PHY_SUN6I_MIPI_DPHY
> > + select MEDIA_CONTROLLER
> > + select VIDEO_V4L2_SUBDEV_API
> > + select V4L2_FWNODE
> > + help
> > + Support for the Allwinner A31 MIPI CSI-2 Controller.
> > diff --git a/drivers/media/platform/sunxi/sun6i-mipi-csi2/Makefile
> > b/drivers/media/platform/sunxi/sun6i-mipi-csi2/Makefile
> > new file mode 100644
> > index ..14e4e03818b5
> > --- /dev/null
> > +++ b/drivers/media/platform/sunxi/sun6i-mipi-csi2/Makefile
> > @@ -0,0 +1,4 @@
> > +# SPDX-License-Identifier: GPL-2.0-only
> > +sun6i-mipi-csi2-y += sun6i_mipi_csi2.o
> > +
> > +obj-$(CONFIG_VIDEO_SUN6I_MIPI_CSI2) += sun6i-mipi-csi2.o
> > diff --git a/drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.c
> > b/drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.c
> > new file mode 100644
> > index ..87307beda4cf
> > --- /dev/null
> > +++ b/drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.c
> > @@ -0,0 +1,590 @@
> [...]
> > +/* Base Driver */
> > +
> > +static int sun6i_mipi_csi2_suspend(struct device *dev)
> > +{
> > + struct sun6i_mipi_csi2_dev *cdev = dev_get_drvdata(dev);
> > +
> > + clk_disable_unprepare(cdev->clk_mod);
> > + clk_disable_unprepare(cdev->clk_bus);
> >
[linux-sunxi] [PATCH v4 10/15] ARM: dts: sun8i: v3s: Add nodes for MIPI CSI-2 support
MIPI CSI-2 is supported on the V3s with an A31-based MIPI CSI-2 bridge
controller. The controller uses a separate D-PHY, which is the same
that is otherwise used for MIPI DSI, but used in Rx mode.
On the V3s, the CSI0 controller is dedicated to MIPI CSI-2 as it does
not have access to any parallel interface pins.
Add all the necessary nodes (CSI0, MIPI CSI-2 bridge and D-PHY) to
support the MIPI CSI-2 interface.
Note that a fwnode graph link is created between CSI0 and MIPI CSI-2
even when no sensor is connected. This will result in a probe failure
for the controller as long as no sensor is connected but this is fine
since no other interface is available.
Signed-off-by: Paul Kocialkowski
---
arch/arm/boot/dts/sun8i-v3s.dtsi | 67
1 file changed, 67 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi
index 7b2d684aeb97..b7f2bcd25c86 100644
--- a/arch/arm/boot/dts/sun8i-v3s.dtsi
+++ b/arch/arm/boot/dts/sun8i-v3s.dtsi
@@ -530,6 +530,31 @@ spi0: spi@1c68000 {
#size-cells = <0>;
};
+ csi0: camera@1cb {
+ compatible = "allwinner,sun8i-v3s-csi";
+ reg = <0x01cb 0x1000>;
+ interrupts = ;
+ clocks = < CLK_BUS_CSI>,
+< CLK_CSI1_SCLK>,
+< CLK_DRAM_CSI>;
+ clock-names = "bus", "mod", "ram";
+ resets = < RST_BUS_CSI>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <1>;
+
+ csi0_in_mipi_csi2: endpoint {
+ remote-endpoint =
<_csi2_out_csi0>;
+ };
+ };
+ };
+ };
+
csi1: camera@1cb4000 {
compatible = "allwinner,sun8i-v3s-csi";
reg = <0x01cb4000 0x3000>;
@@ -552,5 +577,47 @@ gic: interrupt-controller@1c81000 {
#interrupt-cells = <3>;
interrupts = ;
};
+
+ mipi_csi2: csi@1cb1000 {
+ compatible = "allwinner,sun8i-v3s-mipi-csi2",
+"allwinner,sun6i-a31-mipi-csi2";
+ reg = <0x01cb1000 0x1000>;
+ interrupts = ;
+ clocks = < CLK_BUS_CSI>,
+< CLK_CSI1_SCLK>;
+ clock-names = "bus", "mod";
+ resets = < RST_BUS_CSI>;
+ status = "disabled";
+
+ phys = <>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mipi_csi2_in: port@0 {
+ reg = <0>;
+ };
+
+ mipi_csi2_out: port@1 {
+ reg = <1>;
+
+ mipi_csi2_out_csi0: endpoint {
+ remote-endpoint =
<_in_mipi_csi2>;
+ };
+ };
+ };
+ };
+
+ dphy: d-phy@1cb2000 {
+ compatible = "allwinner,sun6i-a31-mipi-dphy";
+ reg = <0x01cb2000 0x1000>;
+ clocks = < CLK_BUS_CSI>,
+< CLK_MIPI_CSI>;
+ clock-names = "bus", "mod";
+ resets = < RST_BUS_CSI>;
+ status = "disabled";
+ #phy-cells = <0>;
+ };
};
};
--
2.29.2
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[linux-sunxi] [PATCH v4 11/15] MAINTAINERS: Add entry for the Allwinner A31 MIPI CSI-2 bridge
Add myself as maintainer of the A31 MIPI CSI-2 bridge media driver. Signed-off-by: Paul Kocialkowski --- MAINTAINERS | 8 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 0644128640fb..a1352171778b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -709,6 +709,14 @@ T: git git://linuxtv.org/media_tree.git F: Documentation/devicetree/bindings/media/allwinner,sun4i-a10-csi.yaml F: drivers/media/platform/sunxi/sun4i-csi/ +ALLWINNER A31 MIPI CSI-2 BRIDGE +M: Paul Kocialkowski +L: linux-me...@vger.kernel.org +S: Maintained +T: git git://linuxtv.org/media_tree.git +F: Documentation/devicetree/bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml +F: drivers/media/platform/sunxi/sun6i-mipi-csi2/ + ALLWINNER CPUFREQ DRIVER M: Yangtao Li L: linux...@vger.kernel.org -- 2.29.2 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/20201231142948.3241780-12-paul.kocialkowski%40bootlin.com.
[linux-sunxi] [PATCH v4 15/15] MAINTAINERS: Add entry for the Allwinner A83T MIPI CSI-2 bridge
Add myself as maintainer of the A83T MIPI CSI-2 bridge media driver. Signed-off-by: Paul Kocialkowski --- MAINTAINERS | 8 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index a1352171778b..3b48612657b6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -717,6 +717,14 @@ T: git git://linuxtv.org/media_tree.git F: Documentation/devicetree/bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml F: drivers/media/platform/sunxi/sun6i-mipi-csi2/ +ALLWINNER A83T MIPI CSI-2 BRIDGE +M: Paul Kocialkowski +L: linux-me...@vger.kernel.org +S: Maintained +T: git git://linuxtv.org/media_tree.git +F: Documentation/devicetree/bindings/media/allwinner,sun8i-a83t-mipi-csi2.yaml +F: drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/ + ALLWINNER CPUFREQ DRIVER M: Yangtao Li L: linux...@vger.kernel.org -- 2.29.2 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/20201231142948.3241780-16-paul.kocialkowski%40bootlin.com.
[linux-sunxi] [PATCH v4 08/15] dt-bindings: media: Add A31 MIPI CSI-2 bindings documentation
This introduces YAML bindings documentation for the A31 MIPI CSI-2
controller.
Signed-off-by: Paul Kocialkowski
---
.../media/allwinner,sun6i-a31-mipi-csi2.yaml | 149 ++
1 file changed, 149 insertions(+)
create mode 100644
Documentation/devicetree/bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml
diff --git
a/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml
b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml
new file mode 100644
index ..bb05105c45b7
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml
@@ -0,0 +1,149 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/allwinner,sun6i-a31-mipi-csi2.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Allwinner A31 MIPI CSI-2 Device Tree Bindings
+
+maintainers:
+ - Paul Kocialkowski
+
+properties:
+ compatible:
+oneOf:
+ - const: allwinner,sun6i-a31-mipi-csi2
+ - items:
+ - const: allwinner,sun8i-v3s-mipi-csi2
+ - const: allwinner,sun6i-a31-mipi-csi2
+
+ reg:
+maxItems: 1
+
+ interrupts:
+maxItems: 1
+
+ clocks:
+items:
+ - description: Bus Clock
+ - description: Module Clock
+
+ clock-names:
+items:
+ - const: bus
+ - const: mod
+
+ phys:
+maxItems: 1
+description: MIPI D-PHY
+
+ resets:
+maxItems: 1
+
+ # See ./video-interfaces.txt for details
+ ports:
+type: object
+
+properties:
+ port@0:
+type: object
+description: Input port, connect to a MIPI CSI-2 sensor
+
+properties:
+ reg:
+const: 0
+
+ endpoint:
+type: object
+
+properties:
+ remote-endpoint: true
+
+ data-lanes:
+minItems: 1
+maxItems: 4
+
+required:
+ - data-lanes
+ - remote-endpoint
+
+required:
+ - endpoint
+
+additionalProperties: false
+
+ port@1:
+type: object
+description: Output port, connect to a CSI controller
+
+properties:
+ reg:
+const: 1
+
+ endpoint:
+type: object
+
+properties:
+ remote-endpoint: true
+
+required:
+ - remote-endpoint
+
+required:
+ - endpoint
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - resets
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+#include
+#include
+
+mipi_csi2: csi@1cb1000 {
+compatible = "allwinner,sun8i-v3s-mipi-csi2",
+ "allwinner,sun6i-a31-mipi-csi2";
+reg = <0x01cb1000 0x1000>;
+interrupts = ;
+clocks = < CLK_BUS_CSI>,
+ < CLK_CSI1_SCLK>;
+clock-names = "bus", "mod";
+resets = < RST_BUS_CSI>;
+
+phys = <>;
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+mipi_csi2_in: port@0 {
+reg = <0>;
+
+mipi_csi2_in_ov5648: endpoint {
+data-lanes = <1 2 3 4>;
+
+remote-endpoint = <_out_mipi_csi2>;
+};
+};
+
+mipi_csi2_out: port@1 {
+reg = <1>;
+
+mipi_csi2_out_csi0: endpoint {
+remote-endpoint = <_in_mipi_csi2>;
+};
+};
+};
+};
+
+...
--
2.29.2
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[linux-sunxi] [PATCH v4 14/15] ARM: dts: sun8i: a83t: Add MIPI CSI-2 controller node
MIPI CSI-2 is supported on the A83T with a dedicated controller that
covers both the protocol and D-PHY. It can be connected to the CSI
interface as a V4L2 subdev through the fwnode graph.
This is not done by default since connecting the bridge without a
subdev attached to it will cause a failure on the CSI driver.
Signed-off-by: Paul Kocialkowski
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 26 ++
1 file changed, 26 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index c010b27fdb6a..d6d55c12b995 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -1066,6 +1066,32 @@ csi_in: port {
};
};
+ mipi_csi2: csi@1cb1000 {
+ compatible = "allwinner,sun8i-a83t-mipi-csi2";
+ reg = <0x01cb1000 0x1000>;
+ interrupts = ;
+ clocks = < CLK_BUS_CSI>,
+< CLK_CSI_SCLK>,
+< CLK_MIPI_CSI>,
+< CLK_CSI_MISC>;
+ clock-names = "bus", "mod", "mipi", "misc";
+ resets = < RST_BUS_CSI>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mipi_csi2_in: port@0 {
+ reg = <0>;
+ };
+
+ mipi_csi2_out: port@1 {
+ reg = <1>;
+ };
+ };
+ };
+
hdmi: hdmi@1ee {
compatible = "allwinner,sun8i-a83t-dw-hdmi";
reg = <0x01ee 0x1>;
--
2.29.2
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[linux-sunxi] [PATCH v4 07/15] media: sun6i-csi: Add support for MIPI CSI-2 bridge input
The A31 CSI controller supports a MIPI CSI-2 bridge input, which has
its own dedicated port in the fwnode graph.
Support for this input is added with this change:
- two pads are defined for the media entity instead of one
and only one needs to be connected at a time;
- the pads currently match the fwnode graph representation;
- links are created between our pads and the subdevs for each
interface and are no longer immutable so that userspace can select
which interface to use in case both are bound to a subdev;
- fwnode endpoints are parsed and stored for each interface;
- the active subdev (and fwnode endpoint) is retrieved when validating
the media link at stream on time and cleared at stream off;
- an error is raised if both links are active at the same time;
- the MIPI interface bit is set if the MIPI CSI-2 bridge endpoint is
active.
In the future, the media entity representation might evolve to:
- distinguish the internal parallel bridge and data formatter;
- represent each of the 4 internal channels that can exist between
the parallel bridge (for BT656 time-multiplex) and MIPI CSI-2
(internal channels can be mapped to virtual channels);
- connect the controller's output to the ISP instead of its
DMA engine.
Finally note that the MIPI CSI-2 bridges should not be linked in
the fwnode graph unless they have a sensor subdev attached.
Signed-off-by: Paul Kocialkowski
---
.../platform/sunxi/sun6i-csi/sun6i_csi.c | 123 ++
.../platform/sunxi/sun6i-csi/sun6i_csi.h | 9 +-
.../platform/sunxi/sun6i-csi/sun6i_video.c| 57
.../platform/sunxi/sun6i-csi/sun6i_video.h| 7 +-
4 files changed, 142 insertions(+), 54 deletions(-)
diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
index f1150de94e98..dcf465d73579 100644
--- a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
+++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
@@ -49,6 +49,7 @@ static inline struct sun6i_csi_dev *sun6i_csi_to_dev(struct
sun6i_csi *csi)
/* TODO add 10&12 bit YUV, RGB support */
bool sun6i_csi_is_format_supported(struct sun6i_csi *csi,
+ struct v4l2_fwnode_endpoint *endpoint,
u32 pixformat, u32 mbus_code)
{
struct sun6i_csi_dev *sdev = sun6i_csi_to_dev(csi);
@@ -58,9 +59,9 @@ bool sun6i_csi_is_format_supported(struct sun6i_csi *csi,
* 8bit and 16bit bus width.
* Identify the media bus format from device tree.
*/
- if ((sdev->csi.v4l2_ep.bus_type == V4L2_MBUS_PARALLEL
-|| sdev->csi.v4l2_ep.bus_type == V4L2_MBUS_BT656)
-&& sdev->csi.v4l2_ep.bus.parallel.bus_width == 16) {
+ if ((endpoint->bus_type == V4L2_MBUS_PARALLEL ||
+endpoint->bus_type == V4L2_MBUS_BT656) &&
+ endpoint->bus.parallel.bus_width == 16) {
switch (pixformat) {
case V4L2_PIX_FMT_HM12:
case V4L2_PIX_FMT_NV12:
@@ -373,7 +374,7 @@ static enum csi_input_seq get_csi_input_seq(struct
sun6i_csi_dev *sdev,
static void sun6i_csi_setup_bus(struct sun6i_csi_dev *sdev)
{
- struct v4l2_fwnode_endpoint *endpoint = >csi.v4l2_ep;
+ struct v4l2_fwnode_endpoint *endpoint = sdev->csi.video.source_endpoint;
struct sun6i_csi *csi = >csi;
unsigned char bus_width;
u32 flags;
@@ -459,6 +460,9 @@ static void sun6i_csi_setup_bus(struct sun6i_csi_dev *sdev)
if (flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
cfg |= CSI_IF_CFG_CLK_POL_FALLING_EDGE;
break;
+ case V4L2_MBUS_CSI2_DPHY:
+ cfg |= CSI_IF_CFG_MIPI_IF_MIPI;
+ break;
default:
dev_warn(sdev->dev, "Unsupported bus type: %d\n",
endpoint->bus_type);
@@ -636,11 +640,11 @@ void sun6i_csi_set_stream(struct sun6i_csi *csi, bool
enable)
* Media Controller and V4L2
*/
static int sun6i_csi_link_entity(struct sun6i_csi *csi,
+struct media_pad *sink_pad,
struct media_entity *entity,
-struct fwnode_handle *fwnode)
+struct fwnode_handle *fwnode, bool enabled)
{
struct media_entity *sink;
- struct media_pad *sink_pad;
int src_pad_index;
int ret;
@@ -654,14 +658,12 @@ static int sun6i_csi_link_entity(struct sun6i_csi *csi,
src_pad_index = ret;
sink = >video.vdev.entity;
- sink_pad = >video.pad;
dev_dbg(csi->dev, "creating %s:%u -> %s:%u link\n",
entity->name, src_pad_index, sink->name, sink_pad->index);
ret = media_create_pad_link(entity, src_pad_index, sink,
[linux-sunxi] [PATCH v4 13/15] media: sunxi: Add support for the A83T MIPI CSI-2 controller
The A83T supports MIPI CSI-2 with a composite controller, covering both the protocol logic and the D-PHY implementation. This controller seems to be found on the A83T only and probably was abandoned since. This implementation splits the protocol and D-PHY registers and uses the PHY framework internally. The D-PHY is not registered as a standalone PHY driver since it cannot be used with any other controller. There are a few notable points about the controller: - The initialisation sequence involes writing specific magic init values that do not seem to make any particular sense given the concerned register fields; - Interrupts appear to be hitting regardless of the interrupt mask registers, which can cause a serious flood when transmission errors occur. Only 8-bit and 10-bit Bayer formats are currently supported. While up to 4 internal channels to the CSI controller exist, only one is currently supported by this implementation. This work is based on the first version of the driver submitted by Kévin L'hôpital, which was adapted to mainline from the Allwinner BSP. This version integrates MIPI CSI-2 support as a standalone V4L2 subdev instead of merging it in the sun6i-csi driver. It was tested on a Banana Pi M3 board with an OV8865 sensor in a 4-lane configuration. Signed-off-by: Paul Kocialkowski --- drivers/media/platform/sunxi/Kconfig | 1 + drivers/media/platform/sunxi/Makefile | 1 + .../sunxi/sun8i-a83t-mipi-csi2/Kconfig| 11 + .../sunxi/sun8i-a83t-mipi-csi2/Makefile | 4 + .../sun8i-a83t-mipi-csi2/sun8i_a83t_dphy.c| 92 +++ .../sun8i-a83t-mipi-csi2/sun8i_a83t_dphy.h| 39 ++ .../sun8i_a83t_mipi_csi2.c| 657 ++ .../sun8i_a83t_mipi_csi2.h| 197 ++ 8 files changed, 1002 insertions(+) create mode 100644 drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/Kconfig create mode 100644 drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/Makefile create mode 100644 drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_dphy.c create mode 100644 drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_dphy.h create mode 100644 drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_mipi_csi2.c create mode 100644 drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_mipi_csi2.h diff --git a/drivers/media/platform/sunxi/Kconfig b/drivers/media/platform/sunxi/Kconfig index 9684e07454ad..db4c07be7e4c 100644 --- a/drivers/media/platform/sunxi/Kconfig +++ b/drivers/media/platform/sunxi/Kconfig @@ -3,3 +3,4 @@ source "drivers/media/platform/sunxi/sun4i-csi/Kconfig" source "drivers/media/platform/sunxi/sun6i-csi/Kconfig" source "drivers/media/platform/sunxi/sun6i-mipi-csi2/Kconfig" +source "drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/Kconfig" diff --git a/drivers/media/platform/sunxi/Makefile b/drivers/media/platform/sunxi/Makefile index 887a7cae8fca..9aa01cb01883 100644 --- a/drivers/media/platform/sunxi/Makefile +++ b/drivers/media/platform/sunxi/Makefile @@ -3,5 +3,6 @@ obj-y += sun4i-csi/ obj-y += sun6i-csi/ obj-y += sun6i-mipi-csi2/ +obj-y += sun8i-a83t-mipi-csi2/ obj-y += sun8i-di/ obj-y += sun8i-rotate/ diff --git a/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/Kconfig b/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/Kconfig new file mode 100644 index ..60e7a9c41065 --- /dev/null +++ b/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/Kconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-only +config VIDEO_SUN8I_A83T_MIPI_CSI2 + tristate "Allwinner A83T MIPI CSI-2 Controller and D-PHY Driver" + depends on ARCH_SUNXI || COMPILE_TEST + depends on PM && COMMON_CLK && VIDEO_V4L2 + select REGMAP_MMIO + select MEDIA_CONTROLLER + select VIDEO_V4L2_SUBDEV_API + select V4L2_FWNODE + help + Support for the Allwinner A83T MIPI CSI-2 Controller and D-PHY. diff --git a/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/Makefile b/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/Makefile new file mode 100644 index ..1427d15a879a --- /dev/null +++ b/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only +sun8i-a83t-mipi-csi2-y += sun8i_a83t_mipi_csi2.o sun8i_a83t_dphy.o + +obj-$(CONFIG_VIDEO_SUN8I_A83T_MIPI_CSI2) += sun8i-a83t-mipi-csi2.o diff --git a/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_dphy.c b/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_dphy.c new file mode 100644 index ..c380065eb7c9 --- /dev/null +++ b/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_dphy.c @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 Bootlin + * Author: Paul Kocialkowski + */ + +#include +#include + +#include &q
[linux-sunxi] [PATCH v4 12/15] dt-bindings: media: Add A83T MIPI CSI-2 bindings documentation
This introduces YAML bindings documentation for the A83T MIPI CSI-2
controller.
Signed-off-by: Paul Kocialkowski
Reviewed-by: Rob Herring
---
.../media/allwinner,sun8i-a83t-mipi-csi2.yaml | 147 ++
1 file changed, 147 insertions(+)
create mode 100644
Documentation/devicetree/bindings/media/allwinner,sun8i-a83t-mipi-csi2.yaml
diff --git
a/Documentation/devicetree/bindings/media/allwinner,sun8i-a83t-mipi-csi2.yaml
b/Documentation/devicetree/bindings/media/allwinner,sun8i-a83t-mipi-csi2.yaml
new file mode 100644
index ..e607fae7d85e
--- /dev/null
+++
b/Documentation/devicetree/bindings/media/allwinner,sun8i-a83t-mipi-csi2.yaml
@@ -0,0 +1,147 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/allwinner,sun8i-a83t-mipi-csi2.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Allwinner A83T MIPI CSI-2 Device Tree Bindings
+
+maintainers:
+ - Paul Kocialkowski
+
+properties:
+ compatible:
+const: allwinner,sun8i-a83t-mipi-csi2
+
+ reg:
+maxItems: 1
+
+ interrupts:
+maxItems: 1
+
+ clocks:
+items:
+ - description: Bus Clock
+ - description: Module Clock
+ - description: MIPI-specific Clock
+ - description: Misc CSI Clock
+
+ clock-names:
+items:
+ - const: bus
+ - const: mod
+ - const: mipi
+ - const: misc
+
+ resets:
+maxItems: 1
+
+ # See ./video-interfaces.txt for details
+ ports:
+type: object
+
+properties:
+ port@0:
+type: object
+description: Input port, connect to a MIPI CSI-2 sensor
+
+properties:
+ reg:
+const: 0
+
+ endpoint:
+type: object
+
+properties:
+ remote-endpoint: true
+
+ clock-lanes:
+maxItems: 1
+
+ data-lanes:
+minItems: 1
+maxItems: 4
+
+required:
+ - data-lanes
+ - remote-endpoint
+
+required:
+ - endpoint
+
+additionalProperties: false
+
+ port@1:
+type: object
+description: Output port, connect to a CSI controller
+
+properties:
+ reg:
+const: 1
+
+ endpoint:
+type: object
+
+properties:
+ remote-endpoint: true
+
+required:
+ - remote-endpoint
+
+required:
+ - endpoint
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - resets
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+#include
+#include
+
+mipi_csi2: csi@1cb1000 {
+compatible = "allwinner,sun8i-a83t-mipi-csi2";
+reg = <0x01cb1000 0x1000>;
+interrupts = ;
+clocks = < CLK_BUS_CSI>,
+ < CLK_CSI_SCLK>,
+ < CLK_MIPI_CSI>,
+ < CLK_CSI_MISC>;
+clock-names = "bus", "mod", "mipi", "misc";
+resets = < RST_BUS_CSI>;
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+mipi_csi2_in: port@0 {
+reg = <0>;
+
+mipi_csi2_in_ov8865: endpoint {
+data-lanes = <1 2 3 4>;
+
+remote-endpoint = <_out_mipi_csi2>;
+};
+};
+
+mipi_csi2_out: port@1 {
+reg = <1>;
+
+mipi_csi2_out_csi: endpoint {
+remote-endpoint = <_in_mipi_csi2>;
+};
+};
+};
+};
+
+...
--
2.29.2
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[linux-sunxi] [PATCH v4 09/15] media: sunxi: Add support for the A31 MIPI CSI-2 controller
The A31 MIPI CSI-2 controller is a dedicated MIPI CSI-2 bridge
found on Allwinner SoCs such as the A31 and V3/V3s.
It is a standalone block, connected to the CSI controller on one side
and to the MIPI D-PHY block on the other. It has a dedicated address
space, interrupt line and clock.
It is represented as a V4L2 subdev to the CSI controller and takes a
MIPI CSI-2 sensor as its own subdev, all using the fwnode graph and
media controller API.
Only 8-bit and 10-bit Bayer formats are currently supported.
While up to 4 internal channels to the CSI controller exist, only one
is currently supported by this implementation.
Signed-off-by: Paul Kocialkowski
---
drivers/media/platform/sunxi/Kconfig | 1 +
drivers/media/platform/sunxi/Makefile | 1 +
.../platform/sunxi/sun6i-mipi-csi2/Kconfig| 12 +
.../platform/sunxi/sun6i-mipi-csi2/Makefile | 4 +
.../sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.c | 590 ++
.../sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.h | 117
6 files changed, 725 insertions(+)
create mode 100644 drivers/media/platform/sunxi/sun6i-mipi-csi2/Kconfig
create mode 100644 drivers/media/platform/sunxi/sun6i-mipi-csi2/Makefile
create mode 100644
drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.c
create mode 100644
drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.h
diff --git a/drivers/media/platform/sunxi/Kconfig
b/drivers/media/platform/sunxi/Kconfig
index 7151cc249afa..9684e07454ad 100644
--- a/drivers/media/platform/sunxi/Kconfig
+++ b/drivers/media/platform/sunxi/Kconfig
@@ -2,3 +2,4 @@
source "drivers/media/platform/sunxi/sun4i-csi/Kconfig"
source "drivers/media/platform/sunxi/sun6i-csi/Kconfig"
+source "drivers/media/platform/sunxi/sun6i-mipi-csi2/Kconfig"
diff --git a/drivers/media/platform/sunxi/Makefile
b/drivers/media/platform/sunxi/Makefile
index fc537c9f5ca9..887a7cae8fca 100644
--- a/drivers/media/platform/sunxi/Makefile
+++ b/drivers/media/platform/sunxi/Makefile
@@ -2,5 +2,6 @@
obj-y += sun4i-csi/
obj-y += sun6i-csi/
+obj-y += sun6i-mipi-csi2/
obj-y += sun8i-di/
obj-y += sun8i-rotate/
diff --git a/drivers/media/platform/sunxi/sun6i-mipi-csi2/Kconfig
b/drivers/media/platform/sunxi/sun6i-mipi-csi2/Kconfig
new file mode 100644
index ..47f1bb0779a8
--- /dev/null
+++ b/drivers/media/platform/sunxi/sun6i-mipi-csi2/Kconfig
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-only
+config VIDEO_SUN6I_MIPI_CSI2
+ tristate "Allwinner A31 MIPI CSI-2 Controller Driver"
+ depends on ARCH_SUNXI || COMPILE_TEST
+ depends on PM && COMMON_CLK && VIDEO_V4L2
+ select REGMAP_MMIO
+ select PHY_SUN6I_MIPI_DPHY
+ select MEDIA_CONTROLLER
+ select VIDEO_V4L2_SUBDEV_API
+ select V4L2_FWNODE
+ help
+ Support for the Allwinner A31 MIPI CSI-2 Controller.
diff --git a/drivers/media/platform/sunxi/sun6i-mipi-csi2/Makefile
b/drivers/media/platform/sunxi/sun6i-mipi-csi2/Makefile
new file mode 100644
index ..14e4e03818b5
--- /dev/null
+++ b/drivers/media/platform/sunxi/sun6i-mipi-csi2/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+sun6i-mipi-csi2-y += sun6i_mipi_csi2.o
+
+obj-$(CONFIG_VIDEO_SUN6I_MIPI_CSI2) += sun6i-mipi-csi2.o
diff --git a/drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.c
b/drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.c
new file mode 100644
index ..87307beda4cf
--- /dev/null
+++ b/drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.c
@@ -0,0 +1,590 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 Bootlin
+ * Author: Paul Kocialkowski
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "sun6i_mipi_csi2.h"
+
+#define MODULE_NAME"sun6i-mipi-csi2"
+
+static const u32 sun6i_mipi_csi2_mbus_codes[] = {
+ MEDIA_BUS_FMT_SBGGR8_1X8,
+ MEDIA_BUS_FMT_SGBRG8_1X8,
+ MEDIA_BUS_FMT_SGRBG8_1X8,
+ MEDIA_BUS_FMT_SRGGB8_1X8,
+ MEDIA_BUS_FMT_SBGGR10_1X10,
+ MEDIA_BUS_FMT_SGBRG10_1X10,
+ MEDIA_BUS_FMT_SGRBG10_1X10,
+ MEDIA_BUS_FMT_SRGGB10_1X10,
+};
+
+/* Video */
+
+static int sun6i_mipi_csi2_s_stream(struct v4l2_subdev *subdev, int on)
+{
+ struct sun6i_mipi_csi2_video *video =
+ sun6i_mipi_csi2_subdev_video(subdev);
+ struct sun6i_mipi_csi2_dev *cdev = sun6i_mipi_csi2_video_dev(video);
+ struct v4l2_subdev *remote_subdev = video->remote_subdev;
+ struct v4l2_fwnode_bus_mipi_csi2 *bus_mipi_csi2 =
+ >endpoint.bus.mipi_csi2;
+ union phy_configure_opts dphy_opts = { 0 };
+ struct phy_configure_opts_mipi_dphy *dphy_cfg = _opts.mipi_dphy;
+ struct regmap *regmap = cdev->regmap;
+ struct v4l2_ctrl *ct
[linux-sunxi] [PATCH v4 06/15] dt-bindings: media: sun6i-a31-csi: Add MIPI CSI-2 input port
The A31 CSI controller supports two distinct input interfaces:
parallel and an external MIPI CSI-2 bridge. The parallel interface
is often connected to a set of hardware pins while the MIPI CSI-2
bridge is an internal FIFO-ish link. As a result, these two inputs
are distinguished as two different ports.
Note that only one of the two may be present on a controller instance.
For example, the V3s has one controller dedicated to MIPI-CSI2 and one
dedicated to parallel.
Update the binding with an explicit ports node that holds two distinct
port nodes: one for parallel input and one for MIPI CSI-2.
This is backward-compatible with the single-port approach that was
previously taken for representing the parallel interface port, which
stays enumerated as fwnode port 0.
Note that additional ports may be added in the future, especially to
support feeding the CSI controller's output to the ISP.
Signed-off-by: Paul Kocialkowski
Reviewed-by: Rob Herring
---
.../media/allwinner,sun6i-a31-csi.yaml| 88 ---
1 file changed, 75 insertions(+), 13 deletions(-)
diff --git
a/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-csi.yaml
b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-csi.yaml
index 1fd9b5532a21..77ded77505e9 100644
--- a/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-csi.yaml
+++ b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-csi.yaml
@@ -67,6 +67,62 @@ properties:
additionalProperties: false
+ ports:
+type: object
+
+properties:
+ port@0:
+type: object
+description: Parallel input port, connect to a parallel sensor
+
+properties:
+ reg:
+const: 0
+
+ endpoint:
+type: object
+
+properties:
+ remote-endpoint: true
+
+ bus-width:
+enum: [ 8, 10, 12, 16 ]
+
+ pclk-sample: true
+ hsync-active: true
+ vsync-active: true
+
+required:
+ - bus-width
+ - remote-endpoint
+
+required:
+ - endpoint
+
+additionalProperties: false
+
+ port@1:
+type: object
+description: MIPI CSI-2 bridge input port
+
+properties:
+ reg:
+const: 1
+
+ endpoint:
+type: object
+
+properties:
+ remote-endpoint: true
+
+required:
+ - remote-endpoint
+
+required:
+ - endpoint
+
+additionalProperties: false
+
required:
- compatible
- reg
@@ -95,19 +151,25 @@ examples:
"ram";
resets = < RST_BUS_CSI>;
-port {
-/* Parallel bus endpoint */
-csi1_ep: endpoint {
-remote-endpoint = <_ep>;
-bus-width = <16>;
-
-/*
- * If hsync-active/vsync-active are missing,
- * embedded BT.656 sync is used.
- */
- hsync-active = <0>; /* Active low */
- vsync-active = <0>; /* Active low */
- pclk-sample = <1>; /* Rising */
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+port@0 {
+reg = <0>;
+/* Parallel bus endpoint */
+csi1_ep: endpoint {
+remote-endpoint = <_ep>;
+bus-width = <16>;
+
+/*
+ * If hsync-active/vsync-active are missing,
+ * embedded BT.656 sync is used.
+ */
+ hsync-active = <0>; /* Active low */
+ vsync-active = <0>; /* Active low */
+ pclk-sample = <1>; /* Rising */
+};
};
};
};
--
2.29.2
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[linux-sunxi] [PATCH v4 05/15] media: sun6i-csi: Only configure the interface data width for parallel
Bits related to the interface data width are only applicable to the
parallel interface and are irrelevant when the CSI controller is taking
input from the MIPI CSI-2 controller.
In prevision of adding support for this case, set these bits
conditionally so there is no ambiguity. The conditional block is
moved around before the interlaced conditional block for nicer code
symmetry (conditional blocks first) while at it.
Co-developed-by: Kévin L'hôpital
Signed-off-by: Kévin L'hôpital
Signed-off-by: Paul Kocialkowski
---
.../platform/sunxi/sun6i-csi/sun6i_csi.c | 42 +++
1 file changed, 25 insertions(+), 17 deletions(-)
diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
index 531a4cccd14a..f1150de94e98 100644
--- a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
+++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
@@ -378,8 +378,13 @@ static void sun6i_csi_setup_bus(struct sun6i_csi_dev *sdev)
unsigned char bus_width;
u32 flags;
u32 cfg;
+ bool input_parallel = false;
bool input_interlaced = false;
+ if (endpoint->bus_type == V4L2_MBUS_PARALLEL ||
+ endpoint->bus_type == V4L2_MBUS_BT656)
+ input_parallel = true;
+
if (csi->config.field == V4L2_FIELD_INTERLACED
|| csi->config.field == V4L2_FIELD_INTERLACED_TB
|| csi->config.field == V4L2_FIELD_INTERLACED_BT)
@@ -395,6 +400,26 @@ static void sun6i_csi_setup_bus(struct sun6i_csi_dev *sdev)
CSI_IF_CFG_HREF_POL_MASK | CSI_IF_CFG_FIELD_MASK |
CSI_IF_CFG_SRC_TYPE_MASK);
+ if (input_parallel) {
+ switch (bus_width) {
+ case 8:
+ cfg |= CSI_IF_CFG_IF_DATA_WIDTH_8BIT;
+ break;
+ case 10:
+ cfg |= CSI_IF_CFG_IF_DATA_WIDTH_10BIT;
+ break;
+ case 12:
+ cfg |= CSI_IF_CFG_IF_DATA_WIDTH_12BIT;
+ break;
+ case 16: /* No need to configure DATA_WIDTH for 16bit */
+ break;
+ default:
+ dev_warn(sdev->dev, "Unsupported bus width: %u\n",
+bus_width);
+ break;
+ }
+ }
+
if (input_interlaced)
cfg |= CSI_IF_CFG_SRC_TYPE_INTERLACED;
else
@@ -440,23 +465,6 @@ static void sun6i_csi_setup_bus(struct sun6i_csi_dev *sdev)
break;
}
- switch (bus_width) {
- case 8:
- cfg |= CSI_IF_CFG_IF_DATA_WIDTH_8BIT;
- break;
- case 10:
- cfg |= CSI_IF_CFG_IF_DATA_WIDTH_10BIT;
- break;
- case 12:
- cfg |= CSI_IF_CFG_IF_DATA_WIDTH_12BIT;
- break;
- case 16: /* No need to configure DATA_WIDTH for 16bit */
- break;
- default:
- dev_warn(sdev->dev, "Unsupported bus width: %u\n", bus_width);
- break;
- }
-
regmap_write(sdev->regmap, CSI_IF_CFG_REG, cfg);
}
--
2.29.2
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[linux-sunxi] [PATCH v4 04/15] media: sun6i-csi: Use common V4L2 format info for storage bpp
V4L2 has a common helper which can be used for calculating the number
of stored bits per pixels of a given (stored) image format.
Use the helper-returned structure instead of our own switch/case list.
Note that a few formats are not in that list so we keep them as
special cases.
The custom switch/case was also wrong concerning 10/12-bit Bayer
formats, which are aligned to 16 bits in memory. Using the common
helper fixes it.
Fixes: 5cc7522d8965 ("media: sun6i: Add support for Allwinner CSI V3s")
Signed-off-by: Paul Kocialkowski
Acked-by: Maxime Ripard
---
.../platform/sunxi/sun6i-csi/sun6i_csi.h | 55 +++
1 file changed, 20 insertions(+), 35 deletions(-)
diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.h
b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.h
index c626821aaedb..092445f04c60 100644
--- a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.h
+++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.h
@@ -86,53 +86,38 @@ void sun6i_csi_update_buf_addr(struct sun6i_csi *csi,
dma_addr_t addr);
*/
void sun6i_csi_set_stream(struct sun6i_csi *csi, bool enable);
-/* get bpp form v4l2 pixformat */
+/* get memory storage bpp from v4l2 pixformat */
static inline int sun6i_csi_get_bpp(unsigned int pixformat)
{
+ const struct v4l2_format_info *info;
+ unsigned int i;
+ int bpp = 0;
+
+ /* Handle special cases unknown to V4L2 format info first. */
switch (pixformat) {
- case V4L2_PIX_FMT_SBGGR8:
- case V4L2_PIX_FMT_SGBRG8:
- case V4L2_PIX_FMT_SGRBG8:
- case V4L2_PIX_FMT_SRGGB8:
case V4L2_PIX_FMT_JPEG:
return 8;
- case V4L2_PIX_FMT_SBGGR10:
- case V4L2_PIX_FMT_SGBRG10:
- case V4L2_PIX_FMT_SGRBG10:
- case V4L2_PIX_FMT_SRGGB10:
- return 10;
- case V4L2_PIX_FMT_SBGGR12:
- case V4L2_PIX_FMT_SGBRG12:
- case V4L2_PIX_FMT_SGRBG12:
- case V4L2_PIX_FMT_SRGGB12:
case V4L2_PIX_FMT_HM12:
- case V4L2_PIX_FMT_NV12:
- case V4L2_PIX_FMT_NV21:
- case V4L2_PIX_FMT_YUV420:
- case V4L2_PIX_FMT_YVU420:
return 12;
- case V4L2_PIX_FMT_YUYV:
- case V4L2_PIX_FMT_YVYU:
- case V4L2_PIX_FMT_UYVY:
- case V4L2_PIX_FMT_VYUY:
- case V4L2_PIX_FMT_NV16:
- case V4L2_PIX_FMT_NV61:
- case V4L2_PIX_FMT_YUV422P:
- case V4L2_PIX_FMT_RGB565:
case V4L2_PIX_FMT_RGB565X:
return 16;
- case V4L2_PIX_FMT_RGB24:
- case V4L2_PIX_FMT_BGR24:
- return 24;
- case V4L2_PIX_FMT_RGB32:
- case V4L2_PIX_FMT_BGR32:
- return 32;
- default:
+ }
+
+ info = v4l2_format_info(pixformat);
+ if (!info) {
WARN(1, "Unsupported pixformat: 0x%x\n", pixformat);
- break;
+ return 0;
+ }
+
+ for (i = 0; i < info->comp_planes; i++) {
+ unsigned int hdiv = (i == 0) ? 1 : info->hdiv;
+ unsigned int vdiv = (i == 0) ? 1 : info->vdiv;
+
+ /* We return bits per pixel while V4L2 format info is bytes. */
+ bpp += 8 * info->bpp[i] / hdiv / vdiv;
}
- return 0;
+ return bpp;
}
#endif /* __SUN6I_CSI_H__ */
--
2.29.2
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[linux-sunxi] [PATCH v4 03/15] phy: allwinner: phy-sun6i-mipi-dphy: Support D-PHY Rx mode for MIPI CSI-2
The Allwinner A31 D-PHY supports both Rx and Tx modes. While the latter
is already supported and used for MIPI DSI this adds support for the
former, to be used with MIPI CSI-2.
This implementation is inspired by Allwinner's V3s Linux SDK
implementation, which was used as a documentation base.
Signed-off-by: Paul Kocialkowski
Acked-by: Maxime Ripard
---
drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 164 +++-
1 file changed, 160 insertions(+), 4 deletions(-)
diff --git a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
index 1fa761ba6cbb..0389b6b670d6 100644
--- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
+++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
@@ -24,6 +24,14 @@
#define SUN6I_DPHY_TX_CTL_REG 0x04
#define SUN6I_DPHY_TX_CTL_HS_TX_CLK_CONT BIT(28)
+#define SUN6I_DPHY_RX_CTL_REG 0x08
+#define SUN6I_DPHY_RX_CTL_EN_DBC BIT(31)
+#define SUN6I_DPHY_RX_CTL_RX_CLK_FORCE BIT(24)
+#define SUN6I_DPHY_RX_CTL_RX_D3_FORCE BIT(23)
+#define SUN6I_DPHY_RX_CTL_RX_D2_FORCE BIT(22)
+#define SUN6I_DPHY_RX_CTL_RX_D1_FORCE BIT(21)
+#define SUN6I_DPHY_RX_CTL_RX_D0_FORCE BIT(20)
+
#define SUN6I_DPHY_TX_TIME0_REG0x10
#define SUN6I_DPHY_TX_TIME0_HS_TRAIL(n)(((n) & 0xff) << 24)
#define SUN6I_DPHY_TX_TIME0_HS_PREPARE(n) (((n) & 0xff) << 16)
@@ -44,12 +52,29 @@
#define SUN6I_DPHY_TX_TIME4_HS_TX_ANA1(n) (((n) & 0xff) << 8)
#define SUN6I_DPHY_TX_TIME4_HS_TX_ANA0(n) ((n) & 0xff)
+#define SUN6I_DPHY_RX_TIME0_REG0x30
+#define SUN6I_DPHY_RX_TIME0_HS_RX_SYNC(n) (((n) & 0xff) << 24)
+#define SUN6I_DPHY_RX_TIME0_HS_RX_CLK_MISS(n) (((n) & 0xff) << 16)
+#define SUN6I_DPHY_RX_TIME0_LP_RX(n) (((n) & 0xff) << 8)
+
+#define SUN6I_DPHY_RX_TIME1_REG0x34
+#define SUN6I_DPHY_RX_TIME1_RX_DLY(n) (((n) & 0xfff) << 20)
+#define SUN6I_DPHY_RX_TIME1_LP_RX_ULPS_WP(n) ((n) & 0xf)
+
+#define SUN6I_DPHY_RX_TIME2_REG0x38
+#define SUN6I_DPHY_RX_TIME2_HS_RX_ANA1(n) (((n) & 0xff) << 8)
+#define SUN6I_DPHY_RX_TIME2_HS_RX_ANA0(n) ((n) & 0xff)
+
+#define SUN6I_DPHY_RX_TIME3_REG0x40
+#define SUN6I_DPHY_RX_TIME3_LPRST_DLY(n) (((n) & 0x) << 16)
+
#define SUN6I_DPHY_ANA0_REG0x4c
#define SUN6I_DPHY_ANA0_REG_PWSBIT(31)
#define SUN6I_DPHY_ANA0_REG_DMPC BIT(28)
#define SUN6I_DPHY_ANA0_REG_DMPD(n)(((n) & 0xf) << 24)
#define SUN6I_DPHY_ANA0_REG_SLV(n) (((n) & 7) << 12)
#define SUN6I_DPHY_ANA0_REG_DEN(n) (((n) & 0xf) << 8)
+#define SUN6I_DPHY_ANA0_REG_SFB(n) (((n) & 3) << 2)
#define SUN6I_DPHY_ANA1_REG0x50
#define SUN6I_DPHY_ANA1_REG_VTTMODEBIT(31)
@@ -92,6 +117,8 @@ struct sun6i_dphy {
struct phy *phy;
struct phy_configure_opts_mipi_dphy config;
+
+ int submode;
};
static int sun6i_dphy_init(struct phy *phy)
@@ -105,6 +132,18 @@ static int sun6i_dphy_init(struct phy *phy)
return 0;
}
+static int sun6i_dphy_set_mode(struct phy *phy, enum phy_mode mode, int
submode)
+{
+ struct sun6i_dphy *dphy = phy_get_drvdata(phy);
+
+ if (mode != PHY_MODE_MIPI_DPHY)
+ return -EINVAL;
+
+ dphy->submode = submode;
+
+ return 0;
+}
+
static int sun6i_dphy_configure(struct phy *phy, union phy_configure_opts
*opts)
{
struct sun6i_dphy *dphy = phy_get_drvdata(phy);
@@ -119,9 +158,8 @@ static int sun6i_dphy_configure(struct phy *phy, union
phy_configure_opts *opts)
return 0;
}
-static int sun6i_dphy_power_on(struct phy *phy)
+static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy)
{
- struct sun6i_dphy *dphy = phy_get_drvdata(phy);
u8 lanes_mask = GENMASK(dphy->config.lanes - 1, 0);
regmap_write(dphy->regs, SUN6I_DPHY_TX_CTL_REG,
@@ -211,12 +249,129 @@ static int sun6i_dphy_power_on(struct phy *phy)
return 0;
}
+static int sun6i_dphy_rx_power_on(struct sun6i_dphy *dphy)
+{
+ /* Physical clock rate is actually half of symbol rate with DDR. */
+ unsigned long mipi_symbol_rate = dphy->config.hs_clk_rate;
+ unsigned long dphy_clk_rate;
+ unsigned int rx_dly;
+ unsigned int lprst_dly;
+ u32 value;
+
+ dphy_clk_rate = clk_get_rate(dphy->mod_clk);
+ if (!dphy_clk_rate)
+ return -EINVAL;
+
+ /* Hardcoded timing parameters from the Allwinner BSP. */
+ regmap_write(dphy->regs, SUN6I_DPHY_RX_TIME0_REG,
+SUN6I_DPHY_RX_TIME0_HS_RX_SYNC(255) |
+SUN6I_DPHY_RX_TIME0_HS_RX_CLK_MISS(255) |
+SUN6I
[linux-sunxi] [PATCH v4 02/15] phy: Distinguish between Rx and Tx for MIPI D-PHY with submodes
As some D-PHY controllers support both Rx and Tx mode, we need a way for
users to explicitly request one or the other. For instance, Rx mode can
be used along with MIPI CSI-2 while Tx mode can be used with MIPI DSI.
Introduce new MIPI D-PHY PHY submodes to use with PHY_MODE_MIPI_DPHY.
The default (zero value) is kept to Tx so only the rkisp1 driver, which
uses D-PHY in Rx mode, needs to be adapted.
Signed-off-by: Paul Kocialkowski
Acked-by: Helen Koike
---
drivers/staging/media/rkisp1/rkisp1-isp.c | 3 ++-
include/linux/phy/phy-mipi-dphy.h | 13 +
2 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/staging/media/rkisp1/rkisp1-isp.c
b/drivers/staging/media/rkisp1/rkisp1-isp.c
index a9715b0b7264..f1167995688a 100644
--- a/drivers/staging/media/rkisp1/rkisp1-isp.c
+++ b/drivers/staging/media/rkisp1/rkisp1-isp.c
@@ -914,7 +914,8 @@ static int rkisp1_mipi_csi2_start(struct rkisp1_isp *isp,
phy_mipi_dphy_get_default_config(pixel_clock, isp->sink_fmt->bus_width,
sensor->lanes, cfg);
- phy_set_mode(sensor->dphy, PHY_MODE_MIPI_DPHY);
+ phy_set_mode_ext(cdev->dphy, PHY_MODE_MIPI_DPHY,
+PHY_MIPI_DPHY_SUBMODE_RX);
phy_configure(sensor->dphy, );
phy_power_on(sensor->dphy);
diff --git a/include/linux/phy/phy-mipi-dphy.h
b/include/linux/phy/phy-mipi-dphy.h
index a877ffee845d..0f57ef46a8b5 100644
--- a/include/linux/phy/phy-mipi-dphy.h
+++ b/include/linux/phy/phy-mipi-dphy.h
@@ -6,6 +6,19 @@
#ifndef __PHY_MIPI_DPHY_H_
#define __PHY_MIPI_DPHY_H_
+/**
+ * enum phy_mipi_dphy_submode - MIPI D-PHY sub-mode
+ *
+ * A MIPI D-PHY can be used to transmit or receive data.
+ * Since some controllers can support both, the direction to enable is
specified
+ * with the PHY sub-mode. Transmit is assumed by default with phy_set_mode.
+ */
+
+enum phy_mipi_dphy_submode {
+ PHY_MIPI_DPHY_SUBMODE_TX = 0,
+ PHY_MIPI_DPHY_SUBMODE_RX,
+};
+
/**
* struct phy_configure_opts_mipi_dphy - MIPI D-PHY configuration set
*
--
2.29.2
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[linux-sunxi] [PATCH v4 01/15] docs: phy: Add a part about PHY mode and submode
Besides giving pointers to the relevant functions for PHY mode and submode configuration, this clarifies the need to set them before powering on the PHY. Signed-off-by: Paul Kocialkowski Reviewed-by: Maxime Ripard --- Documentation/driver-api/phy/phy.rst | 18 ++ 1 file changed, 18 insertions(+) diff --git a/Documentation/driver-api/phy/phy.rst b/Documentation/driver-api/phy/phy.rst index 8fc1ce0bb905..6cbc72707a49 100644 --- a/Documentation/driver-api/phy/phy.rst +++ b/Documentation/driver-api/phy/phy.rst @@ -195,3 +195,21 @@ DeviceTree Binding The documentation for PHY dt binding can be found @ Documentation/devicetree/bindings/phy/phy-bindings.txt + +PHY Mode and Submode + + +Once a reference to a PHY is obtained by a controller, the PHY can be configured +to a PHY mode and submode. PHY modes are described in the `phy_mode` enum while +submodes are specific to the selected PHY mode. + +Mode and submode configuration is done by calling:: + + int phy_set_mode_ext(struct phy *phy, enum phy_mode mode, int submode); + +If no submode is to be configured, users can call:: + + int phy_set_mode(struct phy *phy, enum phy_mode mode); + +The PHY mode and submode must not be configured after the PHY has already been +powered on. -- 2.29.2 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/20201231142948.3241780-2-paul.kocialkowski%40bootlin.com.
[linux-sunxi] [PATCH v4 00/15] Allwinner MIPI CSI-2 support for A31/V3s/A83T
test VIDIOC_EXPBUF: FAIL test Requests: OK (Not Supported) Total for sun6i-video device /dev/video0: 45, Succeeded: 44, Failed: 1, Warnings: 1 # sun6i-csi + sun8i-a83t-mipi-csi2 + ov8865 v4l2-compliance SHA: not available, 32 bits Compliance test for sun6i-video device /dev/video0: Driver Info: Driver name : sun6i-video Card type: sun6i-csi Bus info : platform:camera Driver version : 5.10.0 Capabilities : 0x8421 Video Capture Streaming Extended Pix Format Device Capabilities Device Caps : 0x0421 Video Capture Streaming Extended Pix Format Media Driver Info: Driver name : sun6i-csi Model: Allwinner Video Capture Device Serial : Bus info : platform:1cb.camera Media version: 5.10.0 Hardware revision: 0x (0) Driver version : 5.10.0 Interface Info: ID : 0x0304 Type : V4L Video Entity Info: ID : 0x0001 (1) Name : sun6i-csi Function : V4L2 I/O Pad 0x0102 : 0: Sink Pad 0x0103 : 1: Sink Link 0x020d: from remote pad 0x108 of entity 'sun8i-a83t-mipi-csi2': Data, Enabled Required ioctls: test MC information (see 'Media Driver Info' above): OK warn: v4l2-compliance.cpp(633): media bus_info 'platform:1cb.camera' differs from V4L2 bus_info 'platform:camera' test VIDIOC_QUERYCAP: OK Allow for multiple opens: test second /dev/video0 open: OK warn: v4l2-compliance.cpp(633): media bus_info 'platform:1cb.camera' differs from V4L2 bus_info 'platform:camera' test VIDIOC_QUERYCAP: OK test VIDIOC_G/S_PRIORITY: OK test for unlimited opens: OK Debug ioctls: test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported) test VIDIOC_LOG_STATUS: OK Input ioctls: test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported) test VIDIOC_G/S_FREQUENCY: OK (Not Supported) test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported) test VIDIOC_ENUMAUDIO: OK (Not Supported) test VIDIOC_G/S/ENUMINPUT: OK test VIDIOC_G/S_AUDIO: OK (Not Supported) Inputs: 1 Audio Inputs: 0 Tuners: 0 Output ioctls: test VIDIOC_G/S_MODULATOR: OK (Not Supported) test VIDIOC_G/S_FREQUENCY: OK (Not Supported) test VIDIOC_ENUMAUDOUT: OK (Not Supported) test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported) test VIDIOC_G/S_AUDOUT: OK (Not Supported) Outputs: 0 Audio Outputs: 0 Modulators: 0 Input/Output configuration ioctls: test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported) test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported) test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported) test VIDIOC_G/S_EDID: OK (Not Supported) Control ioctls (Input 0): warn: v4l2-test-controls.cpp(92): Exposure: (max - min) % step != 0 warn: v4l2-test-controls.cpp(92): Gain: (max - min) % step != 0 warn: v4l2-test-controls.cpp(92): Exposure: (max - min) % step != 0 warn: v4l2-test-controls.cpp(92): Gain: (max - min) % step != 0 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK test VIDIOC_QUERYCTRL: OK test VIDIOC_G/S_CTRL: OK test VIDIOC_G/S/TRY_EXT_CTRLS: OK test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK test VIDIOC_G/S_JPEGCOMP: OK (Not Supported) Standard Controls: 11 Private Controls: 0 Format ioctls (Input 0): test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK test VIDIOC_G/S_PARM: OK (Not Supported) test VIDIOC_G_FBUF: OK (Not Supported) test VIDIOC_G_FMT: OK test VIDIOC_TRY_FMT: OK test VIDIOC_S_FMT: OK test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported) test Cropping: OK (Not Supported) test Composing: OK (Not Supported) test Scaling: OK Codec ioctls (Input 0): test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported) test VIDIOC_G_ENC_INDEX: OK (Not Supported) test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported) Buffer ioctls (Input 0): test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK test VIDIOC_EXPBUF: OK test Requests: OK (Not Supported) Total for sun6i-video device /dev/video0: 45, Succeeded: 45, Failed: 0, Warnings: 6 Paul Kocialkowski (15): docs: phy: Add a part about PHY mode and submode phy: Distinguish between Rx and Tx for MIPI D-PHY with submodes phy: allwinner: phy-sun6i-mipi-dphy: Support D-PHY Rx mode for MIPI CSI-2 media: sun6i-csi: Use common V4L2 format info for storage bpp media: sun6i-csi: Only configure the interface data width for parallel dt-binding
[linux-sunxi] Re: [PATCH v3 09/15] media: sunxi: Add support for the A31 MIPI CSI-2 controller
Hi, On Mon 14 Dec 20, 12:39, Maxime Ripard wrote: > On Fri, Dec 11, 2020 at 04:57:02PM +0100, Paul Kocialkowski wrote: > > +#define sun6i_mipi_csi2_subdev_video(subdev) \ > > + container_of(subdev, struct sun6i_mipi_csi2_video, subdev) > > + > > +#define sun6i_mipi_csi2_video_dev(video) \ > > + container_of(video, struct sun6i_mipi_csi2_dev, video) > > Isn't it a bit unsafe? > > The second subdev and video here is not the variable passed in the macro > but the field in the structure, so any attempt at using those two macros > with anything but a variable named subdev or video will result in a > compilation issue? Yep you're totally right. Will fix in the next revision! Cheers, Paul -- Paul Kocialkowski, Bootlin Embedded Linux and kernel engineering https://bootlin.com -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/X%2B3KBO6o5HVRh12e%40aptenodytes. signature.asc Description: PGP signature
[linux-sunxi] [PATCH v3 15/15] MAINTAINERS: Add entry for the Allwinner A83T MIPI CSI-2 bridge
Add myself as maintainer of the A83T MIPI CSI-2 bridge media driver. Signed-off-by: Paul Kocialkowski --- MAINTAINERS | 8 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index a1352171778b..3b48612657b6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -717,6 +717,14 @@ T: git git://linuxtv.org/media_tree.git F: Documentation/devicetree/bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml F: drivers/media/platform/sunxi/sun6i-mipi-csi2/ +ALLWINNER A83T MIPI CSI-2 BRIDGE +M: Paul Kocialkowski +L: linux-me...@vger.kernel.org +S: Maintained +T: git git://linuxtv.org/media_tree.git +F: Documentation/devicetree/bindings/media/allwinner,sun8i-a83t-mipi-csi2.yaml +F: drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/ + ALLWINNER CPUFREQ DRIVER M: Yangtao Li L: linux...@vger.kernel.org -- 2.29.2 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/20201211155708.154710-16-paul.kocialkowski%40bootlin.com.
[linux-sunxi] [PATCH v3 14/15] ARM: dts: sun8i: a83t: Add MIPI CSI-2 controller node
MIPI CSI-2 is supported on the A83T with a dedicated controller that
covers both the protocol and D-PHY. It can be connected to the CSI
interface as a V4L2 subdev through the fwnode graph.
This is not done by default since connecting the bridge without a
subdev attached to it will cause a failure on the CSI driver.
Signed-off-by: Paul Kocialkowski
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 26 ++
1 file changed, 26 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index c010b27fdb6a..d6d55c12b995 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -1066,6 +1066,32 @@ csi_in: port {
};
};
+ mipi_csi2: csi@1cb1000 {
+ compatible = "allwinner,sun8i-a83t-mipi-csi2";
+ reg = <0x01cb1000 0x1000>;
+ interrupts = ;
+ clocks = < CLK_BUS_CSI>,
+< CLK_CSI_SCLK>,
+< CLK_MIPI_CSI>,
+< CLK_CSI_MISC>;
+ clock-names = "bus", "mod", "mipi", "misc";
+ resets = < RST_BUS_CSI>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mipi_csi2_in: port@0 {
+ reg = <0>;
+ };
+
+ mipi_csi2_out: port@1 {
+ reg = <1>;
+ };
+ };
+ };
+
hdmi: hdmi@1ee {
compatible = "allwinner,sun8i-a83t-dw-hdmi";
reg = <0x01ee 0x1>;
--
2.29.2
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[linux-sunxi] [PATCH v3 13/15] media: sunxi: Add support for the A83T MIPI CSI-2 controller
The A83T supports MIPI CSI-2 with a composite controller, covering
both the protocol logic and the D-PHY implementation. This controller
seems to be found on the A83T only and probably was abandoned since.
This implementation splits the protocol and D-PHY registers and
uses the PHY framework internally. The D-PHY is not registered as a
standalone PHY driver since it cannot be used with any other
controller.
There are a few notable points about the controller:
- The initialisation sequence involes writing specific magic init
values that do not seem to make any particular sense given the
concerned register fields;
- Interrupts appear to be hitting regardless of the interrupt mask
registers, which can cause a serious flood when transmission errors
occur.
Only 8-bit and 10-bit Bayer formats are currently supported.
While up to 4 internal channels to the CSI controller exist, only one
is currently supported by this implementation.
This work is based on the first version of the driver submitted by
Kévin L'hôpital, which was adapted to mainline from the Allwinner BSP.
This version integrates MIPI CSI-2 support as a standalone V4L2 subdev
instead of merging it in the sun6i-csi driver.
It was tested on a Banana Pi M3 board with an OV8865 sensor in a 4-lane
configuration.
Signed-off-by: Paul Kocialkowski
---
arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts | 2 +-
drivers/media/platform/sunxi/Kconfig | 1 +
drivers/media/platform/sunxi/Makefile | 1 +
.../sunxi/sun8i-a83t-mipi-csi2/Kconfig| 11 +
.../sunxi/sun8i-a83t-mipi-csi2/Makefile | 4 +
.../sun8i-a83t-mipi-csi2/sun8i_a83t_dphy.c| 92 +++
.../sun8i-a83t-mipi-csi2/sun8i_a83t_dphy.h| 39 ++
.../sun8i_a83t_mipi_csi2.c| 657 ++
.../sun8i_a83t_mipi_csi2.h| 197 ++
9 files changed, 1003 insertions(+), 1 deletion(-)
create mode 100644 drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/Kconfig
create mode 100644 drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/Makefile
create mode 100644
drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_dphy.c
create mode 100644
drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_dphy.h
create mode 100644
drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_mipi_csi2.c
create mode 100644
drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_mipi_csi2.h
diff --git a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
index b437eaeb91e9..bebe843a069b 100644
--- a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
@@ -151,7 +151,7 @@ port@1 {
csi_in_mipi_csi2: endpoint {
remote-endpoint = <_csi2_out_csi>;
- }
+ };
};
};
};
diff --git a/drivers/media/platform/sunxi/Kconfig
b/drivers/media/platform/sunxi/Kconfig
index 9684e07454ad..db4c07be7e4c 100644
--- a/drivers/media/platform/sunxi/Kconfig
+++ b/drivers/media/platform/sunxi/Kconfig
@@ -3,3 +3,4 @@
source "drivers/media/platform/sunxi/sun4i-csi/Kconfig"
source "drivers/media/platform/sunxi/sun6i-csi/Kconfig"
source "drivers/media/platform/sunxi/sun6i-mipi-csi2/Kconfig"
+source "drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/Kconfig"
diff --git a/drivers/media/platform/sunxi/Makefile
b/drivers/media/platform/sunxi/Makefile
index 887a7cae8fca..9aa01cb01883 100644
--- a/drivers/media/platform/sunxi/Makefile
+++ b/drivers/media/platform/sunxi/Makefile
@@ -3,5 +3,6 @@
obj-y += sun4i-csi/
obj-y += sun6i-csi/
obj-y += sun6i-mipi-csi2/
+obj-y += sun8i-a83t-mipi-csi2/
obj-y += sun8i-di/
obj-y += sun8i-rotate/
diff --git a/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/Kconfig
b/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/Kconfig
new file mode 100644
index ..60e7a9c41065
--- /dev/null
+++ b/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/Kconfig
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-only
+config VIDEO_SUN8I_A83T_MIPI_CSI2
+ tristate "Allwinner A83T MIPI CSI-2 Controller and D-PHY Driver"
+ depends on ARCH_SUNXI || COMPILE_TEST
+ depends on PM && COMMON_CLK && VIDEO_V4L2
+ select REGMAP_MMIO
+ select MEDIA_CONTROLLER
+ select VIDEO_V4L2_SUBDEV_API
+ select V4L2_FWNODE
+ help
+ Support for the Allwinner A83T MIPI CSI-2 Controller and D-PHY.
diff --git a/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/Makefile
b/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/Makefile
new file mode 100644
index ..1427d15a879a
--- /dev/null
+++ b/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+s
[linux-sunxi] [PATCH v3 12/15] dt-bindings: media: Add A83T MIPI CSI-2 bindings documentation
This introduces YAML bindings documentation for the A83T MIPI CSI-2
controller.
Signed-off-by: Paul Kocialkowski
Reviewed-by: Rob Herring
---
.../media/allwinner,sun8i-a83t-mipi-csi2.yaml | 147 ++
1 file changed, 147 insertions(+)
create mode 100644
Documentation/devicetree/bindings/media/allwinner,sun8i-a83t-mipi-csi2.yaml
diff --git
a/Documentation/devicetree/bindings/media/allwinner,sun8i-a83t-mipi-csi2.yaml
b/Documentation/devicetree/bindings/media/allwinner,sun8i-a83t-mipi-csi2.yaml
new file mode 100644
index ..e607fae7d85e
--- /dev/null
+++
b/Documentation/devicetree/bindings/media/allwinner,sun8i-a83t-mipi-csi2.yaml
@@ -0,0 +1,147 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/allwinner,sun8i-a83t-mipi-csi2.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Allwinner A83T MIPI CSI-2 Device Tree Bindings
+
+maintainers:
+ - Paul Kocialkowski
+
+properties:
+ compatible:
+const: allwinner,sun8i-a83t-mipi-csi2
+
+ reg:
+maxItems: 1
+
+ interrupts:
+maxItems: 1
+
+ clocks:
+items:
+ - description: Bus Clock
+ - description: Module Clock
+ - description: MIPI-specific Clock
+ - description: Misc CSI Clock
+
+ clock-names:
+items:
+ - const: bus
+ - const: mod
+ - const: mipi
+ - const: misc
+
+ resets:
+maxItems: 1
+
+ # See ./video-interfaces.txt for details
+ ports:
+type: object
+
+properties:
+ port@0:
+type: object
+description: Input port, connect to a MIPI CSI-2 sensor
+
+properties:
+ reg:
+const: 0
+
+ endpoint:
+type: object
+
+properties:
+ remote-endpoint: true
+
+ clock-lanes:
+maxItems: 1
+
+ data-lanes:
+minItems: 1
+maxItems: 4
+
+required:
+ - data-lanes
+ - remote-endpoint
+
+required:
+ - endpoint
+
+additionalProperties: false
+
+ port@1:
+type: object
+description: Output port, connect to a CSI controller
+
+properties:
+ reg:
+const: 1
+
+ endpoint:
+type: object
+
+properties:
+ remote-endpoint: true
+
+required:
+ - remote-endpoint
+
+required:
+ - endpoint
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - resets
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+#include
+#include
+
+mipi_csi2: csi@1cb1000 {
+compatible = "allwinner,sun8i-a83t-mipi-csi2";
+reg = <0x01cb1000 0x1000>;
+interrupts = ;
+clocks = < CLK_BUS_CSI>,
+ < CLK_CSI_SCLK>,
+ < CLK_MIPI_CSI>,
+ < CLK_CSI_MISC>;
+clock-names = "bus", "mod", "mipi", "misc";
+resets = < RST_BUS_CSI>;
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+mipi_csi2_in: port@0 {
+reg = <0>;
+
+mipi_csi2_in_ov8865: endpoint {
+data-lanes = <1 2 3 4>;
+
+remote-endpoint = <_out_mipi_csi2>;
+};
+};
+
+mipi_csi2_out: port@1 {
+reg = <1>;
+
+mipi_csi2_out_csi: endpoint {
+remote-endpoint = <_in_mipi_csi2>;
+};
+};
+};
+};
+
+...
--
2.29.2
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[linux-sunxi] [PATCH v3 11/15] MAINTAINERS: Add entry for the Allwinner A31 MIPI CSI-2 bridge
Add myself as maintainer of the A31 MIPI CSI-2 bridge media driver. Signed-off-by: Paul Kocialkowski --- MAINTAINERS | 8 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 0644128640fb..a1352171778b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -709,6 +709,14 @@ T: git git://linuxtv.org/media_tree.git F: Documentation/devicetree/bindings/media/allwinner,sun4i-a10-csi.yaml F: drivers/media/platform/sunxi/sun4i-csi/ +ALLWINNER A31 MIPI CSI-2 BRIDGE +M: Paul Kocialkowski +L: linux-me...@vger.kernel.org +S: Maintained +T: git git://linuxtv.org/media_tree.git +F: Documentation/devicetree/bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml +F: drivers/media/platform/sunxi/sun6i-mipi-csi2/ + ALLWINNER CPUFREQ DRIVER M: Yangtao Li L: linux...@vger.kernel.org -- 2.29.2 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/20201211155708.154710-12-paul.kocialkowski%40bootlin.com.
[linux-sunxi] [PATCH v3 10/15] ARM: dts: sun8i: v3s: Add nodes for MIPI CSI-2 support
MIPI CSI-2 is supported on the V3s with an A31-based MIPI CSI-2 bridge
controller. The controller uses a separate D-PHY, which is the same
that is otherwise used for MIPI DSI, but used in Rx mode.
On the V3s, the CSI0 controller is dedicated to MIPI CSI-2 as it does
not have access to any parallel interface pins.
Add all the necessary nodes (CSI0, MIPI CSI-2 bridge and D-PHY) to
support the MIPI CSI-2 interface.
Note that a fwnode graph link is created between CSI0 and MIPI CSI-2
even when no sensor is connected. This will result in a probe failure
for the controller as long as no sensor is connected but this is fine
since no other interface is available.
Signed-off-by: Paul Kocialkowski
---
arch/arm/boot/dts/sun8i-v3s.dtsi | 67
1 file changed, 67 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi
index 7b2d684aeb97..b7f2bcd25c86 100644
--- a/arch/arm/boot/dts/sun8i-v3s.dtsi
+++ b/arch/arm/boot/dts/sun8i-v3s.dtsi
@@ -530,6 +530,31 @@ spi0: spi@1c68000 {
#size-cells = <0>;
};
+ csi0: camera@1cb {
+ compatible = "allwinner,sun8i-v3s-csi";
+ reg = <0x01cb 0x1000>;
+ interrupts = ;
+ clocks = < CLK_BUS_CSI>,
+< CLK_CSI1_SCLK>,
+< CLK_DRAM_CSI>;
+ clock-names = "bus", "mod", "ram";
+ resets = < RST_BUS_CSI>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <1>;
+
+ csi0_in_mipi_csi2: endpoint {
+ remote-endpoint =
<_csi2_out_csi0>;
+ };
+ };
+ };
+ };
+
csi1: camera@1cb4000 {
compatible = "allwinner,sun8i-v3s-csi";
reg = <0x01cb4000 0x3000>;
@@ -552,5 +577,47 @@ gic: interrupt-controller@1c81000 {
#interrupt-cells = <3>;
interrupts = ;
};
+
+ mipi_csi2: csi@1cb1000 {
+ compatible = "allwinner,sun8i-v3s-mipi-csi2",
+"allwinner,sun6i-a31-mipi-csi2";
+ reg = <0x01cb1000 0x1000>;
+ interrupts = ;
+ clocks = < CLK_BUS_CSI>,
+< CLK_CSI1_SCLK>;
+ clock-names = "bus", "mod";
+ resets = < RST_BUS_CSI>;
+ status = "disabled";
+
+ phys = <>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mipi_csi2_in: port@0 {
+ reg = <0>;
+ };
+
+ mipi_csi2_out: port@1 {
+ reg = <1>;
+
+ mipi_csi2_out_csi0: endpoint {
+ remote-endpoint =
<_in_mipi_csi2>;
+ };
+ };
+ };
+ };
+
+ dphy: d-phy@1cb2000 {
+ compatible = "allwinner,sun6i-a31-mipi-dphy";
+ reg = <0x01cb2000 0x1000>;
+ clocks = < CLK_BUS_CSI>,
+< CLK_MIPI_CSI>;
+ clock-names = "bus", "mod";
+ resets = < RST_BUS_CSI>;
+ status = "disabled";
+ #phy-cells = <0>;
+ };
};
};
--
2.29.2
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[linux-sunxi] [PATCH v3 09/15] media: sunxi: Add support for the A31 MIPI CSI-2 controller
The A31 MIPI CSI-2 controller is a dedicated MIPI CSI-2 bridge
found on Allwinner SoCs such as the A31 and V3/V3s.
It is a standalone block, connected to the CSI controller on one side
and to the MIPI D-PHY block on the other. It has a dedicated address
space, interrupt line and clock.
It is represented as a V4L2 subdev to the CSI controller and takes a
MIPI CSI-2 sensor as its own subdev, all using the fwnode graph and
media controller API.
Only 8-bit and 10-bit Bayer formats are currently supported.
While up to 4 internal channels to the CSI controller exist, only one
is currently supported by this implementation.
Signed-off-by: Paul Kocialkowski
---
drivers/media/platform/sunxi/Kconfig | 1 +
drivers/media/platform/sunxi/Makefile | 1 +
.../platform/sunxi/sun6i-mipi-csi2/Kconfig| 12 +
.../platform/sunxi/sun6i-mipi-csi2/Makefile | 4 +
.../sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.c | 590 ++
.../sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.h | 117
6 files changed, 725 insertions(+)
create mode 100644 drivers/media/platform/sunxi/sun6i-mipi-csi2/Kconfig
create mode 100644 drivers/media/platform/sunxi/sun6i-mipi-csi2/Makefile
create mode 100644
drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.c
create mode 100644
drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.h
diff --git a/drivers/media/platform/sunxi/Kconfig
b/drivers/media/platform/sunxi/Kconfig
index 7151cc249afa..9684e07454ad 100644
--- a/drivers/media/platform/sunxi/Kconfig
+++ b/drivers/media/platform/sunxi/Kconfig
@@ -2,3 +2,4 @@
source "drivers/media/platform/sunxi/sun4i-csi/Kconfig"
source "drivers/media/platform/sunxi/sun6i-csi/Kconfig"
+source "drivers/media/platform/sunxi/sun6i-mipi-csi2/Kconfig"
diff --git a/drivers/media/platform/sunxi/Makefile
b/drivers/media/platform/sunxi/Makefile
index fc537c9f5ca9..887a7cae8fca 100644
--- a/drivers/media/platform/sunxi/Makefile
+++ b/drivers/media/platform/sunxi/Makefile
@@ -2,5 +2,6 @@
obj-y += sun4i-csi/
obj-y += sun6i-csi/
+obj-y += sun6i-mipi-csi2/
obj-y += sun8i-di/
obj-y += sun8i-rotate/
diff --git a/drivers/media/platform/sunxi/sun6i-mipi-csi2/Kconfig
b/drivers/media/platform/sunxi/sun6i-mipi-csi2/Kconfig
new file mode 100644
index ..47f1bb0779a8
--- /dev/null
+++ b/drivers/media/platform/sunxi/sun6i-mipi-csi2/Kconfig
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-only
+config VIDEO_SUN6I_MIPI_CSI2
+ tristate "Allwinner A31 MIPI CSI-2 Controller Driver"
+ depends on ARCH_SUNXI || COMPILE_TEST
+ depends on PM && COMMON_CLK && VIDEO_V4L2
+ select REGMAP_MMIO
+ select PHY_SUN6I_MIPI_DPHY
+ select MEDIA_CONTROLLER
+ select VIDEO_V4L2_SUBDEV_API
+ select V4L2_FWNODE
+ help
+ Support for the Allwinner A31 MIPI CSI-2 Controller.
diff --git a/drivers/media/platform/sunxi/sun6i-mipi-csi2/Makefile
b/drivers/media/platform/sunxi/sun6i-mipi-csi2/Makefile
new file mode 100644
index ..14e4e03818b5
--- /dev/null
+++ b/drivers/media/platform/sunxi/sun6i-mipi-csi2/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+sun6i-mipi-csi2-y += sun6i_mipi_csi2.o
+
+obj-$(CONFIG_VIDEO_SUN6I_MIPI_CSI2) += sun6i-mipi-csi2.o
diff --git a/drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.c
b/drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.c
new file mode 100644
index ..87307beda4cf
--- /dev/null
+++ b/drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.c
@@ -0,0 +1,590 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 Bootlin
+ * Author: Paul Kocialkowski
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "sun6i_mipi_csi2.h"
+
+#define MODULE_NAME"sun6i-mipi-csi2"
+
+static const u32 sun6i_mipi_csi2_mbus_codes[] = {
+ MEDIA_BUS_FMT_SBGGR8_1X8,
+ MEDIA_BUS_FMT_SGBRG8_1X8,
+ MEDIA_BUS_FMT_SGRBG8_1X8,
+ MEDIA_BUS_FMT_SRGGB8_1X8,
+ MEDIA_BUS_FMT_SBGGR10_1X10,
+ MEDIA_BUS_FMT_SGBRG10_1X10,
+ MEDIA_BUS_FMT_SGRBG10_1X10,
+ MEDIA_BUS_FMT_SRGGB10_1X10,
+};
+
+/* Video */
+
+static int sun6i_mipi_csi2_s_stream(struct v4l2_subdev *subdev, int on)
+{
+ struct sun6i_mipi_csi2_video *video =
+ sun6i_mipi_csi2_subdev_video(subdev);
+ struct sun6i_mipi_csi2_dev *cdev = sun6i_mipi_csi2_video_dev(video);
+ struct v4l2_subdev *remote_subdev = video->remote_subdev;
+ struct v4l2_fwnode_bus_mipi_csi2 *bus_mipi_csi2 =
+ >endpoint.bus.mipi_csi2;
+ union phy_configure_opts dphy_opts = { 0 };
+ struct phy_configure_opts_mipi_dphy *dphy_cfg = _opts.mipi_dphy;
+ struct regmap *regmap = cdev->regmap;
+ struct v4l2_ctrl *ct
[linux-sunxi] [PATCH v3 08/15] dt-bindings: media: Add A31 MIPI CSI-2 bindings documentation
This introduces YAML bindings documentation for the A31 MIPI CSI-2
controller.
Signed-off-by: Paul Kocialkowski
---
.../media/allwinner,sun6i-a31-mipi-csi2.yaml | 149 ++
1 file changed, 149 insertions(+)
create mode 100644
Documentation/devicetree/bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml
diff --git
a/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml
b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml
new file mode 100644
index ..4d0bab541da1
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml
@@ -0,0 +1,149 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/allwinner,sun6i-a31-mipi-csi2.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Allwinner A31 MIPI CSI-2 Device Tree Bindings
+
+maintainers:
+ - Paul Kocialkowski
+
+properties:
+ compatible:
+oneOf:
+ - const: allwinner,sun6i-a31-mipi-csi2
+ - items:
+ - const: allwinner,sun8i-v3s-mipi-csi2
+ - const: allwinner,sun6i-a31-mipi-csi2
+
+ reg:
+maxItems: 1
+
+ interrupts:
+maxItems: 1
+
+ clocks:
+items:
+ - description: Bus Clock
+ - description: Module Clock
+
+ clock-names:
+items:
+ - const: bus
+ - const: mod
+
+ phys:
+items:
+ - description: MIPI D-PHY
+
+ resets:
+maxItems: 1
+
+ # See ./video-interfaces.txt for details
+ ports:
+type: object
+
+properties:
+ port@0:
+type: object
+description: Input port, connect to a MIPI CSI-2 sensor
+
+properties:
+ reg:
+const: 0
+
+ endpoint:
+type: object
+
+properties:
+ remote-endpoint: true
+
+ data-lanes:
+minItems: 1
+maxItems: 4
+
+required:
+ - data-lanes
+ - remote-endpoint
+
+required:
+ - endpoint
+
+additionalProperties: false
+
+ port@1:
+type: object
+description: Output port, connect to a CSI controller
+
+properties:
+ reg:
+const: 1
+
+ endpoint:
+type: object
+
+properties:
+ remote-endpoint: true
+
+required:
+ - remote-endpoint
+
+required:
+ - endpoint
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - resets
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+#include
+#include
+
+mipi_csi2: csi@1cb1000 {
+compatible = "allwinner,sun8i-v3s-mipi-csi2",
+ "allwinner,sun6i-a31-mipi-csi2";
+reg = <0x01cb1000 0x1000>;
+interrupts = ;
+clocks = < CLK_BUS_CSI>,
+ < CLK_CSI1_SCLK>;
+clock-names = "bus", "mod";
+resets = < RST_BUS_CSI>;
+
+phys = <>;
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+mipi_csi2_in: port@0 {
+reg = <0>;
+
+mipi_csi2_in_ov5648: endpoint {
+data-lanes = <1 2 3 4>;
+
+remote-endpoint = <_out_mipi_csi2>;
+};
+};
+
+mipi_csi2_out: port@1 {
+reg = <1>;
+
+mipi_csi2_out_csi0: endpoint {
+remote-endpoint = <_in_mipi_csi2>;
+};
+};
+};
+};
+
+...
--
2.29.2
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[linux-sunxi] [PATCH v3 07/15] media: sun6i-csi: Add support for MIPI CSI-2 bridge input
The A31 CSI controller supports a MIPI CSI-2 bridge input, which has
its own dedicated port in the fwnode graph.
Support for this input is added with this change:
- two pads are defined for the media entity instead of one
and only one needs to be connected at a time;
- the pads currently match the fwnode graph representation;
- links are created between our pads and the subdevs for each
interface and are no longer immutable so that userspace can select
which interface to use in case both are bound to a subdev;
- fwnode endpoints are parsed and stored for each interface;
- the active subdev (and fwnode endpoint) is retrieved when validating
the media link at stream on time and cleared at stream off;
- an error is raised if both links are active at the same time;
- the MIPI interface bit is set if the MIPI CSI-2 bridge endpoint is
active.
In the future, the media entity representation might evolve to:
- distinguish the internal parallel bridge and data formatter;
- represent each of the 4 internal channels that can exist between
the parallel bridge (for BT656 time-multiplex) and MIPI CSI-2
(internal channels can be mapped to virtual channels);
- connect the controller's output to the ISP instead of its
DMA engine.
Finally note that the MIPI CSI-2 bridges should not be linked in
the fwnode graph unless they have a sensor subdev attached.
Signed-off-by: Paul Kocialkowski
---
.../platform/sunxi/sun6i-csi/sun6i_csi.c | 123 ++
.../platform/sunxi/sun6i-csi/sun6i_csi.h | 3 -
.../platform/sunxi/sun6i-csi/sun6i_video.c| 53
.../platform/sunxi/sun6i-csi/sun6i_video.h| 7 +-
4 files changed, 135 insertions(+), 51 deletions(-)
diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
index f1150de94e98..481181038e1e 100644
--- a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
+++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
@@ -52,15 +52,16 @@ bool sun6i_csi_is_format_supported(struct sun6i_csi *csi,
u32 pixformat, u32 mbus_code)
{
struct sun6i_csi_dev *sdev = sun6i_csi_to_dev(csi);
+ struct v4l2_fwnode_endpoint *endpoint = sdev->csi.video.source_endpoint;
/*
* Some video receivers have the ability to be compatible with
* 8bit and 16bit bus width.
* Identify the media bus format from device tree.
*/
- if ((sdev->csi.v4l2_ep.bus_type == V4L2_MBUS_PARALLEL
-|| sdev->csi.v4l2_ep.bus_type == V4L2_MBUS_BT656)
-&& sdev->csi.v4l2_ep.bus.parallel.bus_width == 16) {
+ if ((endpoint->bus_type == V4L2_MBUS_PARALLEL
+|| endpoint->bus_type == V4L2_MBUS_BT656)
+&& endpoint->bus.parallel.bus_width == 16) {
switch (pixformat) {
case V4L2_PIX_FMT_HM12:
case V4L2_PIX_FMT_NV12:
@@ -373,7 +374,7 @@ static enum csi_input_seq get_csi_input_seq(struct
sun6i_csi_dev *sdev,
static void sun6i_csi_setup_bus(struct sun6i_csi_dev *sdev)
{
- struct v4l2_fwnode_endpoint *endpoint = >csi.v4l2_ep;
+ struct v4l2_fwnode_endpoint *endpoint = sdev->csi.video.source_endpoint;
struct sun6i_csi *csi = >csi;
unsigned char bus_width;
u32 flags;
@@ -459,6 +460,9 @@ static void sun6i_csi_setup_bus(struct sun6i_csi_dev *sdev)
if (flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
cfg |= CSI_IF_CFG_CLK_POL_FALLING_EDGE;
break;
+ case V4L2_MBUS_CSI2_DPHY:
+ cfg |= CSI_IF_CFG_MIPI_IF_MIPI;
+ break;
default:
dev_warn(sdev->dev, "Unsupported bus type: %d\n",
endpoint->bus_type);
@@ -636,11 +640,11 @@ void sun6i_csi_set_stream(struct sun6i_csi *csi, bool
enable)
* Media Controller and V4L2
*/
static int sun6i_csi_link_entity(struct sun6i_csi *csi,
+struct media_pad *sink_pad,
struct media_entity *entity,
-struct fwnode_handle *fwnode)
+struct fwnode_handle *fwnode, bool enabled)
{
struct media_entity *sink;
- struct media_pad *sink_pad;
int src_pad_index;
int ret;
@@ -654,14 +658,12 @@ static int sun6i_csi_link_entity(struct sun6i_csi *csi,
src_pad_index = ret;
sink = >video.vdev.entity;
- sink_pad = >video.pad;
dev_dbg(csi->dev, "creating %s:%u -> %s:%u link\n",
entity->name, src_pad_index, sink->name, sink_pad->index);
ret = media_create_pad_link(entity, src_pad_index, sink,
sink_pad->index,
- MEDIA_LNK_FL_ENABLED |
- MEDIA_LNK_FL_IMMU
[linux-sunxi] [PATCH v3 06/15] dt-bindings: media: sun6i-a31-csi: Add MIPI CSI-2 input port
The A31 CSI controller supports two distinct input interfaces:
parallel and an external MIPI CSI-2 bridge. The parallel interface
is often connected to a set of hardware pins while the MIPI CSI-2
bridge is an internal FIFO-ish link. As a result, these two inputs
are distinguished as two different ports.
Note that only one of the two may be present on a controller instance.
For example, the V3s has one controller dedicated to MIPI-CSI2 and one
dedicated to parallel.
Update the binding with an explicit ports node that holds two distinct
port nodes: one for parallel input and one for MIPI CSI-2.
This is backward-compatible with the single-port approach that was
previously taken for representing the parallel interface port, which
stays enumerated as fwnode port 0.
Note that additional ports may be added in the future, especially to
support feeding the CSI controller's output to the ISP.
Signed-off-by: Paul Kocialkowski
---
.../media/allwinner,sun6i-a31-csi.yaml| 88 ---
1 file changed, 75 insertions(+), 13 deletions(-)
diff --git
a/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-csi.yaml
b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-csi.yaml
index 1fd9b5532a21..77ded77505e9 100644
--- a/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-csi.yaml
+++ b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-csi.yaml
@@ -67,6 +67,62 @@ properties:
additionalProperties: false
+ ports:
+type: object
+
+properties:
+ port@0:
+type: object
+description: Parallel input port, connect to a parallel sensor
+
+properties:
+ reg:
+const: 0
+
+ endpoint:
+type: object
+
+properties:
+ remote-endpoint: true
+
+ bus-width:
+enum: [ 8, 10, 12, 16 ]
+
+ pclk-sample: true
+ hsync-active: true
+ vsync-active: true
+
+required:
+ - bus-width
+ - remote-endpoint
+
+required:
+ - endpoint
+
+additionalProperties: false
+
+ port@1:
+type: object
+description: MIPI CSI-2 bridge input port
+
+properties:
+ reg:
+const: 1
+
+ endpoint:
+type: object
+
+properties:
+ remote-endpoint: true
+
+required:
+ - remote-endpoint
+
+required:
+ - endpoint
+
+additionalProperties: false
+
required:
- compatible
- reg
@@ -95,19 +151,25 @@ examples:
"ram";
resets = < RST_BUS_CSI>;
-port {
-/* Parallel bus endpoint */
-csi1_ep: endpoint {
-remote-endpoint = <_ep>;
-bus-width = <16>;
-
-/*
- * If hsync-active/vsync-active are missing,
- * embedded BT.656 sync is used.
- */
- hsync-active = <0>; /* Active low */
- vsync-active = <0>; /* Active low */
- pclk-sample = <1>; /* Rising */
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+port@0 {
+reg = <0>;
+/* Parallel bus endpoint */
+csi1_ep: endpoint {
+remote-endpoint = <_ep>;
+bus-width = <16>;
+
+/*
+ * If hsync-active/vsync-active are missing,
+ * embedded BT.656 sync is used.
+ */
+ hsync-active = <0>; /* Active low */
+ vsync-active = <0>; /* Active low */
+ pclk-sample = <1>; /* Rising */
+};
};
};
};
--
2.29.2
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[linux-sunxi] [PATCH v3 05/15] media: sun6i-csi: Only configure the interface data width for parallel
Bits related to the interface data width are only applicable to the
parallel interface and are irrelevant when the CSI controller is taking
input from the MIPI CSI-2 controller.
In prevision of adding support for this case, set these bits
conditionally so there is no ambiguity. The conditional block is
moved around before the interlaced conditional block for nicer code
symmetry (conditional blocks first) while at it.
Co-developed-by: Kévin L'hôpital
Signed-off-by: Kévin L'hôpital
Signed-off-by: Paul Kocialkowski
---
.../platform/sunxi/sun6i-csi/sun6i_csi.c | 42 +++
1 file changed, 25 insertions(+), 17 deletions(-)
diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
index 531a4cccd14a..f1150de94e98 100644
--- a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
+++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
@@ -378,8 +378,13 @@ static void sun6i_csi_setup_bus(struct sun6i_csi_dev *sdev)
unsigned char bus_width;
u32 flags;
u32 cfg;
+ bool input_parallel = false;
bool input_interlaced = false;
+ if (endpoint->bus_type == V4L2_MBUS_PARALLEL ||
+ endpoint->bus_type == V4L2_MBUS_BT656)
+ input_parallel = true;
+
if (csi->config.field == V4L2_FIELD_INTERLACED
|| csi->config.field == V4L2_FIELD_INTERLACED_TB
|| csi->config.field == V4L2_FIELD_INTERLACED_BT)
@@ -395,6 +400,26 @@ static void sun6i_csi_setup_bus(struct sun6i_csi_dev *sdev)
CSI_IF_CFG_HREF_POL_MASK | CSI_IF_CFG_FIELD_MASK |
CSI_IF_CFG_SRC_TYPE_MASK);
+ if (input_parallel) {
+ switch (bus_width) {
+ case 8:
+ cfg |= CSI_IF_CFG_IF_DATA_WIDTH_8BIT;
+ break;
+ case 10:
+ cfg |= CSI_IF_CFG_IF_DATA_WIDTH_10BIT;
+ break;
+ case 12:
+ cfg |= CSI_IF_CFG_IF_DATA_WIDTH_12BIT;
+ break;
+ case 16: /* No need to configure DATA_WIDTH for 16bit */
+ break;
+ default:
+ dev_warn(sdev->dev, "Unsupported bus width: %u\n",
+bus_width);
+ break;
+ }
+ }
+
if (input_interlaced)
cfg |= CSI_IF_CFG_SRC_TYPE_INTERLACED;
else
@@ -440,23 +465,6 @@ static void sun6i_csi_setup_bus(struct sun6i_csi_dev *sdev)
break;
}
- switch (bus_width) {
- case 8:
- cfg |= CSI_IF_CFG_IF_DATA_WIDTH_8BIT;
- break;
- case 10:
- cfg |= CSI_IF_CFG_IF_DATA_WIDTH_10BIT;
- break;
- case 12:
- cfg |= CSI_IF_CFG_IF_DATA_WIDTH_12BIT;
- break;
- case 16: /* No need to configure DATA_WIDTH for 16bit */
- break;
- default:
- dev_warn(sdev->dev, "Unsupported bus width: %u\n", bus_width);
- break;
- }
-
regmap_write(sdev->regmap, CSI_IF_CFG_REG, cfg);
}
--
2.29.2
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[linux-sunxi] [PATCH v3 04/15] media: sun6i-csi: Use common V4L2 format info for storage bpp
V4L2 has a common helper which can be used for calculating the number
of stored bits per pixels of a given (stored) image format.
Use the helper-returned structure instead of our own switch/case list.
Note that a few formats are not in that list so we keep them as
special cases.
The custom switch/case was also wrong concerning 10/12-bit Bayer
formats, which are aligned to 16 bits in memory. Using the common
helper fixes it.
Fixes: 5cc7522d8965 ("media: sun6i: Add support for Allwinner CSI V3s")
Signed-off-by: Paul Kocialkowski
Acked-by: Maxime Ripard
---
.../platform/sunxi/sun6i-csi/sun6i_csi.h | 55 +++
1 file changed, 20 insertions(+), 35 deletions(-)
diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.h
b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.h
index c626821aaedb..092445f04c60 100644
--- a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.h
+++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.h
@@ -86,53 +86,38 @@ void sun6i_csi_update_buf_addr(struct sun6i_csi *csi,
dma_addr_t addr);
*/
void sun6i_csi_set_stream(struct sun6i_csi *csi, bool enable);
-/* get bpp form v4l2 pixformat */
+/* get memory storage bpp from v4l2 pixformat */
static inline int sun6i_csi_get_bpp(unsigned int pixformat)
{
+ const struct v4l2_format_info *info;
+ unsigned int i;
+ int bpp = 0;
+
+ /* Handle special cases unknown to V4L2 format info first. */
switch (pixformat) {
- case V4L2_PIX_FMT_SBGGR8:
- case V4L2_PIX_FMT_SGBRG8:
- case V4L2_PIX_FMT_SGRBG8:
- case V4L2_PIX_FMT_SRGGB8:
case V4L2_PIX_FMT_JPEG:
return 8;
- case V4L2_PIX_FMT_SBGGR10:
- case V4L2_PIX_FMT_SGBRG10:
- case V4L2_PIX_FMT_SGRBG10:
- case V4L2_PIX_FMT_SRGGB10:
- return 10;
- case V4L2_PIX_FMT_SBGGR12:
- case V4L2_PIX_FMT_SGBRG12:
- case V4L2_PIX_FMT_SGRBG12:
- case V4L2_PIX_FMT_SRGGB12:
case V4L2_PIX_FMT_HM12:
- case V4L2_PIX_FMT_NV12:
- case V4L2_PIX_FMT_NV21:
- case V4L2_PIX_FMT_YUV420:
- case V4L2_PIX_FMT_YVU420:
return 12;
- case V4L2_PIX_FMT_YUYV:
- case V4L2_PIX_FMT_YVYU:
- case V4L2_PIX_FMT_UYVY:
- case V4L2_PIX_FMT_VYUY:
- case V4L2_PIX_FMT_NV16:
- case V4L2_PIX_FMT_NV61:
- case V4L2_PIX_FMT_YUV422P:
- case V4L2_PIX_FMT_RGB565:
case V4L2_PIX_FMT_RGB565X:
return 16;
- case V4L2_PIX_FMT_RGB24:
- case V4L2_PIX_FMT_BGR24:
- return 24;
- case V4L2_PIX_FMT_RGB32:
- case V4L2_PIX_FMT_BGR32:
- return 32;
- default:
+ }
+
+ info = v4l2_format_info(pixformat);
+ if (!info) {
WARN(1, "Unsupported pixformat: 0x%x\n", pixformat);
- break;
+ return 0;
+ }
+
+ for (i = 0; i < info->comp_planes; i++) {
+ unsigned int hdiv = (i == 0) ? 1 : info->hdiv;
+ unsigned int vdiv = (i == 0) ? 1 : info->vdiv;
+
+ /* We return bits per pixel while V4L2 format info is bytes. */
+ bpp += 8 * info->bpp[i] / hdiv / vdiv;
}
- return 0;
+ return bpp;
}
#endif /* __SUN6I_CSI_H__ */
--
2.29.2
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[linux-sunxi] [PATCH v3 03/15] phy: allwinner: phy-sun6i-mipi-dphy: Support D-PHY Rx mode for MIPI CSI-2
The Allwinner A31 D-PHY supports both Rx and Tx modes. While the latter
is already supported and used for MIPI DSI this adds support for the
former, to be used with MIPI CSI-2.
This implementation is inspired by Allwinner's V3s Linux SDK
implementation, which was used as a documentation base.
Signed-off-by: Paul Kocialkowski
Acked-by: Maxime Ripard
---
drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 164 +++-
1 file changed, 160 insertions(+), 4 deletions(-)
diff --git a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
index 1fa761ba6cbb..0389b6b670d6 100644
--- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
+++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
@@ -24,6 +24,14 @@
#define SUN6I_DPHY_TX_CTL_REG 0x04
#define SUN6I_DPHY_TX_CTL_HS_TX_CLK_CONT BIT(28)
+#define SUN6I_DPHY_RX_CTL_REG 0x08
+#define SUN6I_DPHY_RX_CTL_EN_DBC BIT(31)
+#define SUN6I_DPHY_RX_CTL_RX_CLK_FORCE BIT(24)
+#define SUN6I_DPHY_RX_CTL_RX_D3_FORCE BIT(23)
+#define SUN6I_DPHY_RX_CTL_RX_D2_FORCE BIT(22)
+#define SUN6I_DPHY_RX_CTL_RX_D1_FORCE BIT(21)
+#define SUN6I_DPHY_RX_CTL_RX_D0_FORCE BIT(20)
+
#define SUN6I_DPHY_TX_TIME0_REG0x10
#define SUN6I_DPHY_TX_TIME0_HS_TRAIL(n)(((n) & 0xff) << 24)
#define SUN6I_DPHY_TX_TIME0_HS_PREPARE(n) (((n) & 0xff) << 16)
@@ -44,12 +52,29 @@
#define SUN6I_DPHY_TX_TIME4_HS_TX_ANA1(n) (((n) & 0xff) << 8)
#define SUN6I_DPHY_TX_TIME4_HS_TX_ANA0(n) ((n) & 0xff)
+#define SUN6I_DPHY_RX_TIME0_REG0x30
+#define SUN6I_DPHY_RX_TIME0_HS_RX_SYNC(n) (((n) & 0xff) << 24)
+#define SUN6I_DPHY_RX_TIME0_HS_RX_CLK_MISS(n) (((n) & 0xff) << 16)
+#define SUN6I_DPHY_RX_TIME0_LP_RX(n) (((n) & 0xff) << 8)
+
+#define SUN6I_DPHY_RX_TIME1_REG0x34
+#define SUN6I_DPHY_RX_TIME1_RX_DLY(n) (((n) & 0xfff) << 20)
+#define SUN6I_DPHY_RX_TIME1_LP_RX_ULPS_WP(n) ((n) & 0xf)
+
+#define SUN6I_DPHY_RX_TIME2_REG0x38
+#define SUN6I_DPHY_RX_TIME2_HS_RX_ANA1(n) (((n) & 0xff) << 8)
+#define SUN6I_DPHY_RX_TIME2_HS_RX_ANA0(n) ((n) & 0xff)
+
+#define SUN6I_DPHY_RX_TIME3_REG0x40
+#define SUN6I_DPHY_RX_TIME3_LPRST_DLY(n) (((n) & 0x) << 16)
+
#define SUN6I_DPHY_ANA0_REG0x4c
#define SUN6I_DPHY_ANA0_REG_PWSBIT(31)
#define SUN6I_DPHY_ANA0_REG_DMPC BIT(28)
#define SUN6I_DPHY_ANA0_REG_DMPD(n)(((n) & 0xf) << 24)
#define SUN6I_DPHY_ANA0_REG_SLV(n) (((n) & 7) << 12)
#define SUN6I_DPHY_ANA0_REG_DEN(n) (((n) & 0xf) << 8)
+#define SUN6I_DPHY_ANA0_REG_SFB(n) (((n) & 3) << 2)
#define SUN6I_DPHY_ANA1_REG0x50
#define SUN6I_DPHY_ANA1_REG_VTTMODEBIT(31)
@@ -92,6 +117,8 @@ struct sun6i_dphy {
struct phy *phy;
struct phy_configure_opts_mipi_dphy config;
+
+ int submode;
};
static int sun6i_dphy_init(struct phy *phy)
@@ -105,6 +132,18 @@ static int sun6i_dphy_init(struct phy *phy)
return 0;
}
+static int sun6i_dphy_set_mode(struct phy *phy, enum phy_mode mode, int
submode)
+{
+ struct sun6i_dphy *dphy = phy_get_drvdata(phy);
+
+ if (mode != PHY_MODE_MIPI_DPHY)
+ return -EINVAL;
+
+ dphy->submode = submode;
+
+ return 0;
+}
+
static int sun6i_dphy_configure(struct phy *phy, union phy_configure_opts
*opts)
{
struct sun6i_dphy *dphy = phy_get_drvdata(phy);
@@ -119,9 +158,8 @@ static int sun6i_dphy_configure(struct phy *phy, union
phy_configure_opts *opts)
return 0;
}
-static int sun6i_dphy_power_on(struct phy *phy)
+static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy)
{
- struct sun6i_dphy *dphy = phy_get_drvdata(phy);
u8 lanes_mask = GENMASK(dphy->config.lanes - 1, 0);
regmap_write(dphy->regs, SUN6I_DPHY_TX_CTL_REG,
@@ -211,12 +249,129 @@ static int sun6i_dphy_power_on(struct phy *phy)
return 0;
}
+static int sun6i_dphy_rx_power_on(struct sun6i_dphy *dphy)
+{
+ /* Physical clock rate is actually half of symbol rate with DDR. */
+ unsigned long mipi_symbol_rate = dphy->config.hs_clk_rate;
+ unsigned long dphy_clk_rate;
+ unsigned int rx_dly;
+ unsigned int lprst_dly;
+ u32 value;
+
+ dphy_clk_rate = clk_get_rate(dphy->mod_clk);
+ if (!dphy_clk_rate)
+ return -EINVAL;
+
+ /* Hardcoded timing parameters from the Allwinner BSP. */
+ regmap_write(dphy->regs, SUN6I_DPHY_RX_TIME0_REG,
+SUN6I_DPHY_RX_TIME0_HS_RX_SYNC(255) |
+SUN6I_DPHY_RX_TIME0_HS_RX_CLK_MISS(255) |
+SUN6I
[linux-sunxi] [PATCH v3 02/15] phy: Distinguish between Rx and Tx for MIPI D-PHY with submodes
As some D-PHY controllers support both Rx and Tx mode, we need a way for
users to explicitly request one or the other. For instance, Rx mode can
be used along with MIPI CSI-2 while Tx mode can be used with MIPI DSI.
Introduce new MIPI D-PHY PHY submodes to use with PHY_MODE_MIPI_DPHY.
The default (zero value) is kept to Tx so only the rkisp1 driver, which
uses D-PHY in Rx mode, needs to be adapted.
Signed-off-by: Paul Kocialkowski
Acked-by: Helen Koike
---
drivers/staging/media/rkisp1/rkisp1-isp.c | 3 ++-
include/linux/phy/phy-mipi-dphy.h | 13 +
2 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/staging/media/rkisp1/rkisp1-isp.c
b/drivers/staging/media/rkisp1/rkisp1-isp.c
index a9715b0b7264..f1167995688a 100644
--- a/drivers/staging/media/rkisp1/rkisp1-isp.c
+++ b/drivers/staging/media/rkisp1/rkisp1-isp.c
@@ -914,7 +914,8 @@ static int rkisp1_mipi_csi2_start(struct rkisp1_isp *isp,
phy_mipi_dphy_get_default_config(pixel_clock, isp->sink_fmt->bus_width,
sensor->lanes, cfg);
- phy_set_mode(sensor->dphy, PHY_MODE_MIPI_DPHY);
+ phy_set_mode_ext(cdev->dphy, PHY_MODE_MIPI_DPHY,
+PHY_MIPI_DPHY_SUBMODE_RX);
phy_configure(sensor->dphy, );
phy_power_on(sensor->dphy);
diff --git a/include/linux/phy/phy-mipi-dphy.h
b/include/linux/phy/phy-mipi-dphy.h
index a877ffee845d..0f57ef46a8b5 100644
--- a/include/linux/phy/phy-mipi-dphy.h
+++ b/include/linux/phy/phy-mipi-dphy.h
@@ -6,6 +6,19 @@
#ifndef __PHY_MIPI_DPHY_H_
#define __PHY_MIPI_DPHY_H_
+/**
+ * enum phy_mipi_dphy_submode - MIPI D-PHY sub-mode
+ *
+ * A MIPI D-PHY can be used to transmit or receive data.
+ * Since some controllers can support both, the direction to enable is
specified
+ * with the PHY sub-mode. Transmit is assumed by default with phy_set_mode.
+ */
+
+enum phy_mipi_dphy_submode {
+ PHY_MIPI_DPHY_SUBMODE_TX = 0,
+ PHY_MIPI_DPHY_SUBMODE_RX,
+};
+
/**
* struct phy_configure_opts_mipi_dphy - MIPI D-PHY configuration set
*
--
2.29.2
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[linux-sunxi] [PATCH v3 01/15] docs: phy: Add a part about PHY mode and submode
Besides giving pointers to the relevant functions for PHY mode and submode configuration, this clarifies the need to set them before powering on the PHY. Signed-off-by: Paul Kocialkowski Reviewed-by: Maxime Ripard --- Documentation/driver-api/phy/phy.rst | 18 ++ 1 file changed, 18 insertions(+) diff --git a/Documentation/driver-api/phy/phy.rst b/Documentation/driver-api/phy/phy.rst index 8fc1ce0bb905..6cbc72707a49 100644 --- a/Documentation/driver-api/phy/phy.rst +++ b/Documentation/driver-api/phy/phy.rst @@ -195,3 +195,21 @@ DeviceTree Binding The documentation for PHY dt binding can be found @ Documentation/devicetree/bindings/phy/phy-bindings.txt + +PHY Mode and Submode + + +Once a reference to a PHY is obtained by a controller, the PHY can be configured +to a PHY mode and submode. PHY modes are described in the `phy_mode` enum while +submodes are specific to the selected PHY mode. + +Mode and submode configuration is done by calling:: + + int phy_set_mode_ext(struct phy *phy, enum phy_mode mode, int submode); + +If no submode is to be configured, users can call:: + + int phy_set_mode(struct phy *phy, enum phy_mode mode); + +The PHY mode and submode must not be configured after the PHY has already been +powered on. -- 2.29.2 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/20201211155708.154710-2-paul.kocialkowski%40bootlin.com.
[linux-sunxi] [PATCH v3 00/15] Allwinner MIPI CSI-2 support for A31/V3s/A83T
6i-csi Bus info : platform:camera Driver version : 5.10.0 Capabilities : 0x8421 Video Capture Streaming Extended Pix Format Device Capabilities Device Caps : 0x0421 Video Capture Streaming Extended Pix Format Media Driver Info: Driver name : sun6i-csi Model: Allwinner Video Capture Device Serial : Bus info : platform:1cb.camera Media version: 5.10.0 Hardware revision: 0x (0) Driver version : 5.10.0 Interface Info: ID : 0x0304 Type : V4L Video Entity Info: ID : 0x0001 (1) Name : sun6i-csi Function : V4L2 I/O Pad 0x0102 : 0: Sink Pad 0x0103 : 1: Sink Link 0x020d: from remote pad 0x108 of entity 'sun8i-a83t-mipi-csi2': Data, Enabled Required ioctls: test MC information (see 'Media Driver Info' above): OK warn: v4l2-compliance.cpp(633): media bus_info 'platform:1cb.camera' differs from V4L2 bus_info 'platform:camera' test VIDIOC_QUERYCAP: OK Allow for multiple opens: test second /dev/video0 open: OK warn: v4l2-compliance.cpp(633): media bus_info 'platform:1cb.camera' differs from V4L2 bus_info 'platform:camera' test VIDIOC_QUERYCAP: OK test VIDIOC_G/S_PRIORITY: OK test for unlimited opens: OK Debug ioctls: test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported) test VIDIOC_LOG_STATUS: OK Input ioctls: test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported) test VIDIOC_G/S_FREQUENCY: OK (Not Supported) test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported) test VIDIOC_ENUMAUDIO: OK (Not Supported) test VIDIOC_G/S/ENUMINPUT: OK test VIDIOC_G/S_AUDIO: OK (Not Supported) Inputs: 1 Audio Inputs: 0 Tuners: 0 Output ioctls: test VIDIOC_G/S_MODULATOR: OK (Not Supported) test VIDIOC_G/S_FREQUENCY: OK (Not Supported) test VIDIOC_ENUMAUDOUT: OK (Not Supported) test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported) test VIDIOC_G/S_AUDOUT: OK (Not Supported) Outputs: 0 Audio Outputs: 0 Modulators: 0 Input/Output configuration ioctls: test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported) test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported) test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported) test VIDIOC_G/S_EDID: OK (Not Supported) Control ioctls (Input 0): warn: v4l2-test-controls.cpp(92): Exposure: (max - min) % step != 0 warn: v4l2-test-controls.cpp(92): Gain: (max - min) % step != 0 warn: v4l2-test-controls.cpp(92): Exposure: (max - min) % step != 0 warn: v4l2-test-controls.cpp(92): Gain: (max - min) % step != 0 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK test VIDIOC_QUERYCTRL: OK test VIDIOC_G/S_CTRL: OK test VIDIOC_G/S/TRY_EXT_CTRLS: OK test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK test VIDIOC_G/S_JPEGCOMP: OK (Not Supported) Standard Controls: 11 Private Controls: 0 Format ioctls (Input 0): test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK test VIDIOC_G/S_PARM: OK (Not Supported) test VIDIOC_G_FBUF: OK (Not Supported) test VIDIOC_G_FMT: OK test VIDIOC_TRY_FMT: OK test VIDIOC_S_FMT: OK test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported) test Cropping: OK (Not Supported) test Composing: OK (Not Supported) test Scaling: OK Codec ioctls (Input 0): test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported) test VIDIOC_G_ENC_INDEX: OK (Not Supported) test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported) Buffer ioctls (Input 0): test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK test VIDIOC_EXPBUF: OK test Requests: OK (Not Supported) Total for sun6i-video device /dev/video0: 45, Succeeded: 45, Failed: 0, Warnings: 6 Paul Kocialkowski (15): docs: phy: Add a part about PHY mode and submode phy: Distinguish between Rx and Tx for MIPI D-PHY with submodes phy: allwinner: phy-sun6i-mipi-dphy: Support D-PHY Rx mode for MIPI CSI-2 media: sun6i-csi: Use common V4L2 format info for storage bpp media: sun6i-csi: Only configure the interface data width for parallel dt-bindings: media: sun6i-a31-csi: Add MIPI CSI-2 input port media: sun6i-csi: Add support for MIPI CSI-2 bridge input dt-bindings: media: Add A31 MIPI CSI-2 bindings documentation media: sunxi: Add support for the A31 MIPI CSI-2 controller ARM: dts: sun8i: v3s: Add nodes for MIPI CSI-2 support MAINTAINERS: Add entry for the Allwinner A31 MIPI CSI-2 bridge dt-binding
[linux-sunxi] Re: [PATCH v2 13/19] media: sunxi: Add support for the A31 MIPI CSI-2 controller
Hi,
On Wed 02 Dec 20, 16:48, Maxime Ripard wrote:
> On Wed, Dec 02, 2020 at 03:44:47PM +0100, Paul Kocialkowski wrote:
> > > > +static int __maybe_unused sun6i_mipi_csi2_suspend(struct device *dev)
> > > > +{
> > > > + struct sun6i_mipi_csi2_dev *cdev = dev_get_drvdata(dev);
> > > > +
> > > > + clk_disable_unprepare(cdev->clk_mod);
> > > > + clk_disable_unprepare(cdev->clk_bus);
> > > > + reset_control_assert(cdev->reset);
> > > > +
> > > > + return 0;
> > > > +}
> > > > +
> > > > +static int __maybe_unused sun6i_mipi_csi2_resume(struct device *dev)
> > > > +{
> > > > + struct sun6i_mipi_csi2_dev *cdev = dev_get_drvdata(dev);
> > > > + int ret;
> > > > +
> > > > + ret = reset_control_deassert(cdev->reset);
> > > > + if (ret) {
> > > > + dev_err(cdev->dev, "failed to deassert reset\n");
> > > > + return ret;
> > > > + }
> > > > +
> > > > + ret = clk_prepare_enable(cdev->clk_bus);
> > > > + if (ret) {
> > > > + dev_err(cdev->dev, "failed to enable bus clock\n");
> > > > + goto error_reset;
> > > > + }
> > > > +
> > > > + ret = clk_prepare_enable(cdev->clk_mod);
> > > > + if (ret) {
> > > > + dev_err(cdev->dev, "failed to enable module clock\n");
> > > > + goto error_clk_bus;
> > > > + }
> > > > +
> > > > + return 0;
> > > > +
> > > > +error_clk_bus:
> > > > + clk_disable_unprepare(cdev->clk_bus);
> > > > +
> > > > +error_reset:
> > > > + reset_control_assert(cdev->reset);
> > > > +
> > > > + return ret;
> > > > +}
> > >
> > > I'm guessing you set the __maybe_unused attribute because you're using
> > > SET_RUNTIME_PM_OPS, but what would happen if runtime_pm isn't selected?
> > > It looks like you don't handle that case.
> >
> > Indeed, __maybe_unused is because of the conditional definition of
> > SET_RUNTIME_PM_OPS. If CONFIG_PM is not selected, then I guess the
> > controller
> > wouldn't be powered and wouldn't work. So I should definitely add a Kconfig
> > dependency on PM then, right?
>
> There's two ways we can do it. What you suggested is one, the other is
> to have something like our SPI driver to call directly the resume
> function if there's no runtime pm support.
Understood! I think I'll stick to depending on PM (unless you prefer not to)
but it's good to know.
Cheers,
Paul
--
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Embedded Linux and kernel engineering
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[linux-sunxi] Re: [PATCH v2 07/19] media: sun6i-csi: Add support for MIPI CSI-2 bridge input
Hi, On Wed 02 Dec 20, 16:40, Maxime Ripard wrote: > On Wed, Dec 02, 2020 at 03:19:11PM +0100, Paul Kocialkowski wrote: > > Hi, > > > > On Tue 01 Dec 20, 13:12, Maxime Ripard wrote: > > > Hi, > > > > > > On Sat, Nov 28, 2020 at 03:28:27PM +0100, Paul Kocialkowski wrote: > > > > The A31 CSI controller supports a MIPI CSI-2 bridge input, which has > > > > its own dedicated port in the fwnode graph. > > > > > > > > Support for this input is added with this change: > > > > - two pads are defined for the media entity instead of one > > > > and only one needs to be connected at a time; > > > > - the pads currently match the fwnode graph representation; > > > > - links are created between our pads and the subdevs for each > > > > interface and are no longer immutable so that userspace can select > > > > which interface to use in case both are bound to a subdev; > > > > - fwnode endpoints are parsed and stored for each interface; > > > > - the active subdev (and fwnode endpoint) is retrieved when validating > > > > the media link at stream on time and cleared at stream off; > > > > - an error is raised if both links are active at the same time; > > > > - the MIPI interface bit is set if the MIPI CSI-2 bridge endpoint is > > > > active. > > > > > > > > In the future, the media entity representation might evolve to: > > > > - distinguish the internal parallel bridge and data formatter; > > > > - represent each of the 4 internal channels that can exist between > > > > the parallel bridge (for BT656 time-multiplex) and MIPI CSI-2 > > > > (internal channels can be mapped to virtual channels); > > > > - connect the controller's output to the ISP instead of its > > > > DMA engine. > > > > > > > > Finally note that the MIPI CSI-2 bridges should not be linked in > > > > the fwnode graph unless they have a sensor subdev attached. > > > > > > I'll leave most of the review to Laurent and Sakari, but I'm not quite > > > sure what you meant in the last paragraph. Did you mean that the > > > MIPI-CSI controller in the Allwinner SoC should only be linked if it has > > > a sensor attached, or did you mean that any MIPI-CSI2 bridge cannot be > > > attached to the controller? > > > > So the use of plural was a mistake and your first understanding is the > > correct > > one: if the bridge is linked to the CSI controller in the OF graph but the > > bridge doesn't have a sensor attached, the CSI controller driver will fail > > to probe, as far as I could see. > > I'm not sure it's reasonable to not link it in the DTSI then, we'll want > to reduce as much the boilerplate from the board DTS as possible, and > the MIPI-CSI controller is always there anyway. However, we should > definitely have it disabled if there's no sensor, which should solve > your probe issue Ah yes there's a good chance that it will solve it. I'll try that and get back to you! Cheers, Paul -- Paul Kocialkowski, Bootlin Embedded Linux and kernel engineering https://bootlin.com -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/X8e7u3smOjzFluy5%40aptenodytes. signature.asc Description: PGP signature
[linux-sunxi] Re: [PATCH v2 09/19] ARM: dts: sunxi: h3/h5: Add CSI controller port for parallel input
Hi,
On Tue 01 Dec 20, 13:14, Maxime Ripard wrote:
> On Sat, Nov 28, 2020 at 03:28:29PM +0100, Paul Kocialkowski wrote:
> > Since the CSI controller binding is getting a bit more complex due
> > to the addition of MIPI CSI-2 bridge support, make the ports node
> > explicit with the parallel port.
> >
> > This way, it's clear that the controller only supports parallel
> > interface input and there's no confusion about the port number.
> >
> > Signed-off-by: Paul Kocialkowski
> > ---
> > arch/arm/boot/dts/sunxi-h3-h5.dtsi | 9 +
> > 1 file changed, 9 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
> > b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
> > index 9be13378d4df..02b698cace6a 100644
> > --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
> > +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
> > @@ -803,6 +803,15 @@ csi: camera@1cb {
> > pinctrl-names = "default";
> > pinctrl-0 = <_pins>;
> > status = "disabled";
> > +
> > + ports {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + csi_in_parallel: port@0 {
> > + reg = <0>;
> > + };
> > + };
> > };
>
> This will create a DTC warning, since port@0 is the only node, and is
> equivalent to port
I'm not seeing the warning when running dtbs_check.
More generally, why is it a problem that there's only one node defined?
One issue that I did see is that the port node doesn't have an endpoint
here, so I will remove the requirement to have an endpoint in the bindings
documentation to allow this kind of definition.
Cheers,
Paul
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[linux-sunxi] Re: [PATCH v2 13/19] media: sunxi: Add support for the A31 MIPI CSI-2 controller
Hi, On Tue 01 Dec 20, 13:20, Maxime Ripard wrote: > Hi, > > On Sat, Nov 28, 2020 at 03:28:33PM +0100, Paul Kocialkowski wrote: > > The A31 MIPI CSI-2 controller is a dedicated MIPI CSI-2 bridge > > found on Allwinner SoCs such as the A31 and V3/V3s. > > > > It is a standalone block, connected to the CSI controller on one side > > and to the MIPI D-PHY block on the other. It has a dedicated address > > space, interrupt line and clock. > > > > It is represented as a V4L2 subdev to the CSI controller and takes a > > MIPI CSI-2 sensor as its own subdev, all using the fwnode graph and > > media controller API. > > > > Only 8-bit and 10-bit Bayer formats are currently supported. > > While up to 4 internal channels to the CSI controller exist, only one > > is currently supported by this implementation. > > > > Signed-off-by: Paul Kocialkowski > > --- > > drivers/media/platform/sunxi/Kconfig | 1 + > > drivers/media/platform/sunxi/Makefile | 1 + > > .../platform/sunxi/sun6i-mipi-csi2/Kconfig| 12 + > > .../platform/sunxi/sun6i-mipi-csi2/Makefile | 4 + > > .../sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.c | 591 ++ > > .../sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.h | 117 > > 6 files changed, 726 insertions(+) > > create mode 100644 drivers/media/platform/sunxi/sun6i-mipi-csi2/Kconfig > > create mode 100644 drivers/media/platform/sunxi/sun6i-mipi-csi2/Makefile > > create mode 100644 > > drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.c > > create mode 100644 > > drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.h > > > > diff --git a/drivers/media/platform/sunxi/Kconfig > > b/drivers/media/platform/sunxi/Kconfig > > index 7151cc249afa..9684e07454ad 100644 > > --- a/drivers/media/platform/sunxi/Kconfig > > +++ b/drivers/media/platform/sunxi/Kconfig > > @@ -2,3 +2,4 @@ > > > > source "drivers/media/platform/sunxi/sun4i-csi/Kconfig" > > source "drivers/media/platform/sunxi/sun6i-csi/Kconfig" > > +source "drivers/media/platform/sunxi/sun6i-mipi-csi2/Kconfig" > > diff --git a/drivers/media/platform/sunxi/Makefile > > b/drivers/media/platform/sunxi/Makefile > > index fc537c9f5ca9..887a7cae8fca 100644 > > --- a/drivers/media/platform/sunxi/Makefile > > +++ b/drivers/media/platform/sunxi/Makefile > > @@ -2,5 +2,6 @@ > > > > obj-y += sun4i-csi/ > > obj-y += sun6i-csi/ > > +obj-y += sun6i-mipi-csi2/ > > I'm not sure we need a new folder here, it's only ever tied to sun6i-csi > so it would make more sense to have it in the same folder. My thinking was that it's a different driver and a different hardware block, so it's less confusing to have it in a different directory. I think many would expect the driver to share code with sun6i-csi (in a component driver kind of way) if it was in the same directory, which is not the case here. > > obj-y += sun8i-di/ > > obj-y += sun8i-rotate/ > > diff --git a/drivers/media/platform/sunxi/sun6i-mipi-csi2/Kconfig > > b/drivers/media/platform/sunxi/sun6i-mipi-csi2/Kconfig > > new file mode 100644 > > index ..3260591ed5c0 > > --- /dev/null > > +++ b/drivers/media/platform/sunxi/sun6i-mipi-csi2/Kconfig > > @@ -0,0 +1,12 @@ > > +# SPDX-License-Identifier: GPL-2.0-only > > +config VIDEO_SUN6I_MIPI_CSI2 > > + tristate "Allwinner A31 MIPI CSI-2 Controller Driver" > > + depends on VIDEO_V4L2 && COMMON_CLK > > + depends on ARCH_SUNXI || COMPILE_TEST > > + select PHY_SUN6I_MIPI_DPHY > > + select MEDIA_CONTROLLER > > + select VIDEO_V4L2_SUBDEV_API > > + select REGMAP_MMIO > > + select V4L2_FWNODE > > + help > > + Support for the Allwinner A31 MIPI CSI-2 Controller. > > diff --git a/drivers/media/platform/sunxi/sun6i-mipi-csi2/Makefile > > b/drivers/media/platform/sunxi/sun6i-mipi-csi2/Makefile > > new file mode 100644 > > index ..14e4e03818b5 > > --- /dev/null > > +++ b/drivers/media/platform/sunxi/sun6i-mipi-csi2/Makefile > > @@ -0,0 +1,4 @@ > > +# SPDX-License-Identifier: GPL-2.0-only > > +sun6i-mipi-csi2-y += sun6i_mipi_csi2.o > > + > > +obj-$(CONFIG_VIDEO_SUN6I_MIPI_CSI2) += sun6i-mipi-csi2.o > > diff --git a/drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.c > > b/drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.c > > new file mode 100644 > > index ..a6567ef82fb4 &
[linux-sunxi] Re: [PATCH v2 07/19] media: sun6i-csi: Add support for MIPI CSI-2 bridge input
Hi, On Tue 01 Dec 20, 13:12, Maxime Ripard wrote: > Hi, > > On Sat, Nov 28, 2020 at 03:28:27PM +0100, Paul Kocialkowski wrote: > > The A31 CSI controller supports a MIPI CSI-2 bridge input, which has > > its own dedicated port in the fwnode graph. > > > > Support for this input is added with this change: > > - two pads are defined for the media entity instead of one > > and only one needs to be connected at a time; > > - the pads currently match the fwnode graph representation; > > - links are created between our pads and the subdevs for each > > interface and are no longer immutable so that userspace can select > > which interface to use in case both are bound to a subdev; > > - fwnode endpoints are parsed and stored for each interface; > > - the active subdev (and fwnode endpoint) is retrieved when validating > > the media link at stream on time and cleared at stream off; > > - an error is raised if both links are active at the same time; > > - the MIPI interface bit is set if the MIPI CSI-2 bridge endpoint is > > active. > > > > In the future, the media entity representation might evolve to: > > - distinguish the internal parallel bridge and data formatter; > > - represent each of the 4 internal channels that can exist between > > the parallel bridge (for BT656 time-multiplex) and MIPI CSI-2 > > (internal channels can be mapped to virtual channels); > > - connect the controller's output to the ISP instead of its > > DMA engine. > > > > Finally note that the MIPI CSI-2 bridges should not be linked in > > the fwnode graph unless they have a sensor subdev attached. > > I'll leave most of the review to Laurent and Sakari, but I'm not quite > sure what you meant in the last paragraph. Did you mean that the > MIPI-CSI controller in the Allwinner SoC should only be linked if it has > a sensor attached, or did you mean that any MIPI-CSI2 bridge cannot be > attached to the controller? So the use of plural was a mistake and your first understanding is the correct one: if the bridge is linked to the CSI controller in the OF graph but the bridge doesn't have a sensor attached, the CSI controller driver will fail to probe, as far as I could see. I haven't investigated much but it looks like this is expected behavior. > Also, having somewhere (like your cover letter) the media-ctl setup you > tested with would be great. Understood! Cheers, Paul -- Paul Kocialkowski, Bootlin Embedded Linux and kernel engineering https://bootlin.com -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/X8eiXxYw1iHKbdDV%40aptenodytes. signature.asc Description: PGP signature
[linux-sunxi] Re: [PATCH v2 06/19] dt-bindings: media: sun6i-a31-csi: Add MIPI CSI-2 input port
Hi, On Tue 01 Dec 20, 11:43, Maxime Ripard wrote: > On Sat, Nov 28, 2020 at 03:28:26PM +0100, Paul Kocialkowski wrote: > > The A31 CSI controller supports two distinct input interfaces: > > parallel and an external MIPI CSI-2 bridge. The parallel interface > > is often connected to a set of hardware pins while the MIPI CSI-2 > > bridge is an internal FIFO-ish link. As a result, these two inputs > > are distinguished as two different ports. > > > > Note that only one of the two may be present on a controller instance. > > For example, the V3s has one controller dedicated to MIPI-CSI2 and one > > dedicated to parallel. > > > > Update the binding with an explicit ports node that holds two distinct > > port nodes: one for parallel input and one for MIPI CSI-2. > > > > This is backward-compatible with the single-port approach that was > > previously taken for representing the parallel interface port, which > > stays enumerated as fwnode port 0. However, it is now marked as > > deprecated and the multi-port approach should be preferred. > > > > Note that additional ports may be added in the future, especially to > > support feeding the CSI controller's output to the ISP. > > > > Signed-off-by: Paul Kocialkowski > > --- > > .../media/allwinner,sun6i-a31-csi.yaml| 86 --- > > 1 file changed, 73 insertions(+), 13 deletions(-) > > > > diff --git > > a/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-csi.yaml > > b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-csi.yaml > > index 1fd9b5532a21..3bcee2d44f3c 100644 > > --- a/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-csi.yaml > > +++ b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-csi.yaml > > @@ -43,6 +43,7 @@ properties: > ># See ./video-interfaces.txt for details > >port: > > type: object > > +deprecated: true > > I'm not sure we want to deprecate it. There's some SoCs with the same > controller but without the MIPI-CSI block where this would be completely > valid I think we'll need to deprecate it when adding support for the ISP anyway, so I figured we might as well do it now. But I'm okay to postpone this for now. > > properties: > >endpoint: > > @@ -67,6 +68,59 @@ properties: > > > > additionalProperties: false > > > > + ports: > > +type: object > > + > > +properties: > > + port@0: > > +type: object > > +description: Parallel input port, connect to a parallel sensor > > + > > +properties: > > + reg: > > +const: 0 > > + > > + endpoint: > > +type: object > > + > > +properties: > > + remote-endpoint: true > > + > > + bus-width: > > +enum: [ 8, 10, 12, 16 ] > > + > > + pclk-sample: true > > + hsync-active: true > > + vsync-active: true > > + > > +required: > > + - bus-width > > + - remote-endpoint > > + > > +required: > > + - endpoint > > + > > +additionalProperties: false > > + > > + port@1: > > +type: object > > +description: MIPI CSI-2 bridge input port > > + > > +properties: > > + reg: > > +const: 1 > > + > > + endpoint: > > +type: object > > + > > +properties: > > + remote-endpoint: true > > + > > +required: > > + - remote-endpoint > > + > > +additionalProperties: false > > There's a schema for the OF-graph now, you'll want to use it. I didn't know that, thanks for the tip! Will look into it. Cheers, Paul -- Paul Kocialkowski, Bootlin Embedded Linux and kernel engineering https://bootlin.com -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/X8ehzCjZJ3yC8YtJ%40aptenodytes. signature.asc Description: PGP signature
[linux-sunxi] [PATCH v2 19/19] MAINTAINERS: Add entry for the Allwinner A83T MIPI CSI-2 bridge
Add myself as maintainer of the A83T MIPI CSI-2 bridge media driver. Signed-off-by: Paul Kocialkowski --- MAINTAINERS | 8 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index a1352171778b..3b48612657b6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -717,6 +717,14 @@ T: git git://linuxtv.org/media_tree.git F: Documentation/devicetree/bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml F: drivers/media/platform/sunxi/sun6i-mipi-csi2/ +ALLWINNER A83T MIPI CSI-2 BRIDGE +M: Paul Kocialkowski +L: linux-me...@vger.kernel.org +S: Maintained +T: git git://linuxtv.org/media_tree.git +F: Documentation/devicetree/bindings/media/allwinner,sun8i-a83t-mipi-csi2.yaml +F: drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/ + ALLWINNER CPUFREQ DRIVER M: Yangtao Li L: linux...@vger.kernel.org -- 2.29.2 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/20201128142839.517949-20-paul.kocialkowski%40bootlin.com.
[linux-sunxi] [PATCH v2 18/19] ARM: dts: sun8i: a83t: Add MIPI CSI-2 controller node
MIPI CSI-2 is supported on the A83T with a dedicated controller that
covers both the protocol and D-PHY. It can be connected to the CSI
interface as a V4L2 subdev through the fwnode graph.
This is not done by default since connecting the bridge without a
subdev attached to it will cause a failure on the CSI driver.
Signed-off-by: Paul Kocialkowski
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 26 ++
1 file changed, 26 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 3ce030f7e05d..ee19cbb565a6 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -1076,6 +1076,32 @@ csi_in_mipi_csi2_bridge: port@1 {
};
};
+ mipi_csi2: csi@1cb1000 {
+ compatible = "allwinner,sun8i-a83t-mipi-csi2";
+ reg = <0x01cb1000 0x1000>;
+ interrupts = ;
+ clocks = < CLK_BUS_CSI>,
+< CLK_CSI_SCLK>,
+< CLK_MIPI_CSI>,
+< CLK_CSI_MISC>;
+ clock-names = "bus", "mod", "mipi", "misc";
+ resets = < RST_BUS_CSI>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mipi_csi2_in: port@0 {
+ reg = <0>;
+ };
+
+ mipi_csi2_out: port@1 {
+ reg = <1>;
+ };
+ };
+ };
+
hdmi: hdmi@1ee {
compatible = "allwinner,sun8i-a83t-dw-hdmi";
reg = <0x01ee 0x1>;
--
2.29.2
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[linux-sunxi] [PATCH v2 17/19] media: sunxi: Add support for the A83T MIPI CSI-2 controller
The A83T supports MIPI CSI-2 with a composite controller, covering both the protocol logic and the D-PHY implementation. This controller seems to be found on the A83T only and probably was abandoned since. This implementation splits the protocol and D-PHY registers and uses the PHY framework internally. The D-PHY is not registered as a standalone PHY driver since it cannot be used with any other controller. There are a few notable points about the controller: - The initialisation sequence involes writing specific magic init values that do not seem to make any particular sense given the concerned register fields. - Interrupts appear to be hitting regardless of the interrupt mask registers, which can cause a serious flood when transmission errors occur. Only 8-bit and 10-bit Bayer formats are currently supported. While up to 4 internal channels to the CSI controller exist, only one is currently supported by this implementation. This work is based on the first version of the driver submitted by Kévin L'hôpital, which was adapted to mainline from the Allwinner BSP. This version integrates MIPI CSI-2 support as a standalone V4L2 subdev instead of merging it in the sun6i-csi driver. It was tested on a Banana Pi M3 board with an OV8865 sensor in a 4-lane configuration. Signed-off-by: Paul Kocialkowski --- drivers/media/platform/sunxi/Kconfig | 1 + drivers/media/platform/sunxi/Makefile | 1 + .../sunxi/sun8i-a83t-mipi-csi2/Kconfig| 11 + .../sunxi/sun8i-a83t-mipi-csi2/Makefile | 4 + .../sun8i-a83t-mipi-csi2/sun8i_a83t_dphy.c| 92 +++ .../sun8i-a83t-mipi-csi2/sun8i_a83t_dphy.h| 39 ++ .../sun8i_a83t_mipi_csi2.c| 657 ++ .../sun8i_a83t_mipi_csi2.h| 197 ++ 8 files changed, 1002 insertions(+) create mode 100644 drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/Kconfig create mode 100644 drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/Makefile create mode 100644 drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_dphy.c create mode 100644 drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_dphy.h create mode 100644 drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_mipi_csi2.c create mode 100644 drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_mipi_csi2.h diff --git a/drivers/media/platform/sunxi/Kconfig b/drivers/media/platform/sunxi/Kconfig index 9684e07454ad..db4c07be7e4c 100644 --- a/drivers/media/platform/sunxi/Kconfig +++ b/drivers/media/platform/sunxi/Kconfig @@ -3,3 +3,4 @@ source "drivers/media/platform/sunxi/sun4i-csi/Kconfig" source "drivers/media/platform/sunxi/sun6i-csi/Kconfig" source "drivers/media/platform/sunxi/sun6i-mipi-csi2/Kconfig" +source "drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/Kconfig" diff --git a/drivers/media/platform/sunxi/Makefile b/drivers/media/platform/sunxi/Makefile index 887a7cae8fca..9aa01cb01883 100644 --- a/drivers/media/platform/sunxi/Makefile +++ b/drivers/media/platform/sunxi/Makefile @@ -3,5 +3,6 @@ obj-y += sun4i-csi/ obj-y += sun6i-csi/ obj-y += sun6i-mipi-csi2/ +obj-y += sun8i-a83t-mipi-csi2/ obj-y += sun8i-di/ obj-y += sun8i-rotate/ diff --git a/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/Kconfig b/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/Kconfig new file mode 100644 index ..162f5d1dc25f --- /dev/null +++ b/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/Kconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-only +config VIDEO_SUN8I_A83T_MIPI_CSI2 + tristate "Allwinner A83T MIPI CSI-2 Controller and D-PHY Driver" + depends on VIDEO_V4L2 && COMMON_CLK + depends on ARCH_SUNXI || COMPILE_TEST + select MEDIA_CONTROLLER + select VIDEO_V4L2_SUBDEV_API + select REGMAP_MMIO + select V4L2_FWNODE + help + Support for the Allwinner A83T MIPI CSI-2 Controller and D-PHY. diff --git a/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/Makefile b/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/Makefile new file mode 100644 index ..1427d15a879a --- /dev/null +++ b/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only +sun8i-a83t-mipi-csi2-y += sun8i_a83t_mipi_csi2.o sun8i_a83t_dphy.o + +obj-$(CONFIG_VIDEO_SUN8I_A83T_MIPI_CSI2) += sun8i-a83t-mipi-csi2.o diff --git a/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_dphy.c b/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_dphy.c new file mode 100644 index ..ebb504247956 --- /dev/null +++ b/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_dphy.c @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 Bootlin + * Author: Paul Kocialkowski + */ + +#include +#include + +#include "sun8
[linux-sunxi] [PATCH v2 16/19] dt-bindings: media: Add A83T MIPI CSI-2 bindings documentation
This introduces YAML bindings documentation for the A83T MIPI CSI-2
controller.
Signed-off-by: Paul Kocialkowski
---
.../media/allwinner,sun8i-a83t-mipi-csi2.yaml | 147 ++
1 file changed, 147 insertions(+)
create mode 100644
Documentation/devicetree/bindings/media/allwinner,sun8i-a83t-mipi-csi2.yaml
diff --git
a/Documentation/devicetree/bindings/media/allwinner,sun8i-a83t-mipi-csi2.yaml
b/Documentation/devicetree/bindings/media/allwinner,sun8i-a83t-mipi-csi2.yaml
new file mode 100644
index ..78309084f904
--- /dev/null
+++
b/Documentation/devicetree/bindings/media/allwinner,sun8i-a83t-mipi-csi2.yaml
@@ -0,0 +1,147 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/allwinner,sun8i-a83t-mipi-csi2.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Allwinner A83T MIPI CSI-2 Device Tree Bindings
+
+maintainers:
+ - Paul Kocialkowski
+
+properties:
+ compatible:
+const: allwinner,sun8i-a83t-mipi-csi2
+
+ reg:
+maxItems: 1
+
+ interrupts:
+maxItems: 1
+
+ clocks:
+items:
+ - description: Bus Clock
+ - description: Module Clock
+ - description: MIPI-specific Clock
+ - description: Misc CSI Clock
+
+ clock-names:
+items:
+ - const: bus
+ - const: mod
+ - const: mipi
+ - const: misc
+
+ resets:
+maxItems: 1
+
+ # See ./video-interfaces.txt for details
+ ports:
+type: object
+
+properties:
+ port@0:
+type: object
+description: Input port, connect to a MIPI CSI-2 sensor
+
+properties:
+ reg:
+const: 0
+
+ endpoint:
+type: object
+
+properties:
+ remote-endpoint: true
+
+ clock-lanes:
+maxItems: 1
+
+ data-lanes:
+minItems: 1
+maxItems: 4
+
+required:
+ - data-lanes
+ - remote-endpoint
+
+required:
+ - endpoint
+
+additionalProperties: false
+
+ port@1:
+type: object
+description: Output port, connect to a CSI controller
+
+properties:
+ reg:
+const: 1
+
+ endpoint:
+type: object
+
+properties:
+ remote-endpoint: true
+
+ bus-type:
+const: 4
+
+required:
+ - endpoint
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - resets
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+#include
+#include
+
+mipi_csi2: csi@1cb1000 {
+compatible = "allwinner,sun8i-a83t-mipi-csi2";
+reg = <0x01cb1000 0x1000>;
+interrupts = ;
+clocks = < CLK_BUS_CSI>,
+ < CLK_CSI_SCLK>,
+ < CLK_MIPI_CSI>,
+ < CLK_CSI_MISC>;
+clock-names = "bus", "mod", "mipi", "misc";
+resets = < RST_BUS_CSI>;
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+mipi_csi2_in: port@0 {
+reg = <0>;
+
+mipi_csi2_in_ov8865: endpoint {
+data-lanes = <1 2 3 4>;
+
+remote-endpoint = <_out_mipi_csi2>;
+};
+};
+
+mipi_csi2_out: port@1 {
+reg = <1>;
+
+mipi_csi2_out_csi: endpoint {
+remote-endpoint = <_in_mipi_csi2>;
+};
+};
+};
+};
+
+...
--
2.29.2
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[linux-sunxi] [PATCH v2 15/19] MAINTAINERS: Add entry for the Allwinner A31 MIPI CSI-2 bridge
Add myself as maintainer of the A31 MIPI CSI-2 bridge media driver. Signed-off-by: Paul Kocialkowski --- MAINTAINERS | 8 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 0644128640fb..a1352171778b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -709,6 +709,14 @@ T: git git://linuxtv.org/media_tree.git F: Documentation/devicetree/bindings/media/allwinner,sun4i-a10-csi.yaml F: drivers/media/platform/sunxi/sun4i-csi/ +ALLWINNER A31 MIPI CSI-2 BRIDGE +M: Paul Kocialkowski +L: linux-me...@vger.kernel.org +S: Maintained +T: git git://linuxtv.org/media_tree.git +F: Documentation/devicetree/bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml +F: drivers/media/platform/sunxi/sun6i-mipi-csi2/ + ALLWINNER CPUFREQ DRIVER M: Yangtao Li L: linux...@vger.kernel.org -- 2.29.2 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/20201128142839.517949-16-paul.kocialkowski%40bootlin.com.
[linux-sunxi] [PATCH v2 14/19] ARM: dts: sun8i: v3s: Add nodes for MIPI CSI-2 support
MIPI CSI-2 is supported on the V3s with an A31-based MIPI CSI-2 bridge
controller. The controller uses a separate D-PHY, which is the same
that is otherwise used for MIPI DSI, but used in Rx mode.
On the V3s, the CSI0 controller is dedicated to MIPI CSI-2 as it does
not have access to any parallel interface pins.
Add all the necessary nodes (CSI0, MIPI CSI-2 bridge and D-PHY) to
support the MIPI CSI-2 interface.
Note that a fwnode graph link is created between CSI0 and MIPI CSI-2
even when no sensor is connected. This will result in a probe failure
for the controller as long as no sensor is connected but this is fine
since no other interface is available.
Signed-off-by: Paul Kocialkowski
---
arch/arm/boot/dts/sun8i-v3s.dtsi | 68
1 file changed, 68 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi
index 7926c8b2ac5e..641da6c7bca0 100644
--- a/arch/arm/boot/dts/sun8i-v3s.dtsi
+++ b/arch/arm/boot/dts/sun8i-v3s.dtsi
@@ -530,6 +530,31 @@ spi0: spi@1c68000 {
#size-cells = <0>;
};
+ csi0: camera@1cb {
+ compatible = "allwinner,sun8i-v3s-csi";
+ reg = <0x01cb 0x1000>;
+ interrupts = ;
+ clocks = < CLK_BUS_CSI>,
+< CLK_CSI1_SCLK>,
+< CLK_DRAM_CSI>;
+ clock-names = "bus", "mod", "ram";
+ resets = < RST_BUS_CSI>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <1>;
+
+ csi0_in_mipi_csi2: endpoint {
+ remote-endpoint =
<_csi2_out_csi0>;
+ };
+ };
+ };
+ };
+
csi1: camera@1cb4000 {
compatible = "allwinner,sun8i-v3s-csi";
reg = <0x01cb4000 0x3000>;
@@ -561,5 +586,48 @@ gic: interrupt-controller@1c81000 {
#interrupt-cells = <3>;
interrupts = ;
};
+
+ mipi_csi2: csi@1cb1000 {
+ compatible = "allwinner,sun8i-v3s-mipi-csi2",
+"allwinner,sun6i-a31-mipi-csi2";
+ reg = <0x01cb1000 0x1000>;
+ interrupts = ;
+ clocks = < CLK_BUS_CSI>,
+< CLK_CSI1_SCLK>;
+ clock-names = "bus", "mod";
+ resets = < RST_BUS_CSI>;
+ status = "disabled";
+
+ phys = <>;
+ phy-names = "dphy";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mipi_csi2_in: port@0 {
+ reg = <0>;
+ };
+
+ mipi_csi2_out: port@1 {
+ reg = <1>;
+
+ mipi_csi2_out_csi0: endpoint {
+ remote-endpoint =
<_in_mipi_csi2>;
+ };
+ };
+ };
+ };
+
+ dphy: d-phy@1cb2000 {
+ compatible = "allwinner,sun6i-a31-mipi-dphy";
+ reg = <0x01cb2000 0x1000>;
+ clocks = < CLK_BUS_CSI>,
+< CLK_MIPI_CSI>;
+ clock-names = "bus", "mod";
+ resets = < RST_BUS_CSI>;
+ status = "disabled";
+ #phy-cells = <0>;
+ };
};
};
--
2.29.2
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[linux-sunxi] [PATCH v2 13/19] media: sunxi: Add support for the A31 MIPI CSI-2 controller
The A31 MIPI CSI-2 controller is a dedicated MIPI CSI-2 bridge
found on Allwinner SoCs such as the A31 and V3/V3s.
It is a standalone block, connected to the CSI controller on one side
and to the MIPI D-PHY block on the other. It has a dedicated address
space, interrupt line and clock.
It is represented as a V4L2 subdev to the CSI controller and takes a
MIPI CSI-2 sensor as its own subdev, all using the fwnode graph and
media controller API.
Only 8-bit and 10-bit Bayer formats are currently supported.
While up to 4 internal channels to the CSI controller exist, only one
is currently supported by this implementation.
Signed-off-by: Paul Kocialkowski
---
drivers/media/platform/sunxi/Kconfig | 1 +
drivers/media/platform/sunxi/Makefile | 1 +
.../platform/sunxi/sun6i-mipi-csi2/Kconfig| 12 +
.../platform/sunxi/sun6i-mipi-csi2/Makefile | 4 +
.../sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.c | 591 ++
.../sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.h | 117
6 files changed, 726 insertions(+)
create mode 100644 drivers/media/platform/sunxi/sun6i-mipi-csi2/Kconfig
create mode 100644 drivers/media/platform/sunxi/sun6i-mipi-csi2/Makefile
create mode 100644
drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.c
create mode 100644
drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.h
diff --git a/drivers/media/platform/sunxi/Kconfig
b/drivers/media/platform/sunxi/Kconfig
index 7151cc249afa..9684e07454ad 100644
--- a/drivers/media/platform/sunxi/Kconfig
+++ b/drivers/media/platform/sunxi/Kconfig
@@ -2,3 +2,4 @@
source "drivers/media/platform/sunxi/sun4i-csi/Kconfig"
source "drivers/media/platform/sunxi/sun6i-csi/Kconfig"
+source "drivers/media/platform/sunxi/sun6i-mipi-csi2/Kconfig"
diff --git a/drivers/media/platform/sunxi/Makefile
b/drivers/media/platform/sunxi/Makefile
index fc537c9f5ca9..887a7cae8fca 100644
--- a/drivers/media/platform/sunxi/Makefile
+++ b/drivers/media/platform/sunxi/Makefile
@@ -2,5 +2,6 @@
obj-y += sun4i-csi/
obj-y += sun6i-csi/
+obj-y += sun6i-mipi-csi2/
obj-y += sun8i-di/
obj-y += sun8i-rotate/
diff --git a/drivers/media/platform/sunxi/sun6i-mipi-csi2/Kconfig
b/drivers/media/platform/sunxi/sun6i-mipi-csi2/Kconfig
new file mode 100644
index ..3260591ed5c0
--- /dev/null
+++ b/drivers/media/platform/sunxi/sun6i-mipi-csi2/Kconfig
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-only
+config VIDEO_SUN6I_MIPI_CSI2
+ tristate "Allwinner A31 MIPI CSI-2 Controller Driver"
+ depends on VIDEO_V4L2 && COMMON_CLK
+ depends on ARCH_SUNXI || COMPILE_TEST
+ select PHY_SUN6I_MIPI_DPHY
+ select MEDIA_CONTROLLER
+ select VIDEO_V4L2_SUBDEV_API
+ select REGMAP_MMIO
+ select V4L2_FWNODE
+ help
+ Support for the Allwinner A31 MIPI CSI-2 Controller.
diff --git a/drivers/media/platform/sunxi/sun6i-mipi-csi2/Makefile
b/drivers/media/platform/sunxi/sun6i-mipi-csi2/Makefile
new file mode 100644
index ..14e4e03818b5
--- /dev/null
+++ b/drivers/media/platform/sunxi/sun6i-mipi-csi2/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+sun6i-mipi-csi2-y += sun6i_mipi_csi2.o
+
+obj-$(CONFIG_VIDEO_SUN6I_MIPI_CSI2) += sun6i-mipi-csi2.o
diff --git a/drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.c
b/drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.c
new file mode 100644
index ..a6567ef82fb4
--- /dev/null
+++ b/drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.c
@@ -0,0 +1,591 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020 Bootlin
+ * Author: Paul Kocialkowski
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "sun6i_mipi_csi2.h"
+
+#define MODULE_NAME"sun6i-mipi-csi2"
+
+static const u32 sun6i_mipi_csi2_mbus_codes[] = {
+ MEDIA_BUS_FMT_SBGGR8_1X8,
+ MEDIA_BUS_FMT_SGBRG8_1X8,
+ MEDIA_BUS_FMT_SGRBG8_1X8,
+ MEDIA_BUS_FMT_SRGGB8_1X8,
+ MEDIA_BUS_FMT_SBGGR10_1X10,
+ MEDIA_BUS_FMT_SGBRG10_1X10,
+ MEDIA_BUS_FMT_SGRBG10_1X10,
+ MEDIA_BUS_FMT_SRGGB10_1X10,
+};
+
+/* Video */
+
+static int sun6i_mipi_csi2_s_stream(struct v4l2_subdev *subdev, int on)
+{
+ struct sun6i_mipi_csi2_video *video =
+ sun6i_mipi_csi2_subdev_video(subdev);
+ struct sun6i_mipi_csi2_dev *cdev = sun6i_mipi_csi2_video_dev(video);
+ struct v4l2_subdev *remote_subdev = video->remote_subdev;
+ struct v4l2_fwnode_bus_mipi_csi2 *bus_mipi_csi2 =
+ >endpoint.bus.mipi_csi2;
+ union phy_configure_opts dphy_opts = { 0 };
+ struct phy_configure_opts_mipi_dphy *dphy_cfg = _opts.mipi_dphy;
+ struct regmap *regmap = cdev->regmap;
+ struct v4l2_ctrl *ctrl;
+ unsigne
[linux-sunxi] [PATCH v2 12/19] dt-bindings: media: Add A31 MIPI CSI-2 bindings documentation
This introduces YAML bindings documentation for the A31 MIPI CSI-2
controller.
Signed-off-by: Paul Kocialkowski
---
.../media/allwinner,sun6i-a31-mipi-csi2.yaml | 151 ++
1 file changed, 151 insertions(+)
create mode 100644
Documentation/devicetree/bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml
diff --git
a/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml
b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml
new file mode 100644
index ..917cd09d6fda
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml
@@ -0,0 +1,151 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/allwinner,sun6i-a31-mipi-csi2.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Allwinner A31 MIPI CSI-2 Device Tree Bindings
+
+maintainers:
+ - Paul Kocialkowski
+
+properties:
+ compatible:
+oneOf:
+ - const: allwinner,sun6i-a31-mipi-csi2
+ - items:
+ - const: allwinner,sun8i-v3s-mipi-csi2
+ - const: allwinner,sun6i-a31-mipi-csi2
+
+ reg:
+maxItems: 1
+
+ interrupts:
+maxItems: 1
+
+ clocks:
+items:
+ - description: Bus Clock
+ - description: Module Clock
+
+ clock-names:
+items:
+ - const: bus
+ - const: mod
+
+ phys:
+items:
+ - description: MIPI D-PHY
+
+ phy-names:
+items:
+ - const: dphy
+
+ resets:
+maxItems: 1
+
+ # See ./video-interfaces.txt for details
+ ports:
+type: object
+
+properties:
+ port@0:
+type: object
+description: Input port, connect to a MIPI CSI-2 sensor
+
+properties:
+ reg:
+const: 0
+
+ endpoint:
+type: object
+
+properties:
+ remote-endpoint: true
+
+ data-lanes:
+minItems: 1
+maxItems: 4
+
+required:
+ - data-lanes
+ - remote-endpoint
+
+required:
+ - endpoint
+
+additionalProperties: false
+
+ port@1:
+type: object
+description: Output port, connect to a CSI controller
+
+properties:
+ reg:
+const: 1
+
+ endpoint:
+type: object
+
+properties:
+ remote-endpoint: true
+
+required:
+ - endpoint
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - resets
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+#include
+#include
+
+mipi_csi2: csi@1cb1000 {
+compatible = "allwinner,sun8i-v3s-mipi-csi2",
+ "allwinner,sun6i-a31-mipi-csi2";
+reg = <0x01cb1000 0x1000>;
+interrupts = ;
+clocks = < CLK_BUS_CSI>,
+ < CLK_CSI1_SCLK>;
+clock-names = "bus", "mod";
+resets = < RST_BUS_CSI>;
+
+phys = <>;
+phy-names = "dphy";
+
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+mipi_csi2_in: port@0 {
+reg = <0>;
+
+mipi_csi2_in_ov5648: endpoint {
+data-lanes = <1 2 3 4>;
+
+remote-endpoint = <_out_mipi_csi2>;
+};
+};
+
+mipi_csi2_out: port@1 {
+reg = <1>;
+
+mipi_csi2_out_csi0: endpoint {
+remote-endpoint = <_in_mipi_csi2>;
+};
+};
+};
+};
+
+...
--
2.29.2
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[linux-sunxi] [PATCH v2 11/19] arm64: dts: allwinner: a64: Add CSI controller port for parallel input
Since the CSI controller binding is getting a bit more complex due
to the addition of MIPI CSI-2 bridge support, make the ports node
explicit with the parallel port.
This way, it's clear that the controller only supports parallel
interface input and there's no confusion about the port number.
Signed-off-by: Paul Kocialkowski
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 51cc30e84e26..1e1f0d2097d5 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -1109,6 +1109,15 @@ csi: csi@1cb {
pinctrl-names = "default";
pinctrl-0 = <_pins>;
status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csi_in_parallel: port@0 {
+ reg = <0>;
+ };
+ };
};
dsi: dsi@1ca {
--
2.29.2
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[linux-sunxi] [PATCH v2 10/19] ARM: dts: sun8i: v3s: Add CSI1 controller port for parallel input
Since the CSI controller binding is getting a bit more complex due
to the addition of MIPI CSI-2 bridge support, make the ports node
explicit with the parallel port.
This way, it's clear that the controller only supports parallel
interface input and there's no confusion about the port number.
Signed-off-by: Paul Kocialkowski
---
arch/arm/boot/dts/sun8i-v3s.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi
index 7b2d684aeb97..7926c8b2ac5e 100644
--- a/arch/arm/boot/dts/sun8i-v3s.dtsi
+++ b/arch/arm/boot/dts/sun8i-v3s.dtsi
@@ -540,6 +540,15 @@ csi1: camera@1cb4000 {
clock-names = "bus", "mod", "ram";
resets = < RST_BUS_CSI>;
status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csi1_in_parallel: port@0 {
+ reg = <0>;
+ };
+ };
};
gic: interrupt-controller@1c81000 {
--
2.29.2
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[linux-sunxi] [PATCH v2 09/19] ARM: dts: sunxi: h3/h5: Add CSI controller port for parallel input
Since the CSI controller binding is getting a bit more complex due
to the addition of MIPI CSI-2 bridge support, make the ports node
explicit with the parallel port.
This way, it's clear that the controller only supports parallel
interface input and there's no confusion about the port number.
Signed-off-by: Paul Kocialkowski
---
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index 9be13378d4df..02b698cace6a 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -803,6 +803,15 @@ csi: camera@1cb {
pinctrl-names = "default";
pinctrl-0 = <_pins>;
status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csi_in_parallel: port@0 {
+ reg = <0>;
+ };
+ };
};
hdmi: hdmi@1ee {
--
2.29.2
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[linux-sunxi] [PATCH v2 08/19] ARM: dts: sun8i: a83t: Add CSI controller ports
Since the CSI controller binding is getting a bit more complex due
to the addition of MIPI CSI-2 bridge support, make the ports node
explicit with the parallel and MIPI CSI-2 bridge ports.
This way, it's clear that the controller supports both parallel and
MIPI CSI-2 interface inputs and there's no confusion about their port
number.
Signed-off-by: Paul Kocialkowski
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index c010b27fdb6a..3ce030f7e05d 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -1062,7 +1062,17 @@ csi: camera@1cb {
resets = < RST_BUS_CSI>;
status = "disabled";
- csi_in: port {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csi_in_parallel: port@0 {
+ reg = <0>;
+ };
+
+ csi_in_mipi_csi2_bridge: port@1 {
+ reg = <1>;
+ };
};
};
--
2.29.2
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[linux-sunxi] [PATCH v2 07/19] media: sun6i-csi: Add support for MIPI CSI-2 bridge input
The A31 CSI controller supports a MIPI CSI-2 bridge input, which has
its own dedicated port in the fwnode graph.
Support for this input is added with this change:
- two pads are defined for the media entity instead of one
and only one needs to be connected at a time;
- the pads currently match the fwnode graph representation;
- links are created between our pads and the subdevs for each
interface and are no longer immutable so that userspace can select
which interface to use in case both are bound to a subdev;
- fwnode endpoints are parsed and stored for each interface;
- the active subdev (and fwnode endpoint) is retrieved when validating
the media link at stream on time and cleared at stream off;
- an error is raised if both links are active at the same time;
- the MIPI interface bit is set if the MIPI CSI-2 bridge endpoint is
active.
In the future, the media entity representation might evolve to:
- distinguish the internal parallel bridge and data formatter;
- represent each of the 4 internal channels that can exist between
the parallel bridge (for BT656 time-multiplex) and MIPI CSI-2
(internal channels can be mapped to virtual channels);
- connect the controller's output to the ISP instead of its
DMA engine.
Finally note that the MIPI CSI-2 bridges should not be linked in
the fwnode graph unless they have a sensor subdev attached.
Signed-off-by: Paul Kocialkowski
---
.../platform/sunxi/sun6i-csi/sun6i_csi.c | 123 ++
.../platform/sunxi/sun6i-csi/sun6i_csi.h | 3 -
.../platform/sunxi/sun6i-csi/sun6i_video.c| 53
.../platform/sunxi/sun6i-csi/sun6i_video.h| 7 +-
4 files changed, 135 insertions(+), 51 deletions(-)
diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
index f1150de94e98..481181038e1e 100644
--- a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
+++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
@@ -52,15 +52,16 @@ bool sun6i_csi_is_format_supported(struct sun6i_csi *csi,
u32 pixformat, u32 mbus_code)
{
struct sun6i_csi_dev *sdev = sun6i_csi_to_dev(csi);
+ struct v4l2_fwnode_endpoint *endpoint = sdev->csi.video.source_endpoint;
/*
* Some video receivers have the ability to be compatible with
* 8bit and 16bit bus width.
* Identify the media bus format from device tree.
*/
- if ((sdev->csi.v4l2_ep.bus_type == V4L2_MBUS_PARALLEL
-|| sdev->csi.v4l2_ep.bus_type == V4L2_MBUS_BT656)
-&& sdev->csi.v4l2_ep.bus.parallel.bus_width == 16) {
+ if ((endpoint->bus_type == V4L2_MBUS_PARALLEL
+|| endpoint->bus_type == V4L2_MBUS_BT656)
+&& endpoint->bus.parallel.bus_width == 16) {
switch (pixformat) {
case V4L2_PIX_FMT_HM12:
case V4L2_PIX_FMT_NV12:
@@ -373,7 +374,7 @@ static enum csi_input_seq get_csi_input_seq(struct
sun6i_csi_dev *sdev,
static void sun6i_csi_setup_bus(struct sun6i_csi_dev *sdev)
{
- struct v4l2_fwnode_endpoint *endpoint = >csi.v4l2_ep;
+ struct v4l2_fwnode_endpoint *endpoint = sdev->csi.video.source_endpoint;
struct sun6i_csi *csi = >csi;
unsigned char bus_width;
u32 flags;
@@ -459,6 +460,9 @@ static void sun6i_csi_setup_bus(struct sun6i_csi_dev *sdev)
if (flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
cfg |= CSI_IF_CFG_CLK_POL_FALLING_EDGE;
break;
+ case V4L2_MBUS_CSI2_DPHY:
+ cfg |= CSI_IF_CFG_MIPI_IF_MIPI;
+ break;
default:
dev_warn(sdev->dev, "Unsupported bus type: %d\n",
endpoint->bus_type);
@@ -636,11 +640,11 @@ void sun6i_csi_set_stream(struct sun6i_csi *csi, bool
enable)
* Media Controller and V4L2
*/
static int sun6i_csi_link_entity(struct sun6i_csi *csi,
+struct media_pad *sink_pad,
struct media_entity *entity,
-struct fwnode_handle *fwnode)
+struct fwnode_handle *fwnode, bool enabled)
{
struct media_entity *sink;
- struct media_pad *sink_pad;
int src_pad_index;
int ret;
@@ -654,14 +658,12 @@ static int sun6i_csi_link_entity(struct sun6i_csi *csi,
src_pad_index = ret;
sink = >video.vdev.entity;
- sink_pad = >video.pad;
dev_dbg(csi->dev, "creating %s:%u -> %s:%u link\n",
entity->name, src_pad_index, sink->name, sink_pad->index);
ret = media_create_pad_link(entity, src_pad_index, sink,
sink_pad->index,
- MEDIA_LNK_FL_ENABLED |
- MEDIA_LNK_FL_IMMU
[linux-sunxi] [PATCH v2 06/19] dt-bindings: media: sun6i-a31-csi: Add MIPI CSI-2 input port
The A31 CSI controller supports two distinct input interfaces:
parallel and an external MIPI CSI-2 bridge. The parallel interface
is often connected to a set of hardware pins while the MIPI CSI-2
bridge is an internal FIFO-ish link. As a result, these two inputs
are distinguished as two different ports.
Note that only one of the two may be present on a controller instance.
For example, the V3s has one controller dedicated to MIPI-CSI2 and one
dedicated to parallel.
Update the binding with an explicit ports node that holds two distinct
port nodes: one for parallel input and one for MIPI CSI-2.
This is backward-compatible with the single-port approach that was
previously taken for representing the parallel interface port, which
stays enumerated as fwnode port 0. However, it is now marked as
deprecated and the multi-port approach should be preferred.
Note that additional ports may be added in the future, especially to
support feeding the CSI controller's output to the ISP.
Signed-off-by: Paul Kocialkowski
---
.../media/allwinner,sun6i-a31-csi.yaml| 86 ---
1 file changed, 73 insertions(+), 13 deletions(-)
diff --git
a/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-csi.yaml
b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-csi.yaml
index 1fd9b5532a21..3bcee2d44f3c 100644
--- a/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-csi.yaml
+++ b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-csi.yaml
@@ -43,6 +43,7 @@ properties:
# See ./video-interfaces.txt for details
port:
type: object
+deprecated: true
properties:
endpoint:
@@ -67,6 +68,59 @@ properties:
additionalProperties: false
+ ports:
+type: object
+
+properties:
+ port@0:
+type: object
+description: Parallel input port, connect to a parallel sensor
+
+properties:
+ reg:
+const: 0
+
+ endpoint:
+type: object
+
+properties:
+ remote-endpoint: true
+
+ bus-width:
+enum: [ 8, 10, 12, 16 ]
+
+ pclk-sample: true
+ hsync-active: true
+ vsync-active: true
+
+required:
+ - bus-width
+ - remote-endpoint
+
+required:
+ - endpoint
+
+additionalProperties: false
+
+ port@1:
+type: object
+description: MIPI CSI-2 bridge input port
+
+properties:
+ reg:
+const: 1
+
+ endpoint:
+type: object
+
+properties:
+ remote-endpoint: true
+
+required:
+ - remote-endpoint
+
+additionalProperties: false
+
required:
- compatible
- reg
@@ -95,19 +149,25 @@ examples:
"ram";
resets = < RST_BUS_CSI>;
-port {
-/* Parallel bus endpoint */
-csi1_ep: endpoint {
-remote-endpoint = <_ep>;
-bus-width = <16>;
-
-/*
- * If hsync-active/vsync-active are missing,
- * embedded BT.656 sync is used.
- */
- hsync-active = <0>; /* Active low */
- vsync-active = <0>; /* Active low */
- pclk-sample = <1>; /* Rising */
+ports {
+#address-cells = <1>;
+#size-cells = <0>;
+
+port@0 {
+reg = <0>;
+/* Parallel bus endpoint */
+csi1_ep: endpoint {
+remote-endpoint = <_ep>;
+bus-width = <16>;
+
+/*
+ * If hsync-active/vsync-active are missing,
+ * embedded BT.656 sync is used.
+ */
+ hsync-active = <0>; /* Active low */
+ vsync-active = <0>; /* Active low */
+ pclk-sample = <1>; /* Rising */
+};
};
};
};
--
2.29.2
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[linux-sunxi] [PATCH v2 05/19] media: sun6i-csi: Only configure the interface data width for parallel
Bits related to the interface data width are only applicable to the
parallel interface and are irrelevant when the CSI controller is taking
input from the MIPI CSI-2 controller.
In prevision of adding support for this case, set these bits
conditionally so there is no ambiguity. The conditional block is
moved around before the interlaced conditional block for nicer code
symmetry (conditional blocks first) while at it.
Co-developed-by: Kévin L'hôpital
Signed-off-by: Kévin L'hôpital
Signed-off-by: Paul Kocialkowski
---
.../platform/sunxi/sun6i-csi/sun6i_csi.c | 42 +++
1 file changed, 25 insertions(+), 17 deletions(-)
diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
index 531a4cccd14a..f1150de94e98 100644
--- a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
+++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
@@ -378,8 +378,13 @@ static void sun6i_csi_setup_bus(struct sun6i_csi_dev *sdev)
unsigned char bus_width;
u32 flags;
u32 cfg;
+ bool input_parallel = false;
bool input_interlaced = false;
+ if (endpoint->bus_type == V4L2_MBUS_PARALLEL ||
+ endpoint->bus_type == V4L2_MBUS_BT656)
+ input_parallel = true;
+
if (csi->config.field == V4L2_FIELD_INTERLACED
|| csi->config.field == V4L2_FIELD_INTERLACED_TB
|| csi->config.field == V4L2_FIELD_INTERLACED_BT)
@@ -395,6 +400,26 @@ static void sun6i_csi_setup_bus(struct sun6i_csi_dev *sdev)
CSI_IF_CFG_HREF_POL_MASK | CSI_IF_CFG_FIELD_MASK |
CSI_IF_CFG_SRC_TYPE_MASK);
+ if (input_parallel) {
+ switch (bus_width) {
+ case 8:
+ cfg |= CSI_IF_CFG_IF_DATA_WIDTH_8BIT;
+ break;
+ case 10:
+ cfg |= CSI_IF_CFG_IF_DATA_WIDTH_10BIT;
+ break;
+ case 12:
+ cfg |= CSI_IF_CFG_IF_DATA_WIDTH_12BIT;
+ break;
+ case 16: /* No need to configure DATA_WIDTH for 16bit */
+ break;
+ default:
+ dev_warn(sdev->dev, "Unsupported bus width: %u\n",
+bus_width);
+ break;
+ }
+ }
+
if (input_interlaced)
cfg |= CSI_IF_CFG_SRC_TYPE_INTERLACED;
else
@@ -440,23 +465,6 @@ static void sun6i_csi_setup_bus(struct sun6i_csi_dev *sdev)
break;
}
- switch (bus_width) {
- case 8:
- cfg |= CSI_IF_CFG_IF_DATA_WIDTH_8BIT;
- break;
- case 10:
- cfg |= CSI_IF_CFG_IF_DATA_WIDTH_10BIT;
- break;
- case 12:
- cfg |= CSI_IF_CFG_IF_DATA_WIDTH_12BIT;
- break;
- case 16: /* No need to configure DATA_WIDTH for 16bit */
- break;
- default:
- dev_warn(sdev->dev, "Unsupported bus width: %u\n", bus_width);
- break;
- }
-
regmap_write(sdev->regmap, CSI_IF_CFG_REG, cfg);
}
--
2.29.2
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[linux-sunxi] [PATCH v2 04/19] media: sun6i-csi: Use common V4L2 format info for storage bpp
V4L2 has a common helper which can be used for calculating the number
of stored bits per pixels of a given (stored) image format.
Use the helper-returned structure instead of our own switch/case list.
Note that a few formats are not in that list so we keep them as
special cases.
The custom switch/case was also wrong concerning 10/12-bit Bayer
formats, which are aligned to 16 bits in memory. Using the common
helper fixes it.
Fixes: 5cc7522d8965 ("media: sun6i: Add support for Allwinner CSI V3s")
Signed-off-by: Paul Kocialkowski
---
.../platform/sunxi/sun6i-csi/sun6i_csi.h | 55 +++
1 file changed, 20 insertions(+), 35 deletions(-)
diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.h
b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.h
index c626821aaedb..092445f04c60 100644
--- a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.h
+++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.h
@@ -86,53 +86,38 @@ void sun6i_csi_update_buf_addr(struct sun6i_csi *csi,
dma_addr_t addr);
*/
void sun6i_csi_set_stream(struct sun6i_csi *csi, bool enable);
-/* get bpp form v4l2 pixformat */
+/* get memory storage bpp from v4l2 pixformat */
static inline int sun6i_csi_get_bpp(unsigned int pixformat)
{
+ const struct v4l2_format_info *info;
+ unsigned int i;
+ int bpp = 0;
+
+ /* Handle special cases unknown to V4L2 format info first. */
switch (pixformat) {
- case V4L2_PIX_FMT_SBGGR8:
- case V4L2_PIX_FMT_SGBRG8:
- case V4L2_PIX_FMT_SGRBG8:
- case V4L2_PIX_FMT_SRGGB8:
case V4L2_PIX_FMT_JPEG:
return 8;
- case V4L2_PIX_FMT_SBGGR10:
- case V4L2_PIX_FMT_SGBRG10:
- case V4L2_PIX_FMT_SGRBG10:
- case V4L2_PIX_FMT_SRGGB10:
- return 10;
- case V4L2_PIX_FMT_SBGGR12:
- case V4L2_PIX_FMT_SGBRG12:
- case V4L2_PIX_FMT_SGRBG12:
- case V4L2_PIX_FMT_SRGGB12:
case V4L2_PIX_FMT_HM12:
- case V4L2_PIX_FMT_NV12:
- case V4L2_PIX_FMT_NV21:
- case V4L2_PIX_FMT_YUV420:
- case V4L2_PIX_FMT_YVU420:
return 12;
- case V4L2_PIX_FMT_YUYV:
- case V4L2_PIX_FMT_YVYU:
- case V4L2_PIX_FMT_UYVY:
- case V4L2_PIX_FMT_VYUY:
- case V4L2_PIX_FMT_NV16:
- case V4L2_PIX_FMT_NV61:
- case V4L2_PIX_FMT_YUV422P:
- case V4L2_PIX_FMT_RGB565:
case V4L2_PIX_FMT_RGB565X:
return 16;
- case V4L2_PIX_FMT_RGB24:
- case V4L2_PIX_FMT_BGR24:
- return 24;
- case V4L2_PIX_FMT_RGB32:
- case V4L2_PIX_FMT_BGR32:
- return 32;
- default:
+ }
+
+ info = v4l2_format_info(pixformat);
+ if (!info) {
WARN(1, "Unsupported pixformat: 0x%x\n", pixformat);
- break;
+ return 0;
+ }
+
+ for (i = 0; i < info->comp_planes; i++) {
+ unsigned int hdiv = (i == 0) ? 1 : info->hdiv;
+ unsigned int vdiv = (i == 0) ? 1 : info->vdiv;
+
+ /* We return bits per pixel while V4L2 format info is bytes. */
+ bpp += 8 * info->bpp[i] / hdiv / vdiv;
}
- return 0;
+ return bpp;
}
#endif /* __SUN6I_CSI_H__ */
--
2.29.2
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[linux-sunxi] [PATCH v2 02/19] phy: Distinguish between Rx and Tx for MIPI D-PHY with submodes
As some D-PHY controllers support both Rx and Tx mode, we need a way for
users to explicitly request one or the other. For instance, Rx mode can
be used along with MIPI CSI-2 while Tx mode can be used with MIPI DSI.
Introduce new MIPI D-PHY PHY submodes to use with PHY_MODE_MIPI_DPHY.
The default (zero value) is kept to Tx so only the rkisp1 driver, which
uses D-PHY in Rx mode, needs to be adapted.
Signed-off-by: Paul Kocialkowski
Acked-by: Helen Koike
---
drivers/staging/media/rkisp1/rkisp1-isp.c | 3 ++-
include/linux/phy/phy-mipi-dphy.h | 13 +
2 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/staging/media/rkisp1/rkisp1-isp.c
b/drivers/staging/media/rkisp1/rkisp1-isp.c
index a9715b0b7264..f1167995688a 100644
--- a/drivers/staging/media/rkisp1/rkisp1-isp.c
+++ b/drivers/staging/media/rkisp1/rkisp1-isp.c
@@ -914,7 +914,8 @@ static int rkisp1_mipi_csi2_start(struct rkisp1_isp *isp,
phy_mipi_dphy_get_default_config(pixel_clock, isp->sink_fmt->bus_width,
sensor->lanes, cfg);
- phy_set_mode(sensor->dphy, PHY_MODE_MIPI_DPHY);
+ phy_set_mode_ext(cdev->dphy, PHY_MODE_MIPI_DPHY,
+PHY_MIPI_DPHY_SUBMODE_RX);
phy_configure(sensor->dphy, );
phy_power_on(sensor->dphy);
diff --git a/include/linux/phy/phy-mipi-dphy.h
b/include/linux/phy/phy-mipi-dphy.h
index a877ffee845d..0f57ef46a8b5 100644
--- a/include/linux/phy/phy-mipi-dphy.h
+++ b/include/linux/phy/phy-mipi-dphy.h
@@ -6,6 +6,19 @@
#ifndef __PHY_MIPI_DPHY_H_
#define __PHY_MIPI_DPHY_H_
+/**
+ * enum phy_mipi_dphy_submode - MIPI D-PHY sub-mode
+ *
+ * A MIPI D-PHY can be used to transmit or receive data.
+ * Since some controllers can support both, the direction to enable is
specified
+ * with the PHY sub-mode. Transmit is assumed by default with phy_set_mode.
+ */
+
+enum phy_mipi_dphy_submode {
+ PHY_MIPI_DPHY_SUBMODE_TX = 0,
+ PHY_MIPI_DPHY_SUBMODE_RX,
+};
+
/**
* struct phy_configure_opts_mipi_dphy - MIPI D-PHY configuration set
*
--
2.29.2
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[linux-sunxi] [PATCH v2 03/19] phy: allwinner: phy-sun6i-mipi-dphy: Support D-PHY Rx mode for MIPI CSI-2
The Allwinner A31 D-PHY supports both Rx and Tx modes. While the latter
is already supported and used for MIPI DSI this adds support for the
former, to be used with MIPI CSI-2.
This implementation is inspired by Allwinner's V3s Linux SDK
implementation, which was used as a documentation base.
Signed-off-by: Paul Kocialkowski
---
drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 164 +++-
1 file changed, 160 insertions(+), 4 deletions(-)
diff --git a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
index 1fa761ba6cbb..0389b6b670d6 100644
--- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
+++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
@@ -24,6 +24,14 @@
#define SUN6I_DPHY_TX_CTL_REG 0x04
#define SUN6I_DPHY_TX_CTL_HS_TX_CLK_CONT BIT(28)
+#define SUN6I_DPHY_RX_CTL_REG 0x08
+#define SUN6I_DPHY_RX_CTL_EN_DBC BIT(31)
+#define SUN6I_DPHY_RX_CTL_RX_CLK_FORCE BIT(24)
+#define SUN6I_DPHY_RX_CTL_RX_D3_FORCE BIT(23)
+#define SUN6I_DPHY_RX_CTL_RX_D2_FORCE BIT(22)
+#define SUN6I_DPHY_RX_CTL_RX_D1_FORCE BIT(21)
+#define SUN6I_DPHY_RX_CTL_RX_D0_FORCE BIT(20)
+
#define SUN6I_DPHY_TX_TIME0_REG0x10
#define SUN6I_DPHY_TX_TIME0_HS_TRAIL(n)(((n) & 0xff) << 24)
#define SUN6I_DPHY_TX_TIME0_HS_PREPARE(n) (((n) & 0xff) << 16)
@@ -44,12 +52,29 @@
#define SUN6I_DPHY_TX_TIME4_HS_TX_ANA1(n) (((n) & 0xff) << 8)
#define SUN6I_DPHY_TX_TIME4_HS_TX_ANA0(n) ((n) & 0xff)
+#define SUN6I_DPHY_RX_TIME0_REG0x30
+#define SUN6I_DPHY_RX_TIME0_HS_RX_SYNC(n) (((n) & 0xff) << 24)
+#define SUN6I_DPHY_RX_TIME0_HS_RX_CLK_MISS(n) (((n) & 0xff) << 16)
+#define SUN6I_DPHY_RX_TIME0_LP_RX(n) (((n) & 0xff) << 8)
+
+#define SUN6I_DPHY_RX_TIME1_REG0x34
+#define SUN6I_DPHY_RX_TIME1_RX_DLY(n) (((n) & 0xfff) << 20)
+#define SUN6I_DPHY_RX_TIME1_LP_RX_ULPS_WP(n) ((n) & 0xf)
+
+#define SUN6I_DPHY_RX_TIME2_REG0x38
+#define SUN6I_DPHY_RX_TIME2_HS_RX_ANA1(n) (((n) & 0xff) << 8)
+#define SUN6I_DPHY_RX_TIME2_HS_RX_ANA0(n) ((n) & 0xff)
+
+#define SUN6I_DPHY_RX_TIME3_REG0x40
+#define SUN6I_DPHY_RX_TIME3_LPRST_DLY(n) (((n) & 0x) << 16)
+
#define SUN6I_DPHY_ANA0_REG0x4c
#define SUN6I_DPHY_ANA0_REG_PWSBIT(31)
#define SUN6I_DPHY_ANA0_REG_DMPC BIT(28)
#define SUN6I_DPHY_ANA0_REG_DMPD(n)(((n) & 0xf) << 24)
#define SUN6I_DPHY_ANA0_REG_SLV(n) (((n) & 7) << 12)
#define SUN6I_DPHY_ANA0_REG_DEN(n) (((n) & 0xf) << 8)
+#define SUN6I_DPHY_ANA0_REG_SFB(n) (((n) & 3) << 2)
#define SUN6I_DPHY_ANA1_REG0x50
#define SUN6I_DPHY_ANA1_REG_VTTMODEBIT(31)
@@ -92,6 +117,8 @@ struct sun6i_dphy {
struct phy *phy;
struct phy_configure_opts_mipi_dphy config;
+
+ int submode;
};
static int sun6i_dphy_init(struct phy *phy)
@@ -105,6 +132,18 @@ static int sun6i_dphy_init(struct phy *phy)
return 0;
}
+static int sun6i_dphy_set_mode(struct phy *phy, enum phy_mode mode, int
submode)
+{
+ struct sun6i_dphy *dphy = phy_get_drvdata(phy);
+
+ if (mode != PHY_MODE_MIPI_DPHY)
+ return -EINVAL;
+
+ dphy->submode = submode;
+
+ return 0;
+}
+
static int sun6i_dphy_configure(struct phy *phy, union phy_configure_opts
*opts)
{
struct sun6i_dphy *dphy = phy_get_drvdata(phy);
@@ -119,9 +158,8 @@ static int sun6i_dphy_configure(struct phy *phy, union
phy_configure_opts *opts)
return 0;
}
-static int sun6i_dphy_power_on(struct phy *phy)
+static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy)
{
- struct sun6i_dphy *dphy = phy_get_drvdata(phy);
u8 lanes_mask = GENMASK(dphy->config.lanes - 1, 0);
regmap_write(dphy->regs, SUN6I_DPHY_TX_CTL_REG,
@@ -211,12 +249,129 @@ static int sun6i_dphy_power_on(struct phy *phy)
return 0;
}
+static int sun6i_dphy_rx_power_on(struct sun6i_dphy *dphy)
+{
+ /* Physical clock rate is actually half of symbol rate with DDR. */
+ unsigned long mipi_symbol_rate = dphy->config.hs_clk_rate;
+ unsigned long dphy_clk_rate;
+ unsigned int rx_dly;
+ unsigned int lprst_dly;
+ u32 value;
+
+ dphy_clk_rate = clk_get_rate(dphy->mod_clk);
+ if (!dphy_clk_rate)
+ return -EINVAL;
+
+ /* Hardcoded timing parameters from the Allwinner BSP. */
+ regmap_write(dphy->regs, SUN6I_DPHY_RX_TIME0_REG,
+SUN6I_DPHY_RX_TIME0_HS_RX_SYNC(255) |
+SUN6I_DPHY_RX_TIME0_HS_RX_CLK_MISS(255) |
+SUN6I_DPHY_RX_TIME0_LP_RX(255));
+
+ /*
+
[linux-sunxi] [PATCH v2 01/19] docs: phy: Add a part about PHY mode and submode
Besides giving pointers to the relevant functions for PHY mode and submode configuration, this clarifies the need to set them before powering on the PHY. Signed-off-by: Paul Kocialkowski --- Documentation/driver-api/phy/phy.rst | 18 ++ 1 file changed, 18 insertions(+) diff --git a/Documentation/driver-api/phy/phy.rst b/Documentation/driver-api/phy/phy.rst index 8fc1ce0bb905..6cbc72707a49 100644 --- a/Documentation/driver-api/phy/phy.rst +++ b/Documentation/driver-api/phy/phy.rst @@ -195,3 +195,21 @@ DeviceTree Binding The documentation for PHY dt binding can be found @ Documentation/devicetree/bindings/phy/phy-bindings.txt + +PHY Mode and Submode + + +Once a reference to a PHY is obtained by a controller, the PHY can be configured +to a PHY mode and submode. PHY modes are described in the `phy_mode` enum while +submodes are specific to the selected PHY mode. + +Mode and submode configuration is done by calling:: + + int phy_set_mode_ext(struct phy *phy, enum phy_mode mode, int submode); + +If no submode is to be configured, users can call:: + + int phy_set_mode(struct phy *phy, enum phy_mode mode); + +The PHY mode and submode must not be configured after the PHY has already been +powered on. -- 2.29.2 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/20201128142839.517949-2-paul.kocialkowski%40bootlin.com.
[linux-sunxi] [PATCH v2 00/19] Allwinner MIPI CSI-2 support for A31/V3s/A83T
): Exposure: (max - min) % step != 0 warn: v4l2-test-controls.cpp(92): Gain: (max - min) % step != 0 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK test VIDIOC_QUERYCTRL: OK test VIDIOC_G/S_CTRL: OK test VIDIOC_G/S/TRY_EXT_CTRLS: OK test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK test VIDIOC_G/S_JPEGCOMP: OK (Not Supported) Standard Controls: 11 Private Controls: 0 Format ioctls (Input 0): test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK test VIDIOC_G/S_PARM: OK (Not Supported) test VIDIOC_G_FBUF: OK (Not Supported) test VIDIOC_G_FMT: OK test VIDIOC_TRY_FMT: OK test VIDIOC_S_FMT: OK test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported) test Cropping: OK (Not Supported) test Composing: OK (Not Supported) test Scaling: OK Codec ioctls (Input 0): test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported) test VIDIOC_G_ENC_INDEX: OK (Not Supported) test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported) Buffer ioctls (Input 0): test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK test VIDIOC_EXPBUF: OK test Requests: OK (Not Supported) Total for sun6i-video device /dev/video0: 45, Succeeded: 45, Failed: 0, Warnings: 6 Paul Kocialkowski (19): docs: phy: Add a part about PHY mode and submode phy: Distinguish between Rx and Tx for MIPI D-PHY with submodes phy: allwinner: phy-sun6i-mipi-dphy: Support D-PHY Rx mode for MIPI CSI-2 media: sun6i-csi: Use common V4L2 format info for storage bpp media: sun6i-csi: Only configure the interface data width for parallel dt-bindings: media: sun6i-a31-csi: Add MIPI CSI-2 input port media: sun6i-csi: Add support for MIPI CSI-2 bridge input ARM: dts: sun8i: a83t: Add CSI controller ports ARM: dts: sunxi: h3/h5: Add CSI controller port for parallel input ARM: dts: sun8i: v3s: Add CSI1 controller port for parallel input arm64: dts: allwinner: a64: Add CSI controller port for parallel input dt-bindings: media: Add A31 MIPI CSI-2 bindings documentation media: sunxi: Add support for the A31 MIPI CSI-2 controller ARM: dts: sun8i: v3s: Add nodes for MIPI CSI-2 support MAINTAINERS: Add entry for the Allwinner A31 MIPI CSI-2 bridge dt-bindings: media: Add A83T MIPI CSI-2 bindings documentation media: sunxi: Add support for the A83T MIPI CSI-2 controller ARM: dts: sun8i: a83t: Add MIPI CSI-2 controller node MAINTAINERS: Add entry for the Allwinner A83T MIPI CSI-2 bridge .../media/allwinner,sun6i-a31-csi.yaml| 86 ++- .../media/allwinner,sun6i-a31-mipi-csi2.yaml | 151 .../media/allwinner,sun8i-a83t-mipi-csi2.yaml | 147 Documentation/driver-api/phy/phy.rst | 18 + MAINTAINERS | 16 + arch/arm/boot/dts/sun8i-a83t.dtsi | 38 +- arch/arm/boot/dts/sun8i-v3s.dtsi | 77 ++ arch/arm/boot/dts/sunxi-h3-h5.dtsi| 9 + arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 9 + drivers/media/platform/sunxi/Kconfig | 2 + drivers/media/platform/sunxi/Makefile | 2 + .../platform/sunxi/sun6i-csi/sun6i_csi.c | 165 +++-- .../platform/sunxi/sun6i-csi/sun6i_csi.h | 58 +- .../platform/sunxi/sun6i-csi/sun6i_video.c| 53 +- .../platform/sunxi/sun6i-csi/sun6i_video.h| 7 +- .../platform/sunxi/sun6i-mipi-csi2/Kconfig| 12 + .../platform/sunxi/sun6i-mipi-csi2/Makefile | 4 + .../sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.c | 591 .../sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.h | 117 .../sunxi/sun8i-a83t-mipi-csi2/Kconfig| 11 + .../sunxi/sun8i-a83t-mipi-csi2/Makefile | 4 + .../sun8i-a83t-mipi-csi2/sun8i_a83t_dphy.c| 92 +++ .../sun8i-a83t-mipi-csi2/sun8i_a83t_dphy.h| 39 ++ .../sun8i_a83t_mipi_csi2.c| 657 ++ .../sun8i_a83t_mipi_csi2.h| 197 ++ drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 164 - drivers/staging/media/rkisp1/rkisp1-isp.c | 3 +- include/linux/phy/phy-mipi-dphy.h | 13 + 28 files changed, 2620 insertions(+), 122 deletions(-) create mode 100644 Documentation/devicetree/bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml create mode 100644 Documentation/devicetree/bindings/media/allwinner,sun8i-a83t-mipi-csi2.yaml create mode 100644 drivers/media/platform/sunxi/sun6i-mipi-csi2/Kconfig create mode 100644 drivers/media/platform/sunxi/sun6i-mipi-csi2/Makefile create mode 100644 drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.c create mode 100644 drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.h create mode 100644 drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/Kconfig create mode 100644 drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/Makefile create mode 100644 drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_dphy.c create mode 100644 drivers/media
[linux-sunxi] Re: [PATCH 00/14] Allwinner MIPI CSI-2 support for A31/V3s/A83T
Hi, On Wed 04 Nov 20, 13:36, Helen Koike wrote: > Hi Paul, > > On 11/4/20 8:11 AM, Paul Kocialkowski wrote: > > Hi Helen, > > > > On Fri 30 Oct 20, 19:44, Helen Koike wrote: > >> Hi Paul, > >> > >> I have some comments through the series, I hope this helps. > > > > Thanks for your comments :) > > > >> On 10/23/20 2:45 PM, Paul Kocialkowski wrote: > >>> This series introduces support for MIPI CSI-2, with the A31 controller > >>> that is > >>> found on most SoCs (A31, V3s and probably V5) as well as the A83T-specific > >>> controller. While the former uses the same MIPI D-PHY that is already > >>> supported > >>> for DSI, the latter embeds its own D-PHY. > >>> > >>> In order to distinguish the use of the D-PHY between Rx mode (for MIPI > >>> CSI-2) > >>> and Tx mode (for MIPI DSI), a submode is introduced for D-PHY in the PHY > >>> API. > >>> This allows adding Rx support in the A31 D-PHY driver. > >>> > >>> A few changes and fixes are applied to the A31 CSI controller driver, in > >>> order > >>> to support the MIPI CSI-2 use-case. > >>> > >>> Follows is the V4L2 device topology representing the interactions between > >>> the MIPI CSI-2 sensor, the MIPI CSI-2 controller (which controls the > >>> D-PHY) > >>> and the CSI controller: > >>> - entity 1: sun6i-csi (1 pad, 1 link) > >>> type Node subtype V4L flags 0 > >>> device node name /dev/video0 > >>> pad0: Sink > >>> <- "sun6i-mipi-csi2":1 [ENABLED,IMMUTABLE] > >>> > >>> - entity 5: sun6i-mipi-csi2 (2 pads, 2 links) > >>> type V4L2 subdev subtype Unknown flags 0 > >>> pad0: Sink > >>> <- "ov5648 0-0036":0 [ENABLED,IMMUTABLE] > >>> pad1: Source > >>> -> "sun6i-csi":0 [ENABLED,IMMUTABLE] > >>> > >>> - entity 8: ov5648 0-0036 (1 pad, 1 link) > >>> type V4L2 subdev subtype Sensor flags 0 > >>> device node name /dev/v4l-subdev0 > >> > >> Question: I noticed is that sun6i-mipi-csi2 doesn't expose a node under > >> /dev/, but the sensor > >> exposes it. Probably because it uses V4L2_SUBDEV_FL_HAS_DEVNODE and > >> sun6i-csi() calls > >> v4l2_device_register_subdev_nodes(). > >> > >> I find this weird from a userspace pov, since usually we don't mix manual > >> and auto propagation > >> of the configs, so I started wondering if sun6i-csi driver should be > >> calling > >> v4l2_device_register_subdev_nodes() in the first place. > > > > I must admit that I didn't really pay attention to that, but since > > sun6i-mipi-csi2 is basically a bridge driver, it doesn't make sense to apply > > manual configuration to it. It is actually designed to forward most subdev > > ops > > to its own subdev so configuring it manually would actually result in > > configuring the sensor. > > Ack, then maybe sun6i-csi needs a patch removing the call to > v4l2_device_register_subdev_nodes() Apparently Sakari suggested that we do need a subdev node for the MIPI CSI-2 bridge so I'll just do that. This implementation that fowards the ops to the sensor was apparently a mistake. Paul > > > > XXX > > > >> Also, sun6i-csi doesn't seem to be used by any board dts (it's declared on > >> the dtsi, but I > >> didn't find any dts enabling it), so I wonder if it would be a bad thing > >> if we update it. > >> > >>> pad0: Source > >>> [fmt:SBGGR8_1X8/640x480@1/30 field:none colorspace:raw > >>> xfer:none ycbcr:601 quantization:full-range] > >>> -> "sun6i-mipi-csi2":0 [ENABLED,IMMUTABLE] > >> > >> If I understand correctly, this is very similar to ipu3: > >> sensor->bus->dma_engine > >> > >> in the case of ipu3-cio2: > >> sensor->ipu3-csi2->ipu3-cio2 > >> > >> in this case: > >> ov5648->sun6i-mipi-csi2->sun6i-csi > > > > Yes this is the correct picture. > > > >> On thing that is confusing me is the name csi2 with csi (that makes me > >> think of csi > >> version one, which is not the case), I would rename it to sun6i-video (or > >> maybe > >> it is just
[linux-sunxi] Re: [PATCH 08/14] media: sunxi: Add support for the A31 MIPI CSI-2 controller
Hi Sakari and thanks for the review! On Thu 05 Nov 20, 10:45, Sakari Ailus wrote: > On Fri, Oct 23, 2020 at 07:45:40PM +0200, Paul Kocialkowski wrote: > > The A31 MIPI CSI-2 controller is a dedicated MIPI CSI-2 controller > > found on Allwinner SoCs such as the A31 and V3/V3s. > > > > It is a standalone block, connected to the CSI controller on one side > > and to the MIPI D-PHY block on the other. It has a dedicated address > > space, interrupt line and clock. > > > > Currently, the MIPI CSI-2 controller is hard-tied to a specific CSI > > controller (CSI0) but newer SoCs (such as the V5) may allow switching > > MIPI CSI-2 controllers between CSI controllers. > > > > It is represented as a V4L2 subdev to the CSI controller and takes a > > MIPI CSI-2 sensor as its own subdev, all using the fwnode graph and > > media controller API. > > > > Signed-off-by: Paul Kocialkowski > > --- > > drivers/media/platform/sunxi/Kconfig | 1 + > > drivers/media/platform/sunxi/Makefile | 1 + > > .../platform/sunxi/sun6i-mipi-csi2/Kconfig| 11 + > > .../platform/sunxi/sun6i-mipi-csi2/Makefile | 4 + > > .../sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.c | 635 ++ > > .../sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.h | 116 > > 6 files changed, 768 insertions(+) > > create mode 100644 drivers/media/platform/sunxi/sun6i-mipi-csi2/Kconfig > > create mode 100644 drivers/media/platform/sunxi/sun6i-mipi-csi2/Makefile > > create mode 100644 > > drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.c > > create mode 100644 > > drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.h > > > > diff --git a/drivers/media/platform/sunxi/Kconfig > > b/drivers/media/platform/sunxi/Kconfig > > index 7151cc249afa..9684e07454ad 100644 > > --- a/drivers/media/platform/sunxi/Kconfig > > +++ b/drivers/media/platform/sunxi/Kconfig > > @@ -2,3 +2,4 @@ > > > > source "drivers/media/platform/sunxi/sun4i-csi/Kconfig" > > source "drivers/media/platform/sunxi/sun6i-csi/Kconfig" > > +source "drivers/media/platform/sunxi/sun6i-mipi-csi2/Kconfig" > > diff --git a/drivers/media/platform/sunxi/Makefile > > b/drivers/media/platform/sunxi/Makefile > > index fc537c9f5ca9..887a7cae8fca 100644 > > --- a/drivers/media/platform/sunxi/Makefile > > +++ b/drivers/media/platform/sunxi/Makefile > > @@ -2,5 +2,6 @@ > > > > obj-y += sun4i-csi/ > > obj-y += sun6i-csi/ > > +obj-y += sun6i-mipi-csi2/ > > obj-y += sun8i-di/ > > obj-y += sun8i-rotate/ > > diff --git a/drivers/media/platform/sunxi/sun6i-mipi-csi2/Kconfig > > b/drivers/media/platform/sunxi/sun6i-mipi-csi2/Kconfig > > new file mode 100644 > > index ..7033bda483b4 > > --- /dev/null > > +++ b/drivers/media/platform/sunxi/sun6i-mipi-csi2/Kconfig > > @@ -0,0 +1,11 @@ > > +# SPDX-License-Identifier: GPL-2.0-only > > +config VIDEO_SUN6I_MIPI_CSI2 > > + tristate "Allwinner A31 MIPI CSI-2 Controller Driver" > > + depends on VIDEO_V4L2 && COMMON_CLK > > + depends on ARCH_SUNXI || COMPILE_TEST > > + select MEDIA_CONTROLLER > > + select VIDEO_V4L2_SUBDEV_API > > + select REGMAP_MMIO > > + select V4L2_FWNODE > > + help > > + Support for the Allwinner A31 MIPI CSI-2 Controller. > > diff --git a/drivers/media/platform/sunxi/sun6i-mipi-csi2/Makefile > > b/drivers/media/platform/sunxi/sun6i-mipi-csi2/Makefile > > new file mode 100644 > > index ..14e4e03818b5 > > --- /dev/null > > +++ b/drivers/media/platform/sunxi/sun6i-mipi-csi2/Makefile > > @@ -0,0 +1,4 @@ > > +# SPDX-License-Identifier: GPL-2.0-only > > +sun6i-mipi-csi2-y += sun6i_mipi_csi2.o > > + > > +obj-$(CONFIG_VIDEO_SUN6I_MIPI_CSI2) += sun6i-mipi-csi2.o > > diff --git a/drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.c > > b/drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.c > > new file mode 100644 > > index ..ce89c35f5b86 > > --- /dev/null > > +++ b/drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.c > > @@ -0,0 +1,635 @@ > > +// SPDX-License-Identifier: GPL-2.0+ > > +/* > > + * Copyright 2020 Bootlin > > + * Author: Paul Kocialkowski > > + */ > > + > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > >
[linux-sunxi] Re: [PATCH 08/14] media: sunxi: Add support for the A31 MIPI CSI-2 controller
Hi,
On Wed 04 Nov 20, 19:56, Maxime Ripard wrote:
> On Wed, Nov 04, 2020 at 12:34:58PM +0100, Paul Kocialkowski wrote:
> > > > + regmap_write(regmap, SUN6I_MIPI_CSI2_CFG_REG,
> > > > +SUN6I_MIPI_CSI2_CFG_CHANNEL_MODE(1) |
> > > > +SUN6I_MIPI_CSI2_CFG_LANE_COUNT(lanes_count));
> > >
> > > It's not really clear what the channel is here? The number of virtual
> > > channels? Something else?
> >
> > That's somewhat described in the controller documentation. Channels refers
> > to
> > physical channels of the controller, which can be used to redirect data
> > matching either a specific data type, a specific virtual channel, or both.
> > There's a somewhat similar concept of channels in the CSI controller too.
> >
> > We're currently only using one...
> >
> > > > + regmap_write(regmap, SUN6I_MIPI_CSI2_VCDT_RX_REG,
> > > > +SUN6I_MIPI_CSI2_VCDT_RX_CH_VC(3, 3) |
> > > > +SUN6I_MIPI_CSI2_VCDT_RX_CH_VC(2, 2) |
> > > > +SUN6I_MIPI_CSI2_VCDT_RX_CH_VC(1, 1) |
> > > > +SUN6I_MIPI_CSI2_VCDT_RX_CH_VC(0, 0) |
> > > > +SUN6I_MIPI_CSI2_VCDT_RX_CH_DT(0, data_type));
> >
> > ... but it's safer to configure them all to virtual channel numbers so we
> > don't
> > end up with multiple channels matching virtual channel 0.
> >
> > I'll add a comment about that.
>
> Maybe we should have pads for all of them then, even if we don't support
> changing anything?
If that's something we can add later (I think it is), I would rather do this in
a sub-sequent series to keep the current one lightweight and merged ASAP.
It would also require some investigation to find out if the MIPI CSI-2 channel
number i goes directly to the CSI controller channel number i or if some
remapping can take place.
What do you think?
> > > > +static const struct v4l2_subdev_pad_ops sun6i_mipi_csi2_subdev_pad_ops
> > > > = {
> > > > + .enum_mbus_code = sun6i_mipi_csi2_enum_mbus_code,
> > > > + .get_fmt= sun6i_mipi_csi2_get_fmt,
> > > > + .set_fmt= sun6i_mipi_csi2_set_fmt,
> > > > + .enum_frame_size= sun6i_mipi_csi2_enum_frame_size,
> > > > + .enum_frame_interval= sun6i_mipi_csi2_enum_frame_interval,
> > > > +};
> > > > +
> > > > +/* Subdev */
> > > > +
> > > > +static const struct v4l2_subdev_ops sun6i_mipi_csi2_subdev_ops = {
> > > > + .core = _mipi_csi2_subdev_core_ops,
> > > > + .video = _mipi_csi2_subdev_video_ops,
> > > > + .pad= _mipi_csi2_subdev_pad_ops,
> > > > +};
> > > > +
> > > > +/* Notifier */
> > > > +
> > > > +static int sun6i_mipi_csi2_notifier_bound(struct v4l2_async_notifier
> > > > *notifier,
> > > > + struct v4l2_subdev
> > > > *remote_subdev,
> > > > + struct v4l2_async_subdev
> > > > *remote_subdev_async)
> > > > +{
> > > > + struct v4l2_subdev *subdev = notifier->sd;
> > > > + struct sun6i_mipi_csi2_video *video =
> > > > + sun6i_mipi_csi2_subdev_video(subdev);
> > > > + struct sun6i_mipi_csi2_dev *cdev =
> > > > sun6i_mipi_csi2_video_dev(video);
> > > > + int source_pad;
> > > > + int ret;
> > > > +
> > > > + source_pad = media_entity_get_fwnode_pad(_subdev->entity,
> > > > +remote_subdev->fwnode,
> > > > +MEDIA_PAD_FL_SOURCE);
> > > > + if (source_pad < 0)
> > > > + return source_pad;
> > > > +
> > > > + ret = media_create_pad_link(_subdev->entity, source_pad,
> > > > + >entity, 0,
> > > > + MEDIA_LNK_FL_ENABLED |
> > > > + MEDIA_LNK_FL_IMMUTABLE);
> > > > + if (ret) {
> > > > + dev_err(cdev->dev, "failed to create %s:%u -> %s:%u
> > > > link\n",
> > > > + remote_subdev->entity.name, source_pad,
>
[linux-sunxi] Re: [PATCH 08/14] media: sunxi: Add support for the A31 MIPI CSI-2 controller
Hi, On Mon 26 Oct 20, 17:54, Maxime Ripard wrote: > On Fri, Oct 23, 2020 at 07:45:40PM +0200, Paul Kocialkowski wrote: > > The A31 MIPI CSI-2 controller is a dedicated MIPI CSI-2 controller > > found on Allwinner SoCs such as the A31 and V3/V3s. > > > > It is a standalone block, connected to the CSI controller on one side > > and to the MIPI D-PHY block on the other. It has a dedicated address > > space, interrupt line and clock. > > > > Currently, the MIPI CSI-2 controller is hard-tied to a specific CSI > > controller (CSI0) but newer SoCs (such as the V5) may allow switching > > MIPI CSI-2 controllers between CSI controllers. > > > > It is represented as a V4L2 subdev to the CSI controller and takes a > > MIPI CSI-2 sensor as its own subdev, all using the fwnode graph and > > media controller API. > > > > Signed-off-by: Paul Kocialkowski > > --- > > drivers/media/platform/sunxi/Kconfig | 1 + > > drivers/media/platform/sunxi/Makefile | 1 + > > .../platform/sunxi/sun6i-mipi-csi2/Kconfig| 11 + > > .../platform/sunxi/sun6i-mipi-csi2/Makefile | 4 + > > .../sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.c | 635 ++ > > .../sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.h | 116 > > 6 files changed, 768 insertions(+) > > create mode 100644 drivers/media/platform/sunxi/sun6i-mipi-csi2/Kconfig > > create mode 100644 drivers/media/platform/sunxi/sun6i-mipi-csi2/Makefile > > create mode 100644 > > drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.c > > create mode 100644 > > drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.h > > > > diff --git a/drivers/media/platform/sunxi/Kconfig > > b/drivers/media/platform/sunxi/Kconfig > > index 7151cc249afa..9684e07454ad 100644 > > --- a/drivers/media/platform/sunxi/Kconfig > > +++ b/drivers/media/platform/sunxi/Kconfig > > @@ -2,3 +2,4 @@ > > > > source "drivers/media/platform/sunxi/sun4i-csi/Kconfig" > > source "drivers/media/platform/sunxi/sun6i-csi/Kconfig" > > +source "drivers/media/platform/sunxi/sun6i-mipi-csi2/Kconfig" > > diff --git a/drivers/media/platform/sunxi/Makefile > > b/drivers/media/platform/sunxi/Makefile > > index fc537c9f5ca9..887a7cae8fca 100644 > > --- a/drivers/media/platform/sunxi/Makefile > > +++ b/drivers/media/platform/sunxi/Makefile > > @@ -2,5 +2,6 @@ > > > > obj-y += sun4i-csi/ > > obj-y += sun6i-csi/ > > +obj-y += sun6i-mipi-csi2/ > > obj-y += sun8i-di/ > > obj-y += sun8i-rotate/ > > diff --git a/drivers/media/platform/sunxi/sun6i-mipi-csi2/Kconfig > > b/drivers/media/platform/sunxi/sun6i-mipi-csi2/Kconfig > > new file mode 100644 > > index ..7033bda483b4 > > --- /dev/null > > +++ b/drivers/media/platform/sunxi/sun6i-mipi-csi2/Kconfig > > @@ -0,0 +1,11 @@ > > +# SPDX-License-Identifier: GPL-2.0-only > > +config VIDEO_SUN6I_MIPI_CSI2 > > + tristate "Allwinner A31 MIPI CSI-2 Controller Driver" > > + depends on VIDEO_V4L2 && COMMON_CLK > > + depends on ARCH_SUNXI || COMPILE_TEST > > + select MEDIA_CONTROLLER > > + select VIDEO_V4L2_SUBDEV_API > > + select REGMAP_MMIO > > + select V4L2_FWNODE > > + help > > + Support for the Allwinner A31 MIPI CSI-2 Controller. > > diff --git a/drivers/media/platform/sunxi/sun6i-mipi-csi2/Makefile > > b/drivers/media/platform/sunxi/sun6i-mipi-csi2/Makefile > > new file mode 100644 > > index ..14e4e03818b5 > > --- /dev/null > > +++ b/drivers/media/platform/sunxi/sun6i-mipi-csi2/Makefile > > @@ -0,0 +1,4 @@ > > +# SPDX-License-Identifier: GPL-2.0-only > > +sun6i-mipi-csi2-y += sun6i_mipi_csi2.o > > + > > +obj-$(CONFIG_VIDEO_SUN6I_MIPI_CSI2) += sun6i-mipi-csi2.o > > diff --git a/drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.c > > b/drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.c > > new file mode 100644 > > index ..ce89c35f5b86 > > --- /dev/null > > +++ b/drivers/media/platform/sunxi/sun6i-mipi-csi2/sun6i_mipi_csi2.c > > @@ -0,0 +1,635 @@ > > +// SPDX-License-Identifier: GPL-2.0+ > > +/* > > + * Copyright 2020 Bootlin > > + * Author: Paul Kocialkowski > > + */ > > + > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#i
[linux-sunxi] Re: [PATCH 08/14] media: sunxi: Add support for the A31 MIPI CSI-2 controller
Hi, On Mon 02 Nov 20, 10:21, Maxime Ripard wrote: > On Fri, Oct 30, 2020 at 07:45:18PM -0300, Helen Koike wrote: > > On 10/23/20 2:45 PM, Paul Kocialkowski wrote: > > > The A31 MIPI CSI-2 controller is a dedicated MIPI CSI-2 controller > > > found on Allwinner SoCs such as the A31 and V3/V3s. > > > > > > It is a standalone block, connected to the CSI controller on one side > > > and to the MIPI D-PHY block on the other. It has a dedicated address > > > space, interrupt line and clock. > > > > > > Currently, the MIPI CSI-2 controller is hard-tied to a specific CSI > > > controller (CSI0) but newer SoCs (such as the V5) may allow switching > > > MIPI CSI-2 controllers between CSI controllers. > > > > > > It is represented as a V4L2 subdev to the CSI controller and takes a > > > MIPI CSI-2 sensor as its own subdev, all using the fwnode graph and > > > media controller API. > > > > Maybe this is a bad idea, but I was thinking: > > This driver basically just turn on/off and catch some interrupts for errors, > > and all the rest of v4l2 config you just forward to the next subdevice > > on the pipeline. > > > > So instead of exposing it as a subdevice, I was wondering if modeling > > this driver also through the phy subsystem wouldn't be cleaner, so > > you won't need all the v4l2 subdevice/topology boilerplate code that > > it seems you are not using (unless you have plans to add controls or > > some specific configuration on this node later). > > > > But this would require changes on the sun6i-csi driver. > > > > What do you think? > > Eventually we'll need to filter the virtual channels / datatypes I > guess, so it's definitely valuable to have it in v4l2 Agreed and like I mentionned in the discussion on 00/14 I don't think it would be a cleaner way to expose things. There's also the fact that newer SoCs like the V5 seem to allow connecting any MIPI CSI-2 controller to any CSI controller, so the graph representation is definitely welcome here. Paul -- Paul Kocialkowski, Bootlin Embedded Linux and kernel engineering https://bootlin.com -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/20201104111710.GB287014%40aptenodytes. signature.asc Description: PGP signature
[linux-sunxi] Re: [PATCH 00/14] Allwinner MIPI CSI-2 support for A31/V3s/A83T
Hi again, On Wed 04 Nov 20, 12:11, Paul Kocialkowski wrote: > Hi Helen, > > On Fri 30 Oct 20, 19:44, Helen Koike wrote: > > Hi Paul, > > > > I have some comments through the series, I hope this helps. > > Thanks for your comments :) > > > On 10/23/20 2:45 PM, Paul Kocialkowski wrote: > > > This series introduces support for MIPI CSI-2, with the A31 controller > > > that is > > > found on most SoCs (A31, V3s and probably V5) as well as the A83T-specific > > > controller. While the former uses the same MIPI D-PHY that is already > > > supported > > > for DSI, the latter embeds its own D-PHY. > > > > > > In order to distinguish the use of the D-PHY between Rx mode (for MIPI > > > CSI-2) > > > and Tx mode (for MIPI DSI), a submode is introduced for D-PHY in the PHY > > > API. > > > This allows adding Rx support in the A31 D-PHY driver. > > > > > > A few changes and fixes are applied to the A31 CSI controller driver, in > > > order > > > to support the MIPI CSI-2 use-case. > > > > > > Follows is the V4L2 device topology representing the interactions between > > > the MIPI CSI-2 sensor, the MIPI CSI-2 controller (which controls the > > > D-PHY) > > > and the CSI controller: > > > - entity 1: sun6i-csi (1 pad, 1 link) > > > type Node subtype V4L flags 0 > > > device node name /dev/video0 > > > pad0: Sink > > > <- "sun6i-mipi-csi2":1 [ENABLED,IMMUTABLE] > > > > > > - entity 5: sun6i-mipi-csi2 (2 pads, 2 links) > > > type V4L2 subdev subtype Unknown flags 0 > > > pad0: Sink > > > <- "ov5648 0-0036":0 [ENABLED,IMMUTABLE] > > > pad1: Source > > > -> "sun6i-csi":0 [ENABLED,IMMUTABLE] > > > > > > - entity 8: ov5648 0-0036 (1 pad, 1 link) > > > type V4L2 subdev subtype Sensor flags 0 > > > device node name /dev/v4l-subdev0 > > > > Question: I noticed is that sun6i-mipi-csi2 doesn't expose a node under > > /dev/, but the sensor > > exposes it. Probably because it uses V4L2_SUBDEV_FL_HAS_DEVNODE and > > sun6i-csi() calls > > v4l2_device_register_subdev_nodes(). > > > > I find this weird from a userspace pov, since usually we don't mix manual > > and auto propagation > > of the configs, so I started wondering if sun6i-csi driver should be calling > > v4l2_device_register_subdev_nodes() in the first place. > > I must admit that I didn't really pay attention to that, but since > sun6i-mipi-csi2 is basically a bridge driver, it doesn't make sense to apply > manual configuration to it. It is actually designed to forward most subdev ops > to its own subdev so configuring it manually would actually result in > configuring the sensor. > > XXX Hum, I meant to add something here and then forgot. I'm pretty new to auto vs manual propagation so I don't really have a clear opinion on this and whether we should consider removing the sensor /dev node as well. I'm satisfied with the way things are currently, but it might be due to my own ignorance. Paul > > Also, sun6i-csi doesn't seem to be used by any board dts (it's declared on > > the dtsi, but I > > didn't find any dts enabling it), so I wonder if it would be a bad thing if > > we update it. > > > > > pad0: Source > > > [fmt:SBGGR8_1X8/640x480@1/30 field:none colorspace:raw > > > xfer:none ycbcr:601 quantization:full-range] > > > -> "sun6i-mipi-csi2":0 [ENABLED,IMMUTABLE] > > > > If I understand correctly, this is very similar to ipu3: > > sensor->bus->dma_engine > > > > in the case of ipu3-cio2: > > sensor->ipu3-csi2->ipu3-cio2 > > > > in this case: > > ov5648->sun6i-mipi-csi2->sun6i-csi > > Yes this is the correct picture. > > > On thing that is confusing me is the name csi2 with csi (that makes me > > think of csi > > version one, which is not the case), I would rename it to sun6i-video (or > > maybe > > it is just me who gets confused). > > So the CSI name comes from the Allwinner litterature and implementation for > that > controller. Since it supports parallel input on its own, it does in fact > support > parallel CSI. The DMA engine part alone from that controller is also used for > MIPI CSI-2, so in this case the name looses its relevance. > > > I know this driver is already upstream and not pa
[linux-sunxi] Re: [PATCH 00/14] Allwinner MIPI CSI-2 support for A31/V3s/A83T
Hi Helen, On Fri 30 Oct 20, 19:44, Helen Koike wrote: > Hi Paul, > > I have some comments through the series, I hope this helps. Thanks for your comments :) > On 10/23/20 2:45 PM, Paul Kocialkowski wrote: > > This series introduces support for MIPI CSI-2, with the A31 controller that > > is > > found on most SoCs (A31, V3s and probably V5) as well as the A83T-specific > > controller. While the former uses the same MIPI D-PHY that is already > > supported > > for DSI, the latter embeds its own D-PHY. > > > > In order to distinguish the use of the D-PHY between Rx mode (for MIPI > > CSI-2) > > and Tx mode (for MIPI DSI), a submode is introduced for D-PHY in the PHY > > API. > > This allows adding Rx support in the A31 D-PHY driver. > > > > A few changes and fixes are applied to the A31 CSI controller driver, in > > order > > to support the MIPI CSI-2 use-case. > > > > Follows is the V4L2 device topology representing the interactions between > > the MIPI CSI-2 sensor, the MIPI CSI-2 controller (which controls the D-PHY) > > and the CSI controller: > > - entity 1: sun6i-csi (1 pad, 1 link) > > type Node subtype V4L flags 0 > > device node name /dev/video0 > > pad0: Sink > > <- "sun6i-mipi-csi2":1 [ENABLED,IMMUTABLE] > > > > - entity 5: sun6i-mipi-csi2 (2 pads, 2 links) > > type V4L2 subdev subtype Unknown flags 0 > > pad0: Sink > > <- "ov5648 0-0036":0 [ENABLED,IMMUTABLE] > > pad1: Source > > -> "sun6i-csi":0 [ENABLED,IMMUTABLE] > > > > - entity 8: ov5648 0-0036 (1 pad, 1 link) > > type V4L2 subdev subtype Sensor flags 0 > > device node name /dev/v4l-subdev0 > > Question: I noticed is that sun6i-mipi-csi2 doesn't expose a node under > /dev/, but the sensor > exposes it. Probably because it uses V4L2_SUBDEV_FL_HAS_DEVNODE and > sun6i-csi() calls > v4l2_device_register_subdev_nodes(). > > I find this weird from a userspace pov, since usually we don't mix manual and > auto propagation > of the configs, so I started wondering if sun6i-csi driver should be calling > v4l2_device_register_subdev_nodes() in the first place. I must admit that I didn't really pay attention to that, but since sun6i-mipi-csi2 is basically a bridge driver, it doesn't make sense to apply manual configuration to it. It is actually designed to forward most subdev ops to its own subdev so configuring it manually would actually result in configuring the sensor. XXX > Also, sun6i-csi doesn't seem to be used by any board dts (it's declared on > the dtsi, but I > didn't find any dts enabling it), so I wonder if it would be a bad thing if > we update it. > > > pad0: Source > > [fmt:SBGGR8_1X8/640x480@1/30 field:none colorspace:raw > > xfer:none ycbcr:601 quantization:full-range] > > -> "sun6i-mipi-csi2":0 [ENABLED,IMMUTABLE] > > If I understand correctly, this is very similar to ipu3: > sensor->bus->dma_engine > > in the case of ipu3-cio2: > sensor->ipu3-csi2->ipu3-cio2 > > in this case: > ov5648->sun6i-mipi-csi2->sun6i-csi Yes this is the correct picture. > On thing that is confusing me is the name csi2 with csi (that makes me think > of csi > version one, which is not the case), I would rename it to sun6i-video (or > maybe > it is just me who gets confused). So the CSI name comes from the Allwinner litterature and implementation for that controller. Since it supports parallel input on its own, it does in fact support parallel CSI. The DMA engine part alone from that controller is also used for MIPI CSI-2, so in this case the name looses its relevance. > I know this driver is already upstream and not part of this series, but on > the other hand it > doesn't seem to be used. Personally I don't find a rename to be necessary and while I agree that nothing would apparently prevent us from renaming it, I would prefer to keep the naming in line with Allwinner's litterature. > On another note, I always wonder if we should expose the bus in the topology, > I'm not > sure if it provides any useful API or information for userspace, and you > could have > a cleaner code (maybe code could be under phy subsystem). But at the same > time, it > seems this is a pattern on v4l2. > > I'd like to hear what others think on the above. My view on this is that we are dealing with two distinct controllers here, one that acts as a DMA engine and one that acts as a bridge. As a result, two chained subdevs looks like the most appropriate represen
[linux-sunxi] Re: [PATCH 04/14] media: sun6i-csi: Fix the image storage bpp for 10/12-bit Bayer formats
Hi Helen,
On Fri 30 Oct 20, 19:45, Helen Koike wrote:
> Hi Paul,
>
> On 10/23/20 2:45 PM, Paul Kocialkowski wrote:
> > Both 10 and 12-bit Bayer formats are stored aligned as 16-bit values
> > in memory, not unaligned 10 or 12 bits.
> >
> > Since the current code for retreiving the bpp is used only to
> > calculate the memory storage size of the picture (which is what
> > pixel formats describe, unlike media bus formats), fix it there.
> >
> > Fixes: 5cc7522d8965 ("media: sun6i: Add support for Allwinner CSI V3s")
> > Co-developed-by: Kévin L'hôpital
> > Signed-off-by: Kévin L'hôpital
> > Signed-off-by: Paul Kocialkowski
> > ---
> > .../platform/sunxi/sun6i-csi/sun6i_csi.h | 20 +--
> > 1 file changed, 10 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.h
> > b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.h
> > index c626821aaedb..7f2be70ae641 100644
> > --- a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.h
> > +++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.h
> > @@ -86,7 +86,7 @@ void sun6i_csi_update_buf_addr(struct sun6i_csi *csi,
> > dma_addr_t addr);
> > */
> > void sun6i_csi_set_stream(struct sun6i_csi *csi, bool enable);
> >
> > -/* get bpp form v4l2 pixformat */
> > +/* get memory storage bpp from v4l2 pixformat */
> > static inline int sun6i_csi_get_bpp(unsigned int pixformat)
> > {
> > switch (pixformat) {
> > @@ -96,15 +96,6 @@ static inline int sun6i_csi_get_bpp(unsigned int
> > pixformat)
> > case V4L2_PIX_FMT_SRGGB8:
> > case V4L2_PIX_FMT_JPEG:
> > return 8;
> > - case V4L2_PIX_FMT_SBGGR10:
> > - case V4L2_PIX_FMT_SGBRG10:
> > - case V4L2_PIX_FMT_SGRBG10:
> > - case V4L2_PIX_FMT_SRGGB10:
> > - return 10;
> > - case V4L2_PIX_FMT_SBGGR12:
> > - case V4L2_PIX_FMT_SGBRG12:
> > - case V4L2_PIX_FMT_SGRBG12:
> > - case V4L2_PIX_FMT_SRGGB12:
> > case V4L2_PIX_FMT_HM12:
> > case V4L2_PIX_FMT_NV12:
> > case V4L2_PIX_FMT_NV21:
> > @@ -121,6 +112,15 @@ static inline int sun6i_csi_get_bpp(unsigned int
> > pixformat)
> > case V4L2_PIX_FMT_RGB565:
> > case V4L2_PIX_FMT_RGB565X:
> > return 16;
> > + case V4L2_PIX_FMT_SBGGR10:
> > + case V4L2_PIX_FMT_SGBRG10:
> > + case V4L2_PIX_FMT_SGRBG10:
> > + case V4L2_PIX_FMT_SRGGB10:
> > + case V4L2_PIX_FMT_SBGGR12:
> > + case V4L2_PIX_FMT_SGBRG12:
> > + case V4L2_PIX_FMT_SGRBG12:
> > + case V4L2_PIX_FMT_SRGGB12:
> > + return 16;
> > case V4L2_PIX_FMT_RGB24:
> > case V4L2_PIX_FMT_BGR24:
> > return 24;
> >
>
> Instead of updating this table, how about using v4l2_format_info() instead?
Yes that would be a very good thing to do indeed!
Thanks,
Paul
--
Paul Kocialkowski, Bootlin
Embedded Linux and kernel engineering
https://bootlin.com
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[linux-sunxi] Re: [PATCH 02/14] phy: allwinner: phy-sun6i-mipi-dphy: Support D-PHY Rx mode for MIPI CSI-2
Hi Helen and thanks for the review,
On Fri 30 Oct 20, 19:44, Helen Koike wrote:
> On 10/23/20 2:45 PM, Paul Kocialkowski wrote:
> > The Allwinner A31 D-PHY supports both Rx and Tx modes. While the latter
> > is already supported and used for MIPI DSI this adds support for the
> > former, to be used with MIPI CSI-2.
> >
> > This implementation is inspired by the Allwinner BSP implementation.
> >
> > Signed-off-by: Paul Kocialkowski
> > ---
> > drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 164 +++-
> > 1 file changed, 160 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
> > b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
> > index 1fa761ba6cbb..8bcd4bb79f60 100644
> > --- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
> > +++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
> > @@ -24,6 +24,14 @@
> > #define SUN6I_DPHY_TX_CTL_REG 0x04
> > #define SUN6I_DPHY_TX_CTL_HS_TX_CLK_CONT BIT(28)
> >
> > +#define SUN6I_DPHY_RX_CTL_REG 0x08
> > +#define SUN6I_DPHY_RX_CTL_EN_DBC BIT(31)
> > +#define SUN6I_DPHY_RX_CTL_RX_CLK_FORCE BIT(24)
> > +#define SUN6I_DPHY_RX_CTL_RX_D3_FORCE BIT(23)
> > +#define SUN6I_DPHY_RX_CTL_RX_D2_FORCE BIT(22)
> > +#define SUN6I_DPHY_RX_CTL_RX_D1_FORCE BIT(21)
> > +#define SUN6I_DPHY_RX_CTL_RX_D0_FORCE BIT(20)
> > +
> > #define SUN6I_DPHY_TX_TIME0_REG0x10
> > #define SUN6I_DPHY_TX_TIME0_HS_TRAIL(n)(((n) & 0xff) << 24)
> > #define SUN6I_DPHY_TX_TIME0_HS_PREPARE(n) (((n) & 0xff) << 16)
> > @@ -44,12 +52,29 @@
> > #define SUN6I_DPHY_TX_TIME4_HS_TX_ANA1(n) (((n) & 0xff) << 8)
> > #define SUN6I_DPHY_TX_TIME4_HS_TX_ANA0(n) ((n) & 0xff)
> >
> > +#define SUN6I_DPHY_RX_TIME0_REG0x30
> > +#define SUN6I_DPHY_RX_TIME0_HS_RX_SYNC(n) (((n) & 0xff) << 24)
> > +#define SUN6I_DPHY_RX_TIME0_HS_RX_CLK_MISS(n) (((n) & 0xff) << 16)
> > +#define SUN6I_DPHY_RX_TIME0_LP_RX(n) (((n) & 0xff) << 8)
> > +
> > +#define SUN6I_DPHY_RX_TIME1_REG0x34
> > +#define SUN6I_DPHY_RX_TIME1_RX_DLY(n) (((n) & 0xfff) << 20)
> > +#define SUN6I_DPHY_RX_TIME1_LP_RX_ULPS_WP(n) ((n) & 0xf)
> > +
> > +#define SUN6I_DPHY_RX_TIME2_REG0x38
> > +#define SUN6I_DPHY_RX_TIME2_HS_RX_ANA1(n) (((n) & 0xff) << 8)
> > +#define SUN6I_DPHY_RX_TIME2_HS_RX_ANA0(n) ((n) & 0xff)
> > +
> > +#define SUN6I_DPHY_RX_TIME3_REG0x40
> > +#define SUN6I_DPHY_RX_TIME3_LPRST_DLY(n) (((n) & 0x) << 16)
> > +
> > #define SUN6I_DPHY_ANA0_REG0x4c
> > #define SUN6I_DPHY_ANA0_REG_PWSBIT(31)
> > #define SUN6I_DPHY_ANA0_REG_DMPC BIT(28)
> > #define SUN6I_DPHY_ANA0_REG_DMPD(n)(((n) & 0xf) << 24)
> > #define SUN6I_DPHY_ANA0_REG_SLV(n) (((n) & 7) << 12)
> > #define SUN6I_DPHY_ANA0_REG_DEN(n) (((n) & 0xf) << 8)
> > +#define SUN6I_DPHY_ANA0_REG_SFB(n) (((n) & 3) << 2)
> >
> > #define SUN6I_DPHY_ANA1_REG0x50
> > #define SUN6I_DPHY_ANA1_REG_VTTMODEBIT(31)
> > @@ -92,6 +117,8 @@ struct sun6i_dphy {
> >
> > struct phy *phy;
> > struct phy_configure_opts_mipi_dphy config;
> > +
> > + int submode;
> > };
> >
> > static int sun6i_dphy_init(struct phy *phy)
> > @@ -105,6 +132,18 @@ static int sun6i_dphy_init(struct phy *phy)
> > return 0;
> > }
> >
> > +static int sun6i_dphy_set_mode(struct phy *phy, enum phy_mode mode, int
> > submode)
> > +{
> > + struct sun6i_dphy *dphy = phy_get_drvdata(phy);
> > +
> > + if (mode != PHY_MODE_MIPI_DPHY)
> > + return -EINVAL;
> > +
> > + dphy->submode = submode;
>
> Shouldn't you check if the submode is valid here?
Yes that's a good point, thanks!
> > +
> > + return 0;
> > +}
> > +
> > static int sun6i_dphy_configure(struct phy *phy, union phy_configure_opts
> > *opts)
> > {
> > struct sun6i_dphy *dphy = phy_get_drvdata(phy);
> > @@ -119,9 +158,8 @@ static int sun6i_dphy_configure(struct phy *phy, union
> > phy_configure_opts *opts)
> > return 0;
> > }
> >
> > -static int sun6i_dphy_power_on(struct phy *phy)
> &
[linux-sunxi] Re: [PATCH 02/14] phy: allwinner: phy-sun6i-mipi-dphy: Support D-PHY Rx mode for MIPI CSI-2
Hi,
On Tue 27 Oct 20, 19:28, Maxime Ripard wrote:
>
> Hi,
>
> On Tue, Oct 27, 2020 at 10:23:26AM +0100, Paul Kocialkowski wrote:
> > On Mon 26 Oct 20, 16:38, Maxime Ripard wrote:
> > > On Fri, Oct 23, 2020 at 07:45:34PM +0200, Paul Kocialkowski wrote:
> > > > The Allwinner A31 D-PHY supports both Rx and Tx modes. While the latter
> > > > is already supported and used for MIPI DSI this adds support for the
> > > > former, to be used with MIPI CSI-2.
> > > >
> > > > This implementation is inspired by the Allwinner BSP implementation.
> > >
> > > Mentionning which BSP you took this from would be helpful
> >
> > Sure! It's from the Github repo linked from https://linux-sunxi.org/V3s.
> > Would you like that I mention this URL explicitly or would it be enough to
> > mention "Allwinner's V3s Linux SDK" as they seem to call it?
>
> Yeah, that would be great
> > > > +static int sun6i_dphy_rx_power_on(struct sun6i_dphy *dphy)
> > > > +{
> > > > + /* Physical clock rate is actually half of symbol rate with
> > > > DDR. */
> > > > + unsigned long mipi_symbol_rate = dphy->config.hs_clk_rate;
> > > > + unsigned long dphy_clk_rate;
> > > > + unsigned int rx_dly;
> > > > + unsigned int lprst_dly;
> > > > + u32 value;
> > > > +
> > > > + dphy_clk_rate = clk_get_rate(dphy->mod_clk);
> > > > + if (!dphy_clk_rate)
> > > > + return -1;
> > >
> > > Returning -1 is weird here?
> >
> > What do you think would be a more appropriate error code to return?
> > It looks like some other drivers return -EINVAL when that happens (but many
> > don't do the check).
>
> Yeah, EINVAL at least is better than ENOPERM
>
> > > > +
> > > > + /* Hardcoded timing parameters from the Allwinner BSP. */
> > > > + regmap_write(dphy->regs, SUN6I_DPHY_RX_TIME0_REG,
> > > > +SUN6I_DPHY_RX_TIME0_HS_RX_SYNC(255) |
> > > > +SUN6I_DPHY_RX_TIME0_HS_RX_CLK_MISS(255) |
> > > > +SUN6I_DPHY_RX_TIME0_LP_RX(255));
> > > > +
> > > > + /*
> > > > +* Formula from the Allwinner BSP, with hardcoded coefficients
> > > > +* (probably internal divider/multiplier).
> > > > +*/
> > > > + rx_dly = 8 * (unsigned int)(dphy_clk_rate / (mipi_symbol_rate /
> > > > 8));
> > > > +
> > > > + /*
> > > > +* The Allwinner BSP has an alternative formula for
> > > > LP_RX_ULPS_WP:
> > > > +* lp_ulps_wp_cnt = lp_ulps_wp_ms * lp_clk / 1000
> > > > +* but does not use it and hardcodes 255 instead.
> > > > +*/
> > > > + regmap_write(dphy->regs, SUN6I_DPHY_RX_TIME1_REG,
> > > > +SUN6I_DPHY_RX_TIME1_RX_DLY(rx_dly) |
> > > > +SUN6I_DPHY_RX_TIME1_LP_RX_ULPS_WP(255));
> > > > +
> > > > + /* HS_RX_ANA0 value is hardcoded in the Allwinner BSP. */
> > > > + regmap_write(dphy->regs, SUN6I_DPHY_RX_TIME2_REG,
> > > > +SUN6I_DPHY_RX_TIME2_HS_RX_ANA0(4));
> > > > +
> > > > + /*
> > > > +* Formula from the Allwinner BSP, with hardcoded coefficients
> > > > +* (probably internal divider/multiplier).
> > > > +*/
> > > > + lprst_dly = 4 * (unsigned int)(dphy_clk_rate /
> > > > (mipi_symbol_rate / 2));
> > > > +
> > > > + regmap_write(dphy->regs, SUN6I_DPHY_RX_TIME3_REG,
> > > > +SUN6I_DPHY_RX_TIME3_LPRST_DLY(lprst_dly));
> > > > +
> > > > + /* Analog parameters are hardcoded in the Allwinner BSP. */
> > > > + regmap_write(dphy->regs, SUN6I_DPHY_ANA0_REG,
> > > > +SUN6I_DPHY_ANA0_REG_PWS |
> > > > +SUN6I_DPHY_ANA0_REG_SLV(7) |
> > > > +SUN6I_DPHY_ANA0_REG_SFB(2));
> > > > +
> > > > + regmap_write(dphy->regs, SUN6I_DPHY_ANA1_REG,
> > > > +SUN6I_DPHY_ANA1_REG_SVTT(4));
> > > > +
> > > > + regmap_write(dphy->regs, SUN6I_DPHY_ANA4_REG,
> > > > +SUN6I_DPHY_ANA4_REG_DMPLVC |
> > &g
[linux-sunxi] Re: [PATCH 07/14] dt-bindings: media: i2c: Add A31 MIPI CSI-2 bindings documentation
Hi, On Tue 27 Oct 20, 19:44, Maxime Ripard wrote: > On Tue, Oct 27, 2020 at 10:52:21AM +0100, Paul Kocialkowski wrote: > > Hi, > > > > On Mon 26 Oct 20, 17:14, Maxime Ripard wrote: > > > i2c? :) > > > > Oops, good catch! > > > > > On Fri, Oct 23, 2020 at 07:45:39PM +0200, Paul Kocialkowski wrote: > > > > This introduces YAML bindings documentation for the A31 MIPI CSI-2 > > > > controller. > > > > > > > > Signed-off-by: Paul Kocialkowski > > > > --- > > > > .../media/allwinner,sun6i-a31-mipi-csi2.yaml | 168 ++ > > > > 1 file changed, 168 insertions(+) > > > > create mode 100644 > > > > Documentation/devicetree/bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml > > > > > > > > diff --git > > > > a/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml > > > > > > > > b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml > > > > new file mode 100644 > > > > index ..9adc0bc27033 > > > > --- /dev/null > > > > +++ > > > > b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml > > > > @@ -0,0 +1,168 @@ > > > > +# SPDX-License-Identifier: GPL-2.0 > > > > +%YAML 1.2 > > > > +--- > > > > +$id: > > > > http://devicetree.org/schemas/media/allwinner,sun6i-a31-mipi-csi2.yaml# > > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > > > + > > > > +title: Allwinner A31 MIPI CSI-2 Device Tree Bindings > > > > + > > > > +maintainers: > > > > + - Paul Kocialkowski > > > > + > > > > +properties: > > > > + compatible: > > > > +oneOf: > > > > + - const: allwinner,sun6i-a31-mipi-csi2 > > > > + - items: > > > > + - const: allwinner,sun8i-v3s-mipi-csi2 > > > > + - const: allwinner,sun6i-a31-mipi-csi2 > > > > + > > > > + reg: > > > > +maxItems: 1 > > > > + > > > > + interrupts: > > > > +maxItems: 1 > > > > + > > > > + clocks: > > > > +items: > > > > + - description: Bus Clock > > > > + - description: Module Clock > > > > + > > > > + clock-names: > > > > +items: > > > > + - const: bus > > > > + - const: mod > > > > + > > > > + phys: > > > > +items: > > > > + - description: MIPI D-PHY > > > > + > > > > + phy-names: > > > > +items: > > > > + - const: dphy > > > > + > > > > + resets: > > > > +maxItems: 1 > > > > + > > > > + # See ./video-interfaces.txt for details > > > > + ports: > > > > +type: object > > > > + > > > > +properties: > > > > + port@0: > > > > +type: object > > > > +description: Input port, connect to a MIPI CSI-2 sensor > > > > + > > > > +properties: > > > > + reg: > > > > +const: 0 > > > > + > > > > + endpoint: > > > > +type: object > > > > + > > > > +properties: > > > > + remote-endpoint: true > > > > + > > > > + bus-type: > > > > +const: 4 > > > > + > > > > + clock-lanes: > > > > +maxItems: 1 > > > > + > > > > + data-lanes: > > > > +minItems: 1 > > > > +maxItems: 4 > > > > + > > > > +required: > > > > + - bus-type > > > > + - data-lanes > > > > + - remote-endpoint > > > > + > > > > +additionalProperties: false > > > > + > > > > +required: > > > > + - endpoint > > > > + > > > > +additionalProperties: false > > > > + > > > > + port@1: > > > > +type: object > > > > +description: Output port, connect to a CSI controller >
[linux-sunxi] Re: [PATCH 12/14] media: sunxi: Add support for the A83T MIPI CSI-2 controller
Hi, On Mon 26 Oct 20, 18:00, Maxime Ripard wrote: > On Fri, Oct 23, 2020 at 07:45:44PM +0200, Paul Kocialkowski wrote: > > The A83T supports MIPI CSI-2 with a composite controller, covering both the > > protocol logic and the D-PHY implementation. This controller seems to be > > found > > on the A83T only and probably was abandonned since. > > > > This implementation splits the protocol and D-PHY registers and uses the PHY > > framework internally. The D-PHY is not registered as a standalone PHY driver > > since it cannot be used with any other controller. > > > > There are a few notable points about the controller: > > - The initialisation sequence involes writing specific magic init values > > that > > do not seem to make any particular sense given the concerned register > > fields. > > - Interrupts appear to be hitting regardless of the interrupt mask > > registers, > > which can cause a serious flood when transmission errors occur. > > Ah, so it's a separate driver too. > > > This work is based on the first version of the driver submitted by > > Kévin L'hôpital, which was adapted to mainline from the Allwinner BSP. > > This version integrates MIPI CSI-2 support as a standalone V4L2 subdev > > instead of merging it in the sun6i-csi driver. > > > > It was tested on a Banana Pi M3 board with an OV8865 sensor in a 4-lane > > configuration. > > Co-developped-by and SoB from Kevin? Not really. I wrote this driver from scratch and even significantly reworked the register descriptions to the point that I don't think it makes sense to consider that he's an author. For parts that can be considered a derivative work, copyright attribution was given in the header. Cheers, Paul > Looking at the driver, the same comments from the v3s apply there > > Maxime -- Paul Kocialkowski, Bootlin Embedded Linux and kernel engineering https://bootlin.com -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/20201104103731.GC285779%40aptenodytes. signature.asc Description: PGP signature
[linux-sunxi] Re: [PATCH 11/14] dt-bindings: media: i2c: Add A83T MIPI CSI-2 bindings documentation
Hi, On Mon 26 Oct 20, 17:56, Maxime Ripard wrote: > On Fri, Oct 23, 2020 at 07:45:43PM +0200, Paul Kocialkowski wrote: > > This introduces YAML bindings documentation for the A83T MIPI CSI-2 > > controller. > > > > Signed-off-by: Paul Kocialkowski > > What is the difference with the a31/v3s one? It's a different controller, not a variation of the A31 one. I'll rework the commit log to make this clearer. > > --- > > .../media/allwinner,sun8i-a83t-mipi-csi2.yaml | 158 ++ > > 1 file changed, 158 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/media/allwinner,sun8i-a83t-mipi-csi2.yaml > > > > diff --git > > a/Documentation/devicetree/bindings/media/allwinner,sun8i-a83t-mipi-csi2.yaml > > > > b/Documentation/devicetree/bindings/media/allwinner,sun8i-a83t-mipi-csi2.yaml > > new file mode 100644 > > index ..2384ae4e7be0 > > --- /dev/null > > +++ > > b/Documentation/devicetree/bindings/media/allwinner,sun8i-a83t-mipi-csi2.yaml > > @@ -0,0 +1,158 @@ > > +# SPDX-License-Identifier: GPL-2.0 > > +%YAML 1.2 > > +--- > > +$id: > > http://devicetree.org/schemas/media/allwinner,sun8i-a83t-mipi-csi2.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Allwinner A83T MIPI CSI-2 Device Tree Bindings > > + > > +maintainers: > > + - Paul Kocialkowski > > + > > +properties: > > + compatible: > > +const: allwinner,sun8i-a83t-mipi-csi2 > > + > > + reg: > > +maxItems: 1 > > + > > + interrupts: > > +maxItems: 1 > > + > > + clocks: > > +items: > > + - description: Bus Clock > > + - description: Module Clock > > + - description: MIPI-specific Clock > > + - description: Misc CSI Clock > > + > > + clock-names: > > +items: > > + - const: bus > > + - const: mod > > + - const: mipi > > + - const: misc > > If it's only due to the clock, it's soemething you can deal with in the > first schema, there's no need to duplicate them. It's a completely different controller so I don't think it makes sense to have a single schema for both. Even if the bindings look similar. Paul -- Paul Kocialkowski, Bootlin Embedded Linux and kernel engineering https://bootlin.com -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/20201104103332.GB285779%40aptenodytes. signature.asc Description: PGP signature
[linux-sunxi] Re: [PATCH 07/14] dt-bindings: media: i2c: Add A31 MIPI CSI-2 bindings documentation
Hi, On Mon 26 Oct 20, 17:14, Maxime Ripard wrote: > i2c? :) Oops, good catch! > On Fri, Oct 23, 2020 at 07:45:39PM +0200, Paul Kocialkowski wrote: > > This introduces YAML bindings documentation for the A31 MIPI CSI-2 > > controller. > > > > Signed-off-by: Paul Kocialkowski > > --- > > .../media/allwinner,sun6i-a31-mipi-csi2.yaml | 168 ++ > > 1 file changed, 168 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml > > > > diff --git > > a/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml > > > > b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml > > new file mode 100644 > > index ..9adc0bc27033 > > --- /dev/null > > +++ > > b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml > > @@ -0,0 +1,168 @@ > > +# SPDX-License-Identifier: GPL-2.0 > > +%YAML 1.2 > > +--- > > +$id: > > http://devicetree.org/schemas/media/allwinner,sun6i-a31-mipi-csi2.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Allwinner A31 MIPI CSI-2 Device Tree Bindings > > + > > +maintainers: > > + - Paul Kocialkowski > > + > > +properties: > > + compatible: > > +oneOf: > > + - const: allwinner,sun6i-a31-mipi-csi2 > > + - items: > > + - const: allwinner,sun8i-v3s-mipi-csi2 > > + - const: allwinner,sun6i-a31-mipi-csi2 > > + > > + reg: > > +maxItems: 1 > > + > > + interrupts: > > +maxItems: 1 > > + > > + clocks: > > +items: > > + - description: Bus Clock > > + - description: Module Clock > > + > > + clock-names: > > +items: > > + - const: bus > > + - const: mod > > + > > + phys: > > +items: > > + - description: MIPI D-PHY > > + > > + phy-names: > > +items: > > + - const: dphy > > + > > + resets: > > +maxItems: 1 > > + > > + # See ./video-interfaces.txt for details > > + ports: > > +type: object > > + > > +properties: > > + port@0: > > +type: object > > +description: Input port, connect to a MIPI CSI-2 sensor > > + > > +properties: > > + reg: > > +const: 0 > > + > > + endpoint: > > +type: object > > + > > +properties: > > + remote-endpoint: true > > + > > + bus-type: > > +const: 4 > > + > > + clock-lanes: > > +maxItems: 1 > > + > > + data-lanes: > > +minItems: 1 > > +maxItems: 4 > > + > > +required: > > + - bus-type > > + - data-lanes > > + - remote-endpoint > > + > > +additionalProperties: false > > + > > +required: > > + - endpoint > > + > > +additionalProperties: false > > + > > + port@1: > > +type: object > > +description: Output port, connect to a CSI controller > > + > > +properties: > > + reg: > > +const: 1 > > + > > + endpoint: > > +type: object > > + > > +properties: > > + remote-endpoint: true > > + > > + bus-type: > > +const: 4 > > That one seems a bit weird. If the input and output ports are using the > same format, what is that "bridge" supposed to be doing? Fair enough. What this represents is the internal link (likely a FIFO) between the two controllers. It is definitely not a MIPI CSI-2 bus but there's no mbus type for an internal link (probably because it's not a bus after all). Note that on the CSI controller side, we need the bus-type to be set to 4 for it to properly select the MIPI CSI-2 input. So it just felt more logical to have the same on the other side of the endpoint. On the other hand, we can just remove it on the MIPI CSI-2 controller side since it won't check it and have it fallback to the unknown mbus type. But that would make the types inconsistent on the two sides of the link. I don't think V4L2 will complain about it at the moment, but it would also make sense that it does eventually. What do you think? > > +
[linux-sunxi] Re: [PATCH 05/14] media: sun6i-csi: Only configure the interface data width for parallel
Hi,
On Mon 26 Oct 20, 17:00, Maxime Ripard wrote:
> On Fri, Oct 23, 2020 at 07:45:37PM +0200, Paul Kocialkowski wrote:
> > Bits related to the interface data width do not have any effect when
> > the CSI controller is taking input from the MIPI CSI-2 controller.
>
> I guess it would be clearer to mention that the data width is only
> applicable for parallel here.
Understood, will change the wording in the next version.
> > In prevision of adding support for this case, set these bits
> > conditionally so there is no ambiguity.
> >
> > Co-developed-by: Kévin L'hôpital
> > Signed-off-by: Kévin L'hôpital
> > Signed-off-by: Paul Kocialkowski
> > ---
> > .../platform/sunxi/sun6i-csi/sun6i_csi.c | 42 +++
> > 1 file changed, 25 insertions(+), 17 deletions(-)
> >
> > diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
> > b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
> > index 5d2389a5cd17..a876a05ea3c7 100644
> > --- a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
> > +++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
> > @@ -378,8 +378,13 @@ static void sun6i_csi_setup_bus(struct sun6i_csi_dev
> > *sdev)
> > unsigned char bus_width;
> > u32 flags;
> > u32 cfg;
> > + bool input_parallel = false;
> > bool input_interlaced = false;
> >
> > + if (endpoint->bus_type == V4L2_MBUS_PARALLEL ||
> > + endpoint->bus_type == V4L2_MBUS_BT656)
> > + input_parallel = true;
> > +
> > if (csi->config.field == V4L2_FIELD_INTERLACED
> > || csi->config.field == V4L2_FIELD_INTERLACED_TB
> > || csi->config.field == V4L2_FIELD_INTERLACED_BT)
> > @@ -395,6 +400,26 @@ static void sun6i_csi_setup_bus(struct sun6i_csi_dev
> > *sdev)
> > CSI_IF_CFG_HREF_POL_MASK | CSI_IF_CFG_FIELD_MASK |
> > CSI_IF_CFG_SRC_TYPE_MASK);
> >
> > + if (input_parallel) {
> > + switch (bus_width) {
> > + case 8:
> > + cfg |= CSI_IF_CFG_IF_DATA_WIDTH_8BIT;
> > + break;
> > + case 10:
> > + cfg |= CSI_IF_CFG_IF_DATA_WIDTH_10BIT;
> > + break;
> > + case 12:
> > + cfg |= CSI_IF_CFG_IF_DATA_WIDTH_12BIT;
> > + break;
> > + case 16: /* No need to configure DATA_WIDTH for 16bit */
> > + break;
> > + default:
> > + dev_warn(sdev->dev, "Unsupported bus width: %u\n",
> > +bus_width);
> > + break;
> > + }
> > + }
> > +
> > if (input_interlaced)
> > cfg |= CSI_IF_CFG_SRC_TYPE_INTERLACED;
> > else
> > @@ -440,23 +465,6 @@ static void sun6i_csi_setup_bus(struct sun6i_csi_dev
> > *sdev)
> > break;
> > }
> >
> > - switch (bus_width) {
> > - case 8:
> > - cfg |= CSI_IF_CFG_IF_DATA_WIDTH_8BIT;
> > - break;
> > - case 10:
> > - cfg |= CSI_IF_CFG_IF_DATA_WIDTH_10BIT;
> > - break;
> > - case 12:
> > - cfg |= CSI_IF_CFG_IF_DATA_WIDTH_12BIT;
> > - break;
> > - case 16: /* No need to configure DATA_WIDTH for 16bit */
> > - break;
> > - default:
> > - dev_warn(sdev->dev, "Unsupported bus width: %u\n", bus_width);
> > - break;
> > - }
> > -
>
> Is there any reason to move it around?
The main reason is cosmetics: input_parallel is introduced to match the already
existing input_interlaced variable, so it made sense to me to have both of these
conditionals one after the other instead of spreading them randomly.
I can mention this in the commit log if you prefer.
--
Paul Kocialkowski, Bootlin
Embedded Linux and kernel engineering
https://bootlin.com
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[linux-sunxi] Re: [PATCH 03/14] media: sun6i-csi: Support an optional dedicated memory pool
Hi,
On Mon 26 Oct 20, 16:41, Maxime Ripard wrote:
> On Fri, Oct 23, 2020 at 07:45:35PM +0200, Paul Kocialkowski wrote:
> > This allows selecting a dedicated CMA memory pool (specified via
> > device-tree) instead of the default one.
> >
> > Signed-off-by: Paul Kocialkowski
>
> Why would that be needed?
Sorry for the confusion, this is indeed unrelated to the current series and
it is not needed for MIPI CSI-2 support.
However, I think it's a worthwhile addition to the driver.
I will take it out of the series and re-submit it separately then.
> > ---
> > drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c | 8
> > 1 file changed, 8 insertions(+)
> >
> > diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
> > b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
> > index 28e89340fed9..5d2389a5cd17 100644
> > --- a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
> > +++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c
> > @@ -16,6 +16,7 @@
> > #include
> > #include
> > #include
> > +#include
> > #include
> > #include
> > #include
> > @@ -849,6 +850,12 @@ static int sun6i_csi_resource_request(struct
> > sun6i_csi_dev *sdev,
> > return PTR_ERR(sdev->regmap);
> > }
> >
> > + ret = of_reserved_mem_device_init(>dev);
> > + if (ret && ret != -ENODEV) {
> > + dev_err(>dev, "Unable to init reserved memory\n");
> > + return ret;
> > + }
> > +
> > sdev->clk_mod = devm_clk_get(>dev, "mod");
>
> If that clk_get or any subsequent function fail you'll end up leaking
> whatever the initialization of the reserved memory has allocated
Right, there's a missing of_reserved_mem_device_release in the error path here.
Thanks!
Paul
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[linux-sunxi] Re: [PATCH 02/14] phy: allwinner: phy-sun6i-mipi-dphy: Support D-PHY Rx mode for MIPI CSI-2
Hi,
On Mon 26 Oct 20, 16:38, Maxime Ripard wrote:
> On Fri, Oct 23, 2020 at 07:45:34PM +0200, Paul Kocialkowski wrote:
> > The Allwinner A31 D-PHY supports both Rx and Tx modes. While the latter
> > is already supported and used for MIPI DSI this adds support for the
> > former, to be used with MIPI CSI-2.
> >
> > This implementation is inspired by the Allwinner BSP implementation.
>
> Mentionning which BSP you took this from would be helpful
Sure! It's from the Github repo linked from https://linux-sunxi.org/V3s.
Would you like that I mention this URL explicitly or would it be enough to
mention "Allwinner's V3s Linux SDK" as they seem to call it?
> > Signed-off-by: Paul Kocialkowski
> > ---
> > drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 164 +++-
> > 1 file changed, 160 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
> > b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
> > index 1fa761ba6cbb..8bcd4bb79f60 100644
> > --- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
> > +++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
> > @@ -24,6 +24,14 @@
> > #define SUN6I_DPHY_TX_CTL_REG 0x04
> > #define SUN6I_DPHY_TX_CTL_HS_TX_CLK_CONT BIT(28)
> >
> > +#define SUN6I_DPHY_RX_CTL_REG 0x08
> > +#define SUN6I_DPHY_RX_CTL_EN_DBC BIT(31)
> > +#define SUN6I_DPHY_RX_CTL_RX_CLK_FORCE BIT(24)
> > +#define SUN6I_DPHY_RX_CTL_RX_D3_FORCE BIT(23)
> > +#define SUN6I_DPHY_RX_CTL_RX_D2_FORCE BIT(22)
> > +#define SUN6I_DPHY_RX_CTL_RX_D1_FORCE BIT(21)
> > +#define SUN6I_DPHY_RX_CTL_RX_D0_FORCE BIT(20)
> > +
>
> It's hard to tell from the diff, but it looks like you aligned the
> BIT(..) with the register?
That's correct, yes.
> If so, you should follow the what the rest of this driver (ie, one more
> indentation for register values).
I'll fix it in the next revision!
> > #define SUN6I_DPHY_TX_TIME0_REG0x10
> > #define SUN6I_DPHY_TX_TIME0_HS_TRAIL(n)(((n) & 0xff) << 24)
> > #define SUN6I_DPHY_TX_TIME0_HS_PREPARE(n) (((n) & 0xff) << 16)
> > @@ -44,12 +52,29 @@
> > #define SUN6I_DPHY_TX_TIME4_HS_TX_ANA1(n) (((n) & 0xff) << 8)
> > #define SUN6I_DPHY_TX_TIME4_HS_TX_ANA0(n) ((n) & 0xff)
> >
> > +#define SUN6I_DPHY_RX_TIME0_REG0x30
> > +#define SUN6I_DPHY_RX_TIME0_HS_RX_SYNC(n) (((n) & 0xff) << 24)
> > +#define SUN6I_DPHY_RX_TIME0_HS_RX_CLK_MISS(n) (((n) & 0xff) << 16)
> > +#define SUN6I_DPHY_RX_TIME0_LP_RX(n) (((n) & 0xff) << 8)
> > +
> > +#define SUN6I_DPHY_RX_TIME1_REG0x34
> > +#define SUN6I_DPHY_RX_TIME1_RX_DLY(n) (((n) & 0xfff) << 20)
> > +#define SUN6I_DPHY_RX_TIME1_LP_RX_ULPS_WP(n) ((n) & 0xf)
> > +
> > +#define SUN6I_DPHY_RX_TIME2_REG0x38
> > +#define SUN6I_DPHY_RX_TIME2_HS_RX_ANA1(n) (((n) & 0xff) << 8)
> > +#define SUN6I_DPHY_RX_TIME2_HS_RX_ANA0(n) ((n) & 0xff)
> > +
> > +#define SUN6I_DPHY_RX_TIME3_REG0x40
> > +#define SUN6I_DPHY_RX_TIME3_LPRST_DLY(n) (((n) & 0x) << 16)
> > +
> > #define SUN6I_DPHY_ANA0_REG0x4c
> > #define SUN6I_DPHY_ANA0_REG_PWSBIT(31)
> > #define SUN6I_DPHY_ANA0_REG_DMPC BIT(28)
> > #define SUN6I_DPHY_ANA0_REG_DMPD(n)(((n) & 0xf) << 24)
> > #define SUN6I_DPHY_ANA0_REG_SLV(n) (((n) & 7) << 12)
> > #define SUN6I_DPHY_ANA0_REG_DEN(n) (((n) & 0xf) << 8)
> > +#define SUN6I_DPHY_ANA0_REG_SFB(n) (((n) & 3) << 2)
> >
> > #define SUN6I_DPHY_ANA1_REG0x50
> > #define SUN6I_DPHY_ANA1_REG_VTTMODEBIT(31)
> > @@ -92,6 +117,8 @@ struct sun6i_dphy {
> >
> > struct phy *phy;
> > struct phy_configure_opts_mipi_dphy config;
> > +
> > + int submode;
> > };
> >
> > static int sun6i_dphy_init(struct phy *phy)
> > @@ -105,6 +132,18 @@ static int sun6i_dphy_init(struct phy *phy)
> > return 0;
> > }
> >
> > +static int sun6i_dphy_set_mode(struct phy *phy, enum phy_mode mode, int
> > submode)
> > +{
> > + struct sun6i_dphy *dphy = phy_get_drvdata(phy);
> > +
> > + if (mode != PHY_MODE_MIPI_DPHY)
> > + return -EINVAL;
> > +
> > + dphy->submode = submode;
> > +
> > + retur
Re: [linux-sunxi] [PATCH 01/14] phy: Distinguish between Rx and Tx for MIPI D-PHY with submodes
Hi Jernej,
On Fri 23 Oct 20, 20:18, Jernej Škrabec wrote:
> Dne petek, 23. oktober 2020 ob 19:45:33 CEST je Paul Kocialkowski napisal(a):
> > As some D-PHY controllers support both Rx and Tx mode, we need a way for
> > users to explicitly request one or the other. For instance, Rx mode can
> > be used along with MIPI CSI-2 while Tx mode can be used with MIPI DSI.
> >
> > Introduce new MIPI D-PHY PHY submodes to use with PHY_MODE_MIPI_DPHY.
> > The default (zero value) is kept to Tx so only the rkisp1 driver, which
> > uses D-PHY in Rx mode, needs to be adapted.
> >
> > Signed-off-by: Paul Kocialkowski
> > ---
> > drivers/staging/media/rkisp1/rkisp1-isp.c | 3 ++-
> > include/linux/phy/phy-mipi-dphy.h | 13 +
>
> I think some changes are missing in this patch. For example,
> phy_set_mode_ext() must be modified to take another argument, otherwise
> change
> of rkisp1-isp driver doesn't make much sense.
Thanks for looking into this! As you can see in:
https://elixir.bootlin.com/linux/latest/source/include/linux/phy/phy.h#L213
phy_set_mode_ext already takes a submode argument (which is already used for
USB mode selection, for instance) and phy_set_mode is just a macro which calls
phy_set_mode_ext with submode set to 0.
In our case, that means that most current users of phy_set_mode with
PHY_MODE_MIPI_DPHY will select Tx mode by default, so there is no particular
need for adaptation. Only the rkisp1 driver uses PHY_MODE_MIPI_DPHY for Rx,
so this one was changed to use phy_set_mode_ext with PHY_MIPI_DPHY_SUBMODE_RX
instead.
As a result, there should be no missing changes. Do you agree?
Cheers,
Paul
> Best regards,
> Jernej
>
> > 2 files changed, 15 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/staging/media/rkisp1/rkisp1-isp.c b/drivers/staging/
> media/rkisp1/rkisp1-isp.c
> > index 6ec1e9816e9f..0afbce00121e 100644
> > --- a/drivers/staging/media/rkisp1/rkisp1-isp.c
> > +++ b/drivers/staging/media/rkisp1/rkisp1-isp.c
> > @@ -902,7 +902,8 @@ static int rkisp1_mipi_csi2_start(struct rkisp1_isp
> *isp,
> >
> > phy_mipi_dphy_get_default_config(pixel_clock, isp->sink_fmt-
> >bus_width,
> > sensor->lanes, cfg);
> > - phy_set_mode(sensor->dphy, PHY_MODE_MIPI_DPHY);
> > + phy_set_mode_ext(cdev->dphy, PHY_MODE_MIPI_DPHY,
> > +PHY_MIPI_DPHY_SUBMODE_RX);
> > phy_configure(sensor->dphy, );
> > phy_power_on(sensor->dphy);
> >
> > diff --git a/include/linux/phy/phy-mipi-dphy.h b/include/linux/phy/phy-mipi-
> dphy.h
> > index a877ffee845d..0f57ef46a8b5 100644
> > --- a/include/linux/phy/phy-mipi-dphy.h
> > +++ b/include/linux/phy/phy-mipi-dphy.h
> > @@ -6,6 +6,19 @@
> > #ifndef __PHY_MIPI_DPHY_H_
> > #define __PHY_MIPI_DPHY_H_
> >
> > +/**
> > + * enum phy_mipi_dphy_submode - MIPI D-PHY sub-mode
> > + *
> > + * A MIPI D-PHY can be used to transmit or receive data.
> > + * Since some controllers can support both, the direction to enable is
> specified
> > + * with the PHY sub-mode. Transmit is assumed by default with phy_set_mode.
> > + */
> > +
> > +enum phy_mipi_dphy_submode {
> > + PHY_MIPI_DPHY_SUBMODE_TX = 0,
> > + PHY_MIPI_DPHY_SUBMODE_RX,
> > +};
> > +
> > /**
> > * struct phy_configure_opts_mipi_dphy - MIPI D-PHY configuration set
> > *
> > --
> > 2.28.0
> >
> > --
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> linux-sunxi/20201023174546.504028-2-paul.kocialkowski%40bootlin.com.
> >
>
>
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Embedded Linux and kernel engineering
https://bootlin.com
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