06, 2018 at 01:47:47PM +0200, Philipp Rossak wrote:
On 04.09.2018 18:46, Emmanuel Vadot wrote:
+ /* Data cells */
+ thermal_calibration: calib@234 {
+ reg = <0x234 0x8>;
+ };
You are declaring 8 bytes of calibratio
On 06.09.2018 14:04, Icenowy Zheng wrote:
于 2018年9月6日 GMT+08:00 下午7:51:15, Maxime Ripard 写到:
On Thu, Sep 06, 2018 at 01:47:47PM +0200, Philipp Rossak wrote:
On 04.09.2018 18:46, Emmanuel Vadot wrote:
+ /* Data cells */
+ thermal_calibration
On 04.09.2018 18:46, Emmanuel Vadot wrote:
+ /* Data cells */
+ thermal_calibration: calib@234 {
+ reg = <0x234 0x8>;
+ };
You are declaring 8 bytes of calibration data but to my knowledge it's
On 06.09.2018 09:24, Quentin Schulz wrote:
Hi Philipp,
On Thu, Aug 30, 2018 at 05:45:18PM +0200, Philipp Rossak wrote:
Since we have now thermal trotteling enabeled we can now add the full
range of the OPP table.
That's not the reason why they were not added.
Please see commit
On 02.09.2018 22:01, Jonathan Cameron wrote:
On Thu, 30 Aug 2018 17:44:53 +0200
Philipp Rossak wrote:
We are moving the SUN4I_GPADC_CHANNEL define to the header file.
Maxime has raised this point in other patches...
Why? Obvious what but I have no idea why you are doing this.
Thanks
On 02.09.2018 22:11, Jonathan Cameron wrote:
This feels like a good place to factor out the code into a utility
function that just does one of them. That should hopefully
reduce the indenting etc enough to make the code easier to read.
+ info->tzds[i].info = info;
+
On 31.08.2018 11:09, Maxime Ripard wrote:
+static int sun4i_ths_suspend(struct sun4i_gpadc_iio *info)
suspend is already a hook in the kernel, which hasn't the same meaning
than runtime_suspend (and the same applies to resume), so we'd rather
pick a better name. And all the functions (and
On 31.08.2018 11:11, Maxime Ripard wrote:
+ regmap_write(info->regmap, SUN8I_H3_THS_CTRL0,
+ SUN4I_GPADC_CTRL0_T_ACQ(0xff));
+
+ regmap_write(info->regmap, SUN8I_H3_THS_CTRL2,
+ SUN8I_H3_THS_ACQ1(0x3f));
+
+ regmap_write(info->regmap,
On 31.08.2018 11:51, Icenowy Zheng wrote:
Personally I suggest to leave out all SID or calibration related
patches here.
Currently we seems to be wrongly converting SID to big endian, however,
the orgnization of the THS calibration data on H6 shows that it's
surely little endian:
It
On 30.08.2018 22:00, Philipp Rossak wrote:
On 30.08.2018 18:27, Ondřej Jirman wrote:
+static int sun8i_h3_calibrate(struct sun4i_gpadc_iio *info)
+{
+// regmap_write(info->regmap, SUNXI_THS_CDATA_0_1,
+// info->calibration_data[0]);
+// regmap_write(info-&
On 30.08.2018 18:38, Ondřej Jirman wrote:
Hello,
On Thu, Aug 30, 2018 at 05:45:18PM +0200, Philipp Rossak wrote:
Since we have now thermal trotteling enabeled we can now add the full
range of the OPP table.
I'm not sure we can. I have a tablet with A83T SoC and it gets unstable
On 30.08.2018 18:27, Ondřej Jirman wrote:
+static int sun8i_h3_calibrate(struct sun4i_gpadc_iio *info)
+{
+// regmap_write(info->regmap, SUNXI_THS_CDATA_0_1,
+// info->calibration_data[0]);
+// regmap_write(info->regmap, SUNXI_THS_CDATA_2_3,
+//
This patch reworks the driver to support nvmem calibration cells.
The driver checks if the nvmem calibration is supported and reads out
the nvmem.
Signed-off-by: Philipp Rossak
---
drivers/iio/adc/sun4i-gpadc-iio.c | 24
1 file changed, 24 insertions(+)
diff --git
This patch adds the thermal zones to the H3. We have only one sensor and
that is placed in the cpu.
Signed-off-by: Philipp Rossak
---
arch/arm/boot/dts/sun8i-h3.dtsi| 31 +++
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 1 +
2 files changed, 32 insertions(+)
diff --git
This patch adds the missing compatible and the thermal sensor cells.
The H3 has one sensor.
Signed-off-by: Philipp Rossak
---
arch/arm/boot/dts/sun8i-h3.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index
The H3 SID is supported by the kernel so we can add a NVMEM Data cell,
that contains the calibration data.
On the H3 the eFuses are located at the offset 0x200. The thermal data
itself has an offset of 0x34 from the eFuse base. So we end on an offset
of 0x234.
Signed-off-by: Philipp Rossak
Since we have now thermal trotteling enabeled we can now add the full
range of the OPP table.
The operating points were found in Allwinner BSP and fex files.
Signed-off-by: Philipp Rossak
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 32
1 file changed, 32 insertions
This patch adds the thermal zones to the A83T. Sensor 0 is located
besides the cpu cluster 0. Sensor 1 is located besides cluster 1 and
sensor 2 is located besides in the gpu.
Signed-off-by: Philipp Rossak
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 103 ++
1
As we have gained the support for the thermal sensor in A83T,
we can now add its device nodes to the device tree.
The A83T seems to have a broken IRQ 31, thus we use here IRQ 41.
Signed-off-by: Philipp Rossak
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 8
1 file changed, 8 insertions
This patch enables the the sid controller in the H3. It can be used
for thermal calibration data.
Signed-off-by: Philipp Rossak
---
arch/arm/boot/dts/sun8i-h3.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index
This patch adds support for the A83T ths sensor.
The A83T supports interrupts. The interrupt is configured to update the
the sensor values every second.
Signed-off-by: Philipp Rossak
---
drivers/iio/adc/sun4i-gpadc-iio.c | 59 +
include/linux/iio/adc/sun4i
Different sensors will have different suspend and resume functions. So
we are modularize the suspend and resume functions.
The resume function configures and initializes the thermal sensor and
the suspend function disables the sensors.
Signed-off-by: Philipp Rossak
---
drivers/iio/adc/sun4i
This patch adds support for the H3 ths sensor.
The H3 supports interrupts. The interrupt is configured to update the
the sensor values every second. The calibration data is writen at the
begin of the init process.
Signed-off-by: Philipp Rossak
---
drivers/iio/adc/sun4i-gpadc-iio.c | 91
As we have gained the support for the thermal sensor in H3 and H5,
we can now add its device nodes to the device tree. The H3 and H5 share
most of its compatible. The compatible and the thermal sensor cells
will be added in an additional patch per device.
Signed-off-by: Philipp Rossak
---
arch
of an adc and a thermal sensor.
Signed-off-by: Philipp Rossak
---
drivers/iio/adc/sun4i-gpadc-iio.c | 63 +
include/linux/iio/adc/sun4i-gpadc.h | 3 ++
2 files changed, 46 insertions(+), 20 deletions(-)
diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c
b/drive
.
Signed-off-by: Philipp Rossak
---
drivers/iio/adc/sun4i-gpadc-iio.c | 72 +--
1 file changed, 70 insertions(+), 2 deletions(-)
diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c
b/drivers/iio/adc/sun4i-gpadc-iio.c
index c278e165e161..c12de48c4e86 100644
Since we reworked the sun4i-gpadc iio driver we can now remove the mfd
driver and move it's header to include/linux/iio/adc.
Signed-off-by: Philipp Rossak
---
drivers/iio/adc/sun4i-gpadc-iio.c| 2 +-
drivers/mfd/sun4i-gpadc.c| 181
To disable the driver we are removing the compatibles.
Signed-off-by: Philipp Rossak
---
drivers/iio/adc/sun4i-gpadc-iio.c | 9 -
1 file changed, 9 deletions(-)
diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c
b/drivers/iio/adc/sun4i-gpadc-iio.c
index 04d7147e0110..d95dd0fde2a6 100644
From: Icenowy Zheng
As the H3 SoC, which is also in sun8i line, has totally different
register map for the thermal sensor (a cut down version of GPADC), we
should rename A23/A33-specified registers to contain A33, in order to
prevent obfuscation with H3 registers. Currently these registers are
In the previous commit we removed the function call, now we remove the
unused functions.
Signed-off-by: Philipp Rossak
---
drivers/iio/adc/sun4i-gpadc-iio.c | 126 --
1 file changed, 126 deletions(-)
diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c
b/drivers
We want to use this driver mostly as thermal sensor, that still supports
the adc for the older chips, thus we threat the A33 as thermal sensor.
We also remove the adc channel without thermal support.
Signed-off-by: Philipp Rossak
---
drivers/iio/adc/sun4i-gpadc-iio.c | 19 ---
1
Since we have now new compatibles we can enable the SUN4I_GPADC driver
next to the sun4i-ts driver.
Signed-off-by: Philipp Rossak
---
arch/arm/configs/sunxi_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/sunxi_defconfig b/arch/arm/configs/sunxi_defconfig
index
We rework the irq handling and the adc_channel handling.
This is requiered since we merge the mfd driver into the adc driver.
Signed-off-by: Philipp Rossak
---
drivers/iio/adc/sun4i-gpadc-iio.c | 157 --
include/linux/mfd/sun4i-gpadc.h | 7 --
2 files
Since we are merging the mfd driver into the sun4i-gpadc driver we need
to remove the build options for the sun4i-gpadc driver.
Signed-off-by: Philipp Rossak
---
drivers/mfd/Makefile | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index
We are merging the mfd:sun4i-gpadc driver into the
iio/adc/sun4i-gpadc driver. So we need to remove the MFD_SUN4I_GPADC
config option.
Signed-off-by: Philipp Rossak
---
drivers/mfd/Kconfig | 17 -
1 file changed, 17 deletions(-)
diff --git a/drivers/mfd/Kconfig b/drivers/mfd
We are now adding the new compatibles.
Signed-off-by: Philipp Rossak
---
drivers/iio/adc/sun4i-gpadc-iio.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c
b/drivers/iio/adc/sun4i-gpadc-iio.c
index a2027614ee0c..79b8efdab803 100644
We are moving the SUN4I_GPADC_CHANNEL define to the header file.
Signed-off-by: Philipp Rossak
---
drivers/iio/adc/sun4i-gpadc-iio.c | 9 -
include/linux/mfd/sun4i-gpadc.h | 9 +
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c
and the reset was removed from the CCU. The THS in A83T
has a clock that is directly connected and runs with 24 MHz.
Update the binding document to cover H3 and A83T.
Signed-off-by: Philipp Rossak
---
.../devicetree/bindings/iio/adc/sun4i-gpadc.txt| 41 --
1 file changed
For adding newer sensor some basic rework of the code is necessary.
This commit reworks the code and uses regmap field to read out
temp_data.
Signed-off-by: Philipp Rossak
---
drivers/iio/adc/sun4i-gpadc-iio.c | 21 +
1 file changed, 13 insertions(+), 8 deletions(-)
diff
Since we are merging the mfd dirver into the adc driver we don't need
two different probing functions. Thus we remove the ofnode options
Signed-off-by: Philipp Rossak
---
drivers/iio/adc/sun4i-gpadc-iio.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/iio/adc
fix naming conventions of defines
* clarify commits
* update documentation to cover the new nvmem calibraion
* change nvmem calibration
Icenowy Zheng (1):
iio: adc: sun4i-gpadc-iio: rename A33-specified registers to contain
A33
Philipp Rossak (29):
mfd: Makefile: Re
Since we are merging the mfd driver into the iio adc driver we need to
update the Kconfig build options.
Signed-off-by: Philipp Rossak
---
drivers/iio/adc/Kconfig | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
:19, Kyle Evans wrote:
On Thu, Apr 19, 2018 at 10:13 AM, Icenowy Zheng <icen...@aosc.io> wrote:
于 2018年4月19日 GMT+08:00 下午11:11:22, Kyle Evans <kev...@freebsd.org> 写到:
On Mon, Jan 29, 2018 at 6:03 AM, Philipp Rossak <embe...@gmail.com>
wrote:
On 29.01.2018 10:52, Maxime Ripa
On 13.02.2018 13:29, Philipp Rossak wrote:
This patch series adds support for the sunxi A83T ir module and enhances
the sunxi-ir driver. Right now the base clock frequency for the ir driver
is a hard coded define and is set to 8 MHz.
This works for the most common ir receivers. On the Sinovoip
On 19.02.2018 09:10, Maxime Ripard wrote:
On Sat, Feb 17, 2018 at 03:22:35PM +0100, Philipp Rossak wrote:
Right now the performance govenor is the default frequency govenor on
sunxi devices. This causes some general problems.
When the cpu is idle the cpu runs with its maximum frequency
d clk output support")
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
Changes in v4:
* add more information to the comment
Changes in v3:
* add information when the bug appeared
* make the comment more clear
Changes in v2:
* add tag Fixes: ... t
frequency govenor to ondemand mode
and reduce the temperature when the cpu is idle and activate the thermal
throtteling.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
arch/arm/configs/sunxi_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/sunxi_defconfig
On 16.02.2018 13:59, Chen-Yu Tsai wrote:
On Fri, Feb 16, 2018 at 8:49 PM, Philipp Rossak <embe...@gmail.com> wrote:
On 16.02.2018 05:10, Chen-Yu Tsai wrote:
On Fri, Feb 16, 2018 at 1:53 AM, Philipp Rossak <embe...@gmail.com> wrote:
On 15.02.2018 15:11, Maxime Ripard wrot
On 16.02.2018 05:10, Chen-Yu Tsai wrote:
On Fri, Feb 16, 2018 at 1:53 AM, Philipp Rossak <embe...@gmail.com> wrote:
On 15.02.2018 15:11, Maxime Ripard wrote:
On Wed, Feb 14, 2018 at 02:56:12PM +0100, Philipp Rossak wrote:
This patch fixes a bug, that prevents the Allwinne
On 15.02.2018 15:11, Maxime Ripard wrote:
On Wed, Feb 14, 2018 at 02:56:12PM +0100, Philipp Rossak wrote:
This patch fixes a bug, that prevents the Allwinner A83T and the A80
from a successful boot.
The bug is there since v4.16-rc1 and appeared after the clk branch was
merged.
Out
On 15.02.2018 10:08, Maxime Ripard wrote:
On Wed, Feb 14, 2018 at 03:10:23PM +0100, Philipp Rossak wrote:
This patchseries fixes the bananapi m1 devicetree, to be able to boot again.
The first two patches update/improve the devicetree and the last patch adds
all missing regulators.
Regards
properties on the mmc0 and mmc2
node to use the allready existent regulators.
We can now remove the sunxi-common-regulators.dtsi include since we
don't need it anymore.
Fixes: 7daa21370075 ("ARM: dts: sunxi: Add regulators for Sinovoip
BPI-M2")
Signed-off-by: Philipp Rossak <embe
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts
b/arch/arm/boot/dts/sun6i-a31s-sinovoip-bpi-m2.dts
index 51e6f1d21c32..fb34f32502cf 10064
This patchseries fixes the bananapi m1 devicetree, to be able to boot again.
The first two patches update/improve the devicetree and the last patch adds
all missing regulators.
Regards,
Philipp
Changes since v1:
* squashed commit 1 and 3
* fix wrong mmc regulator
Philipp Rossak
d clk output support")
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
Changes in v3:
* add information when the bug appeared
* make the comment more clear
Changes in v2:
* add tag Fixes: ... to commit message
* add comment to if statement why we are
On 13.02.2018 14:44, Chen-Yu Tsai wrote:
On Tue, Feb 13, 2018 at 9:32 PM, Maxime Ripard
<maxime.rip...@bootlin.com> wrote:
On Tue, Feb 13, 2018 at 01:14:14PM +0100, Philipp Rossak wrote:
This patch fixes a bug, that prevents the Allwinner A83T and the A80
from a successful boot. You ca
The cir interface is like on the H3 located at 0x01f02000 and is exactly
the same. This patch adds support for the ir interface on the A83T.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 13 +
1 file changed, 13 insertions(+)
diff
This patch updates documentation for Device-Tree bindings for sunxi IR
controller and adds the new optional property for the base clock
frequency.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
Acked-by: Maxime Ripard <maxime.rip...@free-electrons.com>
Reviewed-by: Rob Herring <
,
than the default 8 MHz.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
Reviewed-by: Andi Shyti <andi.sh...@samsung.com>
Acked-by: Sean Young <s...@mess.org>
---
drivers/media/rc/sunxi-cir.c | 19 +++
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git
The CIR Pin of the A83T is located at PL12.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 7f4955a5fab7..f7f78a
The Bananapi M3 has an onboard IR receiver.
This enables the onboard IR receiver subnode.
Unlike the other IR receivers this one needs a base clock frequency
of 300 Hz (3 MHz), to be able to work.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
Acked-by: Chen-Yu Tsai <w...
The size of the register should be the size of the whole memory block,
not just the registers, that are needed.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/su
to clock-frequency
Regards,
Philipp
Philipp Rossak (6):
media: rc: update sunxi-ir driver to get base clock frequency from
devicetree
media: dt: bindings: Update binding documentation for sunxi IR
controller
arm: dts: sun8i: a83t: Add the cir pin for the A83T
arm: dts: sun8i: a83t: Add
if the return of the
clk_hw_get_parent_by_index is non zero. If it is zero we skip that
clock parent.
The BUG report could be found here: https://lkml.org/lkml/2018/2/10/198
Fixes: 04940631b8d2 ("rtc: ac100: Add clk output support")
Signed-off-by: Philipp Rossak <embe...@gmail.com>
--
On 13.02.2018 03:59, Chen-Yu Tsai wrote:
On Tue, Feb 13, 2018 at 9:25 AM, Philipp Rossak <embe...@gmail.com> wrote:
On 12.02.2018 19:21, Philipp Rossak wrote:
Hey,
When I try to boot my A31s (Bananapi M2) u-boot is showing only Starting
kernel ... . After enabling the earlyprintk I
On 12.02.2018 19:21, Philipp Rossak wrote:
Hey,
When I try to boot my A31s (Bananapi M2) u-boot is showing only Starting
kernel ... . After enabling the earlyprintk I could capture this log: [1].
After reverting those 5 commits from Chen-Yu I was able to boot again:
clk: sunxi-ng
Hey,
When I try to boot my A31s (Bananapi M2) u-boot is showing only Starting
kernel ... . After enabling the earlyprintk I could capture this log: [1].
After reverting those 5 commits from Chen-Yu I was able to boot again:
clk: sunxi-ng: Support fixed post-dividers on NM style clocks
On 30.01.2018 18:46, Philipp Rossak wrote:
This patch series adds support for the sunxi A83T ir module and enhances
the sunxi-ir driver. Right now the base clock frequency for the ir driver
is a hard coded define and is set to 8 MHz.
This works for the most common ir receivers. On the Sinovoip
Am Freitag, den 09.02.2018, 18:52 +0100 schrieb Philipp Rossak:
> This patch updates the vmmc-supply properties on the mmc0 and mmc2
> node to use the allready existent regulators.
> We can now remove the sunxi-common-regulators.dtsi include since we
> don't need it anymore.
>
Am Sonntag, den 11.02.2018, 10:55 +0300 schrieb Sergey Suloev:
> On 02/11/2018 01:07 AM, Philipp Rossak wrote:
> >
> >
> > On 10.02.2018 22:08, Sergey Suloev wrote:
> > > On 02/11/2018 12:01 AM, Philipp Rossak wrote:
> > > > Hey Sergey,
> >
Hey,
When I boot my A83T I get the following bootlog [1].
After some debugging, I found out that the function call:
clk_hw_get_num_parents() returns 2. After a look in the devicetree I
found out that this value should be 1, since we only have one parent
clock [3].
Setting the variable
On 10.02.2018 22:08, Sergey Suloev wrote:
On 02/11/2018 12:01 AM, Philipp Rossak wrote:
Hey Sergey,
Thanks for mentioning, but I think the problem has nothing to do with
those patches. I tested them with the v4.15.0 Kernel since this is the
last stable release and we are right now
is
not booting (I can't see any uart output).
Thanks,
Philipp
On 10.02.2018 14:56, Sergey Suloev wrote:
On 02/09/2018 08:52 PM, Philipp Rossak wrote:
This patchseries fixes the bananapi m1 devicetree, to be able to boot
again.
The first two patches update/improve the devicetree and the last patch
This patch updates the vmmc-supply properties on the mmc0 and mmc2
node to use the allready existent regulators.
We can now remove the sunxi-common-regulators.dtsi include since we
don't need it anymore.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
arch/arm/boot/dts/sun6i-a31s-si
This patchseries fixes the bananapi m1 devicetree, to be able to boot again.
The first two patches update/improve the devicetree and the last patch adds
all missing regulators.
Regards,
Philipp
Philipp Rossak (3):
arm: dts: sun6i: a31s: bpi-m2: update mmc supply nodes
arm: dts: sun6i: a31s
The eldoin is supplied from the dcdc1 regulator. The N_VBUSEN pin is
connected to an external power regulator (SY6280AAC).
With this commit we update the pmic binding properties to support
those features.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
arch/arm/boot/dts/sun6i-a31s-si
: 3,3V, powers the audio
* reg_dldo1: 3,0V, powers the RTL8211E
* reg_dldo2: 2,8V, powers the analog part of the csi
* reg_dldo3: 3,3V, powers misc
* reg_eldo1: 1,8V, powers the csi
* reg_ldo_io1:1,8V, powers the gpio
* reg_dc5ldo: needs to be always on
Signed-off-by: Philipp Rossak <e
/* prevents concurrent reads of temperature and ADC */
struct mutexmutex;
struct thermal_zone_device *tzd;
@@ -561,6 +569,9 @@ static int sun4i_gpadc_probe_dt(struct platform_device
*pdev,
struct resource *mem;
void __iomem
On 31.01.2018 20:23, Quentin Schulz wrote:
Hi Philipp,
On Mon, Jan 29, 2018 at 12:29:12AM +0100, Philipp Rossak wrote:
This patch adds support for the H3 ths sensor.
The H3 supports interrupts. The interrupt is configured to update the
the sensor values every second. The calibration data
On 31.01.2018 20:07, Quentin Schulz wrote:
Hi Philipp,
On Mon, Jan 29, 2018 at 12:29:11AM +0100, Philipp Rossak wrote:
This patch rewors the driver to support interrupts for the thermal part
of the sensor.
This is only available for the newer sensor (currently H3 and A83T).
The interrupt
On 31.01.2018 19:42, Quentin Schulz wrote:
Hi Philipp,
On Mon, Jan 29, 2018 at 12:29:09AM +0100, Philipp Rossak wrote:
For adding newer sensor some basic rework of the code is necessary.
This patch reworks the driver to be able to handle more than one
thermal sensor. Newer SoC like the A80
On 31.01.2018 18:51, Quentin Schulz wrote:
Hi Philipp,
On Mon, Jan 29, 2018 at 12:29:07AM +0100, Philipp Rossak wrote:
For adding newer sensor some basic rework of the code is necessary.
This commit reworks the code and allows the sampling start/end code and
the position of value readout
On 31.01.2018 18:40, Quentin Schulz wrote:
Hi Philipp,
On Mon, Jan 29, 2018 at 12:29:04AM +0100, Philipp Rossak wrote:
Allwinner H3 features a thermal sensor like the one in A33, but has its
register re-arranged, the clock divider moved to CCU (originally the
clock divider is in ADC
,
than the default 8 MHz.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
Reviewed-by: Andi Shyti <andi.sh...@samsung.com>
Acked-by: Sean Young <s...@mess.org>
---
drivers/media/rc/sunxi-cir.c | 19 +++
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git
to clock-frequency
Regards,
Philipp
Philipp Rossak (6):
media: rc: update sunxi-ir driver to get base clock frequency from
devicetree
media: dt: bindings: Update binding documentation for sunxi IR
controller
arm: dts: sun8i: a83t: Add the cir pin for the A83T
arm: dts: sun8i: a83t: Add
The CIR Pin of the A83T is located at PL12.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 7f4955a5fab7..f7f78a
The cir interface is like on the H3 located at 0x01f02000 and is exactly
the same. This patch adds support for the ir interface on the A83T.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 13 +
1 file changed, 13 insertions(+)
diff
The Bananapi M3 has an onboard IR receiver.
This enables the onboard IR receiver subnode.
Unlike the other IR receivers this one needs a base clock frequency
of 300 Hz (3 MHz), to be able to work.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
Acked-by: Chen-Yu Tsai <w...
The size of the register should be the size of the whole memory block,
not just the registers, that are needed.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/su
The CIR Pin of the A83T is located at PL12.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi
b/arch/arm/boot/dts/sun8i-a83t.dtsi
index de5119a2a91c..06e96d
The Bananapi M3 has an onboard IR receiver.
This enables the onboard IR receiver subnode.
Unlike the other IR receivers this one needs a base clock frequency
of 300 Hz (3 MHz), to be able to work.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
Acked-by: Chen-Yu Tsai <w...
,
than the default 8 MHz.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
Reviewed-by: Andi Shyti <andi.sh...@samsung.com>
Acked-by: Sean Young <s...@mess.org>
---
drivers/media/rc/sunxi-cir.c | 19 +++
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git
vailable in
the dtb the driver uses the default base clock frequency.
* the driver prints out the the selected base clock frequency.
* changed devicetree property from base-clk-frequency to clock-frequency
Regards,
Philipp
Philipp Rossak (6):
media: rc: update sunxi-ir driver to get ba
The size of the register should be the size of the whole memory block,
not just the registers, that are needed.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/su
This patch updates documentation for Device-Tree bindings for sunxi IR
controller and adds the new optional property for the base clock
frequency.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
Acked-by: Maxime Ripard <maxime.rip...@free-electrons.com>
Reviewed-by: Rob Herring <
The cir interface is like on the H3 located at 0x01f02000 and is exactly
the same. This patch adds support for the ir interface on the A83T.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff
On 29.01.2018 10:40, Maxime Ripard wrote:
On Mon, Jan 29, 2018 at 12:29:10AM +0100, Philipp Rossak wrote:
This patch reworks the driver to support nvmem calibration cells.
The driver checks if the nvmem calibration is supported and reads out
the nvmem.
Signed-off-by: Philipp Rossak <e
+Example for A33:
ths: ths@1c25000 {
compatible = "allwinner,sun8i-a33-ths";
reg = <0x01c25000 0x100>;
@@ -17,6 +40,27 @@ Example:
#io-channel-cells = <0>;
};
+Example for H3:
+ ths: thermal-sensor@1c25000 {
+
On 29.01.2018 10:52, Maxime Ripard wrote:
On Mon, Jan 29, 2018 at 12:29:17AM +0100, Philipp Rossak wrote:
This patch enables the the sid controller in the H3. It can be used
for thermal calibration data.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
arch/arm/boot/dts/sun8i-h
On 29.01.2018 10:50, Maxime Ripard wrote:
On Mon, Jan 29, 2018 at 12:29:16AM +0100, Philipp Rossak wrote:
This patch adds the thermal zones to the H3. We have only one sensor and
that is placed in the cpu.
Signed-off-by: Philipp Rossak <embe...@gmail.com>
---
arch/arm/boot/dts/su
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