[linux-sunxi] Re: [U-Boot] [PATCH 00/12] Big work on sunxi DW DRAM controllers and some new DDR type support

2017-06-02 Thread André Przywara 
On 02/06/17 19:34, Jagan Teki wrote:
> On Wed, Apr 26, 2017 at 8:19 PM, Icenowy Zheng  wrote:
>> This patchset contains several works on the sunxi DesignWare DRAM
>> controllers.
>>
>> The 1st patch made an option for H3-like DRAM controllers
>> (DesignWare ones), which can ease further import of alike controllers.
>>
>> The 2nd and 3rd patches are for supporting 16-bit DW DRAM controllers,
>> in order to add V3s DRAM support (The controller on V3s is 16-bit).
>>
>> The 4th patch adds bank detection code, in order to support some DDR2
>> chips.
>>
>> The 5th patch adds a framework for select DRAM type and timing -- it's
>> needed for boards that use DRAM chips rather than DDR3.
>>
>> The 6th patch enables dual rank detection in the DW DRAM code on SoCs
>> except R40. For R40 the dual rank facility is still not so clear, so it's
>> temporarily disabled.
>>
>> The 7th~9th patches enables support for DRAM initialization and SPL for
>> the V3s SoC, which integrates a DDR2 chip.
>>
>> The 10th and 11th patches adds support for LPDDR3, with the stock boot0
>> timing. (Seen in A83T boot0 source and some leaked H5/R40 libdram source)
>>
>> The 12th patches adds a defconfig for SoPine w/ official baseboard, which
>> utilizes LPDDR3.
>>
>> Icenowy Zheng (12):
>>   sunxi: makes an invisible option for H3-like DRAM controllers
>>   sunxi: Rename bus-width related macros in H3 DRAM code
>>   sunxi: add option for 16-bit DW DRAM controller
>>   sunxi: add bank detection code to H3 DRAM initialization code
>>   sunxi: Add selective DRAM type and timing
>>   sunxi: enable dual rank detection in DesignWare-like DRAM code
>>   sunxi: add support for the DDR2 in V3s SoC
>>   sunxi: add support for V3s DRAM controller
>>   sunxi: enable DRAM initialization and SPL for V3s SoC
>>   sunxi: add LPDDR3 DRAM type support for DesignWare-like DRAM
>> controller
>>   sunxi: add LPDDR3 timing from stock boot0
>>   sunxi: add a defconfig for SoPine w/ official baseboard
> 
> Can you rebase on master and sen it again, difficult to fix the things
> while applying.

... maybe on the way fix the minor things I mentioned in the lower part
of my reply to 11/12?
https://lists.denx.de/pipermail/u-boot/2017-May/290436.html

Cheers,
Andre.

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[linux-sunxi] Re: [U-Boot] [PATCH 00/12] Big work on sunxi DW DRAM controllers and some new DDR type support

2017-06-02 Thread Jagan Teki 
On Wed, Apr 26, 2017 at 8:19 PM, Icenowy Zheng  wrote:
> This patchset contains several works on the sunxi DesignWare DRAM
> controllers.
>
> The 1st patch made an option for H3-like DRAM controllers
> (DesignWare ones), which can ease further import of alike controllers.
>
> The 2nd and 3rd patches are for supporting 16-bit DW DRAM controllers,
> in order to add V3s DRAM support (The controller on V3s is 16-bit).
>
> The 4th patch adds bank detection code, in order to support some DDR2
> chips.
>
> The 5th patch adds a framework for select DRAM type and timing -- it's
> needed for boards that use DRAM chips rather than DDR3.
>
> The 6th patch enables dual rank detection in the DW DRAM code on SoCs
> except R40. For R40 the dual rank facility is still not so clear, so it's
> temporarily disabled.
>
> The 7th~9th patches enables support for DRAM initialization and SPL for
> the V3s SoC, which integrates a DDR2 chip.
>
> The 10th and 11th patches adds support for LPDDR3, with the stock boot0
> timing. (Seen in A83T boot0 source and some leaked H5/R40 libdram source)
>
> The 12th patches adds a defconfig for SoPine w/ official baseboard, which
> utilizes LPDDR3.
>
> Icenowy Zheng (12):
>   sunxi: makes an invisible option for H3-like DRAM controllers
>   sunxi: Rename bus-width related macros in H3 DRAM code
>   sunxi: add option for 16-bit DW DRAM controller
>   sunxi: add bank detection code to H3 DRAM initialization code
>   sunxi: Add selective DRAM type and timing
>   sunxi: enable dual rank detection in DesignWare-like DRAM code
>   sunxi: add support for the DDR2 in V3s SoC
>   sunxi: add support for V3s DRAM controller
>   sunxi: enable DRAM initialization and SPL for V3s SoC
>   sunxi: add LPDDR3 DRAM type support for DesignWare-like DRAM
> controller
>   sunxi: add LPDDR3 timing from stock boot0
>   sunxi: add a defconfig for SoPine w/ official baseboard

Can you rebase on master and sen it again, difficult to fix the things
while applying.

thanks!
-- 
Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.

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