Re: [linux-sunxi] [PATCH 6/8] power: axp209: Add support for voltage rate control on LDO3

Hey Marcus, On 01-03-17 16:10, Marcus Weseloh wrote: Hi Oliver, 2017-03-01 13:52 GMT+01:00 Olliver Schinagl >: +#define AXP209_VRC_LDO3_EN BIT(3) +#define AXP209_VRC_DCDC2_ENBIT(2) +#define

Re: [linux-sunxi] Re: [PATCH 14/17] sunxi: Pine64: defconfig: enable SPL FIT support

2017年3月1日 23:51于 Maxime Ripard 写道： > > Hi Andre, > > On Wed, Mar 01, 2017 at 02:25:26AM +, Andre Przywara wrote: > > The Pine64 (and all other 64-bit Allwinner boards) need to load an > > ARM Trusted Firmware image beside the actual U-Boot proper. > >

Re: [linux-sunxi] [PATCH 6/8] power: axp209: Add support for voltage rate control on LDO3

On Thu, Mar 2, 2017 at 12:02 AM, Olliver Schinagl wrote: > Hey Marcus, > > On 01-03-17 16:10, Marcus Weseloh wrote: >> >> Hi Oliver, >> >> 2017-03-01 13:52 GMT+01:00 Olliver Schinagl > >: >> >> +#define

Re: [linux-sunxi] Re: [PATCH 2/4] clk: sunxi-ng: Add sun7i-a20 CCU driver

2017年3月2日 上午5:38于 Priit Laes 写道： > > On Tue, 2017-02-28 at 09:21 +0100, Maxime Ripard wrote: > > Hi, > > > > On Mon, Feb 27, 2017 at 11:09:12PM +0200, Priit Laes wrote: > > > Introduce a clock controller driver for sun7i A20 SoC. > > > > > > > > Signed-off-by: Priit Laes

[linux-sunxi] Re: [PATCH 0/8] Stop AXP from crashing when enabeling LDO3

Hey Jagan, FYI, I used the wrong e-mail address, I think it is still listed in some of the u-boot sources. Olliver On 01-03-17 15:06, Olliver Schinagl wrote: Hey Maxime, Jagan, On 01-03-17 14:00, Maxime Ripard wrote: Hi Oliver, On Wed, Mar 01, 2017 at 01:52:16PM +0100, Olliver Schinagl

Re: [linux-sunxi] Toggeling LDO3 causes crash/shutdown of the AXP209. Some verification help needed.

Hey Lub, On Tue, 2017-02-28 at 04:19 -0800, Lyubcho Haralanov wrote: > The question that really bugs me is: why toggling LDO4 doesn't affect > the board but toggling LDO3 kills it... I was wondering the same thing, but it could be very well because it has a different circuitry behind it inside

Re: [linux-sunxi] Re: [U-Boot] [PATCH v2] sunxi: add NanoPi NEO Air defconfig

On 03/01/17 at 03:33pm, Chen-Yu Tsai wrote: > On Sat, Feb 25, 2017 at 4:26 PM, Jagan Teki wrote: > > On Mon, Feb 13, 2017 at 1:22 PM, Maxime Ripard > > wrote: > >> On Sun, Feb 12, 2017 at 04:21:40PM +0100, Jelle van der Waa wrote: > >>> Add

Re: [linux-sunxi] Toggeling LDO3 causes crash/shutdown of the AXP209. Some verification help needed.

Hey Marcus, On Tue, 2017-02-28 at 13:58 +0100, Marcus Weseloh wrote: > 2017-02-28 13:19 GMT+01:00 Lyubcho Haralanov : > > The question that really bugs me is: why toggling LDO4 doesn't > > affect the board but toggling LDO3 kills it... > > > > Can you measure the time it

[linux-sunxi] Re: [U-Boot] [PATCH] sunxi: Add boards/sunxi and arch/arm/mach-sunxi to sunxi MAINTAINERS entry

On Wed, Mar 1, 2017 at 11:33 AM, Chen-Yu Tsai wrote: > Recently some sunxi related code was moved to arch/arm/mach-sunxi, but > the MAINTAINERS entry was not updated to reflect this. Add this, and > the board level boards/sunxi directory to our entry. > > While at it, also update

Re: [linux-sunxi] [PATCH 00/12] sunxi: Add support for R40 SoC

2017年3月1日 15:04于 Chen-Yu Tsai 写道： > > Hi everyone, > > This series adds support for the new R40 SoC. The R40 is marketed as the > successor to the A20. It is mostly pin compatible (in software) with the > A20. It has a somewhat similar memory layout, a hybrid of A20 and newer >

[linux-sunxi] Re: [U-Boot] [PATCH] sunxi: makes an invisible option for H3-like DRAM controllers

On Tue, Feb 14, 2017 at 7:19 PM, Icenowy Zheng wrote: > Allwinner SoCs after H3 (e.g. A64, H5, R40, V3s) uses a H3-like > DesignWare DRAM controller, which do not have official free DRAM > initialization code, but can use modified dram_sun8i_h3.c. > > Add a invisible option for

[linux-sunxi] Re: [U-Boot] [PATCH v2 1/6] sunxi: add invisible options for PRCM and RSB support

On Sun, Feb 26, 2017 at 5:22 AM, Icenowy Zheng wrote: > The Makefile of mach-sunxi used to build PRCM and RSB according to the > SoC's MACH_SUNxI macro, which makes it needed to add lines for new SoC > generation. > > Change this behavior to invisible options in sunxi Kconfig,

[linux-sunxi] Re: [U-Boot] [PATCH v2 3/6] sunxi: add AXP_PMIC_BUS invisible options for AXP PMICs access

On Sun, Feb 26, 2017 at 5:22 AM, Icenowy Zheng wrote: > For AXP PMICs' drivers some functions are needed to provide I/O access > for the PMIC. > > The source file used to be controlled by different AXPxxx_POWER config > option. > > Control the file's compliation via a generic

[linux-sunxi] Re: [PATCH 01/12] sunxi: Add initial support for R40

Hi Chen-Yu On Wed, Mar 01, 2017 at 03:04:36PM +0800, Chen-Yu Tsai wrote: > The R40 is the successor to the A20. It is a hybrid of the A20, A33 > and the H3. > > The R40's PIO controller is compatible with the A20, > Reuse the A20 UART and I2C muxing code by adding the R40's macro. > > The

[linux-sunxi] Re: [PATCH 03/12] sunxi: Fix watchdog reset function for R40

On Wed, Mar 01, 2017 at 03:04:38PM +0800, Chen-Yu Tsai wrote: > The watchdog found on the R40 SoC is the older variant found on the A20. > Add the proper "#if defines" to make it work. > > Signed-off-by: Chen-Yu Tsai Acked-by: Maxime Ripard

[linux-sunxi] Re: [PATCH 04/12] sunxi: Add mmc[1-3] pinmux settings for R40

On Wed, Mar 01, 2017 at 03:04:39PM +0800, Chen-Yu Tsai wrote: > The PIO is generally compatible with the A20, except that it routes the > full 8 bits and eMMC reset pins for mmc2. > > Signed-off-by: Chen-Yu Tsai Acked-by: Maxime Ripard Thanks!

[linux-sunxi] Re: [PATCH 02/12] sunxi: Enable AXP221s in I2C mode with the R40 SoC

On Wed, Mar 01, 2017 at 03:04:37PM +0800, Chen-Yu Tsai wrote: > The R40 SoC uses the AXP221s in I2C mode to supply power. > > Some regulator's common usages have changed, and also the recommended > voltage for existing usages have changed. Update the defaults to match. > > Signed-off-by: Chen-Yu

[linux-sunxi] Re: [PATCH 01/12] sunxi: Add initial support for R40

On Wed, Mar 1, 2017 at 6:55 PM, Maxime Ripard wrote: > Hi Chen-Yu > > On Wed, Mar 01, 2017 at 03:04:36PM +0800, Chen-Yu Tsai wrote: >> The R40 is the successor to the A20. It is a hybrid of the A20, A33 >> and the H3. >> >> The R40's PIO controller is compatible

Re: [linux-sunxi] Re: [PATCH 2/3] clk: sunxi-ng: add support for PRCM CCUs

2017年3月1日 18:47于 Maxime Ripard 写道： > > On Wed, Mar 01, 2017 at 12:15:40PM +0800, Icenowy Zheng wrote: > > SoCs after A31 has a clock controller module in the PRCM part. > > > > Support the clock controller module on H5 and A64 now. > > > > Signed-off-by:

[linux-sunxi] Re: [PATCH 2/3] clk: sunxi-ng: add support for PRCM CCUs

2017年3月1日 18:47于 Maxime Ripard 写道： > > On Wed, Mar 01, 2017 at 12:15:40PM +0800, Icenowy Zheng wrote: > > SoCs after A31 has a clock controller module in the PRCM part. > > > > Support the clock controller module on H5 and A64 now. > > > > Signed-off-by:

[linux-sunxi] [PATCH 7/8] power: axp209: Limit inrush current for broken boards

Some boards feature a capacitance on LDO3's output that is to large, causing inrush currents which as a result, shut down the AXP209. This has been reported before, without knowing the actual cause. A fix appeared to be done with commit 0e6e34ac8db ("sunxi: Olimex A20 boards: Enable LDO3 and LDO4

[linux-sunxi] [PATCH 0/8] Stop AXP from crashing when enabeling LDO3

Hi list, When powering up an AXP209, the default value for LDO3 output is enabled. This works fine. However if for whatever reason, LDO3 is disabled, for example by OS during reboot and u-boot enables LDO3 again, the PMIC shutsdown (without setting an interrupt) causing the board to hang. This

[linux-sunxi] [PATCH 8/8] arm: sunxi: Enable inrush quirk on Olimex OLinuXino-A20-Lime2

The lime2 features a too large capacitor on the LDO3 output, which causes the PMIC to shutdown when enabling power. To be able to still boot up however, we must gradually enable power on LDO3 for this board. Signed-off-by: Olliver Schinagl ---

[linux-sunxi] [PATCH 6/8] power: axp209: Add support for voltage rate control on LDO3

The AXP209 has voltage rate control, or can set a slew rate, for LDO3. This allows for the power to gradually rise to the desired voltage, instead of spiking up quickly. Reason to have this can be to reduce the inrush currents for example. There are 3 slopes to choose from, the default, 'none' is

[linux-sunxi] [PATCH 2/8] sunxi: pmic_bus: Decrease boot time by not writing duplicate data

When we set or clear a pmic_bus bit, we do a read-modify-write operation. We waste some time however, by writing back the exact same value that was already set in the chip. Let us thus only configure the chip if the data is different. Signed-off-by: Olliver Schinagl ---

[linux-sunxi] [PATCH 5/8] power: axp209: Reduce magic values by adding defines for LDO[234]

The AXP209 has a few 'magisc-ish' values that are better served with clear defines. Signed-off-by: Olliver Schinagl --- drivers/power/axp209.c | 10 -- include/axp209.h | 14 ++ 2 files changed, 18 insertions(+), 6 deletions(-) diff --git

[linux-sunxi] [PATCH 3/8] power: axp209: Use BIT() macro

Use the standard BIT() macro to define BITS. Signed-off-by: Olliver Schinagl --- include/axp209.h | 34 ++ 1 file changed, 18 insertions(+), 16 deletions(-) diff --git a/include/axp209.h b/include/axp209.h index e1b22e3442..7803300328 100644

[linux-sunxi] [PATCH 1/8] sunxi: board: Print error after power initialization fails

Currently during init, we enable all power, then enable the dram and after that check if there was an error during power-up. This makes little sense, we should enable power and then check if power was brought up properly initializing other things. This patch moves the DRAM init after the power

[linux-sunxi] [PATCH 4/8] power: axp209: Define the chip version mask

Use a define for the chip version mask on the axp209. Signed-off-by: Olliver Schinagl --- drivers/power/axp209.c | 5 + include/axp209.h | 2 ++ 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/power/axp209.c b/drivers/power/axp209.c index

[linux-sunxi] Re: [PATCH 0/8] Stop AXP from crashing when enabeling LDO3

Hi Oliver, On Wed, Mar 01, 2017 at 01:52:16PM +0100, Olliver Schinagl wrote: > Hi list, > > When powering up an AXP209, the default value for LDO3 output is enabled. This > works fine. However if for whatever reason, LDO3 is disabled, for example by > OS > during reboot and u-boot enables LDO3

Re: [linux-sunxi] [PATCH 1/8] sunxi: board: Print error after power initialization fails

01.03.2017, 20:52, "Olliver Schinagl" : > Currently during init, we enable all power, then enable the dram and > after that check if there was an error during power-up. > > This makes little sense, we should enable power and then check if power > was brought up properly

[linux-sunxi] Re: [PATCH 0/8] Stop AXP from crashing when enabeling LDO3

Hey Maxime, On 01-03-17 14:00, Maxime Ripard wrote: Hi Oliver, On Wed, Mar 01, 2017 at 01:52:16PM +0100, Olliver Schinagl wrote: Hi list, When powering up an AXP209, the default value for LDO3 output is enabled. This works fine. However if for whatever reason, LDO3 is disabled, for example

Re: [linux-sunxi] Re: [PATCH 0/8] Stop AXP from crashing when enabeling LDO3

01.03.2017, 21:45, "Olliver Schinagl" : > Hey Maxime, > > On 01-03-17 14:00, Maxime Ripard wrote: >>  Hi Oliver, >> >>  On Wed, Mar 01, 2017 at 01:52:16PM +0100, Olliver Schinagl wrote: >>>  Hi list, >>> >>>  When powering up an AXP209, the default value for LDO3 output

[linux-sunxi] How to handle quirky behavior with boards.

Hey all, We found a bug in the design of a board that we use. This board (Olimex OLinuXino Lime2) features a PMIC (AXP209) and has an LDO, LDO3, that needs special treatment. The bug is, that there is too much capacitance on the output of LDO3, which causes the PMIC to shutdown when

[linux-sunxi] Re: [PATCH 0/8] Stop AXP from crashing when enabeling LDO3

Hey Maxime, Jagan, On 01-03-17 14:00, Maxime Ripard wrote: Hi Oliver, On Wed, Mar 01, 2017 at 01:52:16PM +0100, Olliver Schinagl wrote: Hi list, When powering up an AXP209, the default value for LDO3 output is enabled. This works fine. However if for whatever reason, LDO3 is disabled, for

[linux-sunxi] Re: [PATCH 09/12] sunxi: Enable SPL for R40

On Wed, Mar 01, 2017 at 03:04:44PM +0800, Chen-Yu Tsai wrote: > Now that we can do DRAM initialization for the R40, we can enable > SPL support for it. > > Signed-off-by: Chen-Yu Tsai Acked-by: Maxime Ripard Maxime -- Maxime Ripard, Free

[linux-sunxi] Re: [PATCH 08/12] sunxi: Use H3/A64 DRAM initialization code for R40

On Wed, Mar 01, 2017 at 03:04:43PM +0800, Chen-Yu Tsai wrote: > The R40 seems to have a variant of the memory controller found in > the H3 and A64 SoCs. Adapt the code for use on the R40. The changes > are based on released DRAM code and comparing register dumps from > boot0. > > Signed-off-by:

[linux-sunxi] Re: [PATCH 10/12] sunxi: Fix CPUCFG address for R40

On Wed, Mar 01, 2017 at 03:04:45PM +0800, Chen-Yu Tsai wrote: > The R40 has the CPUCFG block at the same address as the A20. > Fix it. > > Signed-off-by: Chen-Yu Tsai Acked-by: Maxime Ripard Maxime -- Maxime Ripard, Free Electrons Embedded

[linux-sunxi] Re: [PATCH 11/12] sunxi: Add PSCI support for R40

On Wed, Mar 01, 2017 at 03:04:46PM +0800, Chen-Yu Tsai wrote: > The R40's CPU controls are a combination of sun6i and sun7i. > > All controls are in the CPUCFG block, and it seems the R40 does not > have a PRCM block. The core reset, power gating and clamp controls > are grouped like sun6i. > >

[linux-sunxi] Re: [PATCH 12/12] sunxi: Add support for Bananapi M2 Ultra

On Wed, Mar 01, 2017 at 03:04:47PM +0800, Chen-Yu Tsai wrote: > The Bananapi M2 Ultra is the first publicly available development board > featuring the R40 SoC. > > This patch add barebone dtsi/dts files for the R40 and Bananapi M2 Ultra, > as well as a defconfig for it. > > Signed-off-by:

[linux-sunxi] Re: [PATCH 01/12] sunxi: Add initial support for R40

1;4601;0c On Wed, Mar 01, 2017 at 08:10:55PM +0800, Chen-Yu Tsai wrote: > On Wed, Mar 1, 2017 at 6:55 PM, Maxime Ripard > wrote: > > Hi Chen-Yu > > > > On Wed, Mar 01, 2017 at 03:04:36PM +0800, Chen-Yu Tsai wrote: > >> The R40 is the successor to the A20. It is a

[linux-sunxi] Re: [PATCH 05/12] sunxi: Set PLL lock enable bits for R40

On Wed, Mar 01, 2017 at 03:04:40PM +0800, Chen-Yu Tsai wrote: > According to the BSP released by Banana Pi, the R40 (sun8iw11p1) has > an extra "PLL lock control" register in the CCU, which controls whether > the individual PLL lock status bits in each PLL's control register work > or not. > >

[linux-sunxi] Re: [PATCH 06/12] sunxi: Provide defaults for R40 DRAM settings

On Wed, Mar 01, 2017 at 03:04:41PM +0800, Chen-Yu Tsai wrote: > These values were taken from the Banana Pi M2 Ultra fex file > found in the released vendor BSP. This is the only publicly > available R40 device at the time of this writing. > > Signed-off-by: Chen-Yu Tsai Acked-by:

[linux-sunxi] Re: [PATCH 07/12] gpio: sunxi: Add compatible string for R40 PIO

On Wed, Mar 01, 2017 at 03:04:42PM +0800, Chen-Yu Tsai wrote: > The PIO on the R40 SoC is mostly compatible with the A20. > Only a few pin functions for mmc2 were added to the PC > pingroup, to support 8 bit eMMCs. > > Signed-off-by: Chen-Yu Tsai Acked-by: Maxime Ripard

Re: [linux-sunxi] [PATCH 6/8] power: axp209: Add support for voltage rate control on LDO3

Hi Oliver, 2017-03-01 13:52 GMT+01:00 Olliver Schinagl : > +#define AXP209_VRC_LDO3_EN BIT(3) > +#define AXP209_VRC_DCDC2_ENBIT(2) > +#define AXP209_VRC_LDO3_800uV_uS (BIT(1) | AXP209_VRC_LDO3_EN) > +#define AXP209_VRC_LDO3_1600uV_uS

Re: [linux-sunxi] Re: [PATCH 01/12] sunxi: Add initial support for R40

01.03.2017, 22:57, "Maxime Ripard" : > 1;4601;0c > On Wed, Mar 01, 2017 at 08:10:55PM +0800, Chen-Yu Tsai wrote: >>  On Wed, Mar 1, 2017 at 6:55 PM, Maxime Ripard >>   wrote: >>  > Hi Chen-Yu >>  > >>  > On Wed, Mar 01, 2017 at

[linux-sunxi] Re: [PATCH 14/17] sunxi: Pine64: defconfig: enable SPL FIT support

Hi Andre, On Wed, Mar 01, 2017 at 02:25:26AM +, Andre Przywara wrote: > The Pine64 (and all other 64-bit Allwinner boards) need to load an > ARM Trusted Firmware image beside the actual U-Boot proper. > This can now be easily achieved by using the just extended SPL FIT > loading support, so

Re: [linux-sunxi] [PATCH 05/12] sunxi: Set PLL lock enable bits for R40

Hi! Dne sreda, 01. marec 2017 ob 08:04:40 CET je Chen-Yu Tsai napisal(a): > According to the BSP released by Banana Pi, the R40 (sun8iw11p1) has > an extra "PLL lock control" register in the CCU, which controls whether > the individual PLL lock status bits in each PLL's control register work > or

Re: [linux-sunxi] [PATCH 3/4] ARM: sun7i: Convert to CCU

On Tue, 2017-02-28 at 14:01 -0300, Emilio López wrote: > Hi, > > I spotted a couple of things here on a quick look, see below > > El 27/02/17 a las 18:09, Priit Laes escribió: > > Convert sun7i-a20.dtsi to new CCU driver. > > > > > > Signed-off-by: Priit Laes > > --- > >  

[linux-sunxi] [PATCH] arm: dts: sun8i: split Allwinner H3 .dtsi

From: Andre Przywara The new Allwinner H5 SoC is pin-compatible to the H3 SoC, but with the Cortex-A7 cores replaced by Cortex-A53 cores and the MMC controller updated. So we should really share almost the whole .dtsi. In preparation for that move the peripheral parts of

[linux-sunxi] [PATCH v6 0/4] Allwinner H5 and Orange Pi PC2 support

Allwinner H5 is a 64-bit SoC with a design like the 32-bit H3, and it's pin-to-pin compatible with H3. This patchset adds support for it, along with the first available board -- Orange Pi PC2. Several H5 boards by Sinovoip Banana Pi and FriendlyARM Nano Pi are coming, so we should get ready for

[linux-sunxi] [PATCH v6 3/4] arm64: dts: allwinner: add Allwinner H5 .dtsi

From: Andre Przywara The Allwinner H5 SoC is pin-compatible to the H3 SoC, but uses Cortex-A53 cores instead. Based on the now shared base .dtsi describing the common peripherals describe the H5 specific nodes on top of that. That symlinks in the sunxi-h3-h5.dtsi from the

[linux-sunxi] [PATCH v6 4/4] arm64: dts: sunxi: add support for the Orange Pi PC 2 board

From: Andre Przywara The Orange Pi PC 2 is a typical single board computer using the Allwinner H5 SoC. Apart from the usual suspects it features three separately driven USB ports and a Gigabit Ethernet port. Also it has a SPI NOR flash soldered, from which the board can

Re: [linux-sunxi] Re: [PATCH 2/4] clk: sunxi-ng: Add sun7i-a20 CCU driver

On Tue, 2017-02-28 at 09:21 +0100, Maxime Ripard wrote: > Hi, > > On Mon, Feb 27, 2017 at 11:09:12PM +0200, Priit Laes wrote: > > Introduce a clock controller driver for sun7i A20 SoC. > > > > > > Signed-off-by: Priit Laes > > --- > >  drivers/clk/sunxi-ng/Kconfig |