在 2017-09-11 23:55,Icenowy Zheng 写道:
The DE2 in H3/H5 has a clock control unit in it, and the behavior is
slightly different between H3 and H5.
Add the common parts in H3/H5 DTSI, and add the compatible string in H3
DTSI.
The compatible string of H5 DE2 CCU will be added in a separated patch.
On Fri, Oct 27, 2017 at 2:02 AM, André Przywara wrote:
> On 26/10/17 19:13, Jagan Teki wrote:
>> On Thu, Oct 26, 2017 at 4:50 PM, Jagan Teki
>> wrote:
>>> On Sun, Oct 22, 2017 at 5:59 PM, Thomas Petazzoni
>>>
This patchset adds support for the SimpleFB on Allwinner SoCs with
"Display Engine 2.0".
PATCH 1 to PATCH 3 are DE2 CCU fixes for H3/H5 SoCs.
PATCH 4 adds the pipeline strings for DE2 SimpleFB.
PATCH 5 to 7 adds necessary device tree nodes (DE2 CCU and SimpleFB)
for H3/H5 SoCs.
PATCH 8 to 10
在 2017-10-16 20:09,Maxime Ripard 写道:
On Mon, Oct 16, 2017 at 05:41:10PM +0800, icen...@aosc.io wrote:
在 2017-10-16 17:11,Maxime Ripard 写道:
> On Sat, Oct 14, 2017 at 08:29:24PM +0800, Icenowy Zheng wrote:
> > A64's Display Engine 2.0 needs a section of SRAM (SRAM C) to be
> > claimed.
>
> Why?
The A64 SoC features two display pipelines, one has a LCD output, the
other has a HDMI output.
Add support for simplefb for these pipelines on A64 SoC.
Signed-off-by: Icenowy Zheng
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 31 +++
1 file
The A64 SoC features a DE2 CCU like the one in H5, but needs to claim a
section of SRAM (SRAM C) to be accessed.
Adds the device tree nodes for the SRAM controller and the DE2 CCU.
Signed-off-by: Icenowy Zheng
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 34
The DE2 CCU is different on A83T and H3 -- the parent of the clocks on
A83T is PLL_DE but on H3 it's the DE module clock. This is not noticed
when I develop the DE2 CCU driver.
Fix the binding by using different compatibles for A83T and H3, adding
notes for the PLL_DE usage on A83T, and change
Allwinner H3 features a DE2 CCU like the one on A83T, however the
parent of the clocks is the DE module clock, not the PLL_DE clock.
Add support for it.
Signed-off-by: Icenowy Zheng
---
drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 47
1 file
The clocks of A64/H5 SoCs in the DE2 CCU is the same as the clocks in H3
DE2 CCU rather than the A83T DE2 CCU (the parent of them is the DE
module clock).
Fix this by change the clock descriptions to use the clocks of H3.
Fixes: 763c5bd045b1 ("clk: sunxi-ng: add support for DE2 CCU")
On Fri, Oct 27, 2017 at 10:33:29PM +0800, icen...@aosc.io wrote:
> 在 2017-10-16 20:09,Maxime Ripard 写道:
> > On Mon, Oct 16, 2017 at 05:41:10PM +0800, icen...@aosc.io wrote:
> > > 在 2017-10-16 17:11,Maxime Ripard 写道:
> > > > On Sat, Oct 14, 2017 at 08:29:24PM +0800, Icenowy Zheng wrote:
> > > > >
The DE2 in H3/H5 has a clock control unit in it, and the behavior is
slightly different between H3 and H5.
Add the common parts in H3/H5 DTSI, and add the compatible string in H3
DTSI.
The compatible string of H5 DE2 CCU will be added in a separated patch.
Signed-off-by: Icenowy Zheng
The DE2 CCU on Allwinner H5 SoC has a slightly different behavior than
the one on H3, so the compatible string is not set in the common DTSI
file.
Add the compatible string of H5 DE2 CCU in H5 DTSI file.
Signed-off-by: Icenowy Zheng
---
A64's Display Engine 2.0 needs a section of SRAM (SRAM C) to be claimed,
otherwise the whole DE2 memory zone cannot be accessed (kept to all 0).
Add binding for this, in order to make the DE2 CCU able to claim the
SRAM and enable access to the DE2 clock and reset registers.
Signed-off-by:
The H3/H5 SoCs have a HDMI output and a TV Composite output.
Add simplefb nodes for these outputs.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 29 +
1 file changed, 29 insertions(+)
diff --git
Hi,
On Thu, Oct 26, 2017 at 02:57:00PM +, Joonas Kylmälä wrote:
> Maxime Ripard:
> > On Sun, Oct 22, 2017 at 12:19:56PM +0300, Joonas Kylmälä wrote:
> >> Most of the boards use the mmc0 pins and their attributes defined in
> >> mmc0_pins_a and mmc0_cd_pin. Let's default to those by moving the
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