于 2018年11月20日 GMT+08:00 下午4:42:45, Maxime Ripard 写到:
>On Sun, Nov 18, 2018 at 05:17:02PM +0300, Mesih Kilinc wrote:
>> Add option for Allwinner ARMv5 SoCs and SoC F1C100s (which has a die
>> used for many new F-series products, including F1C100A, F1C100s,
>F1C200s,
>> F1C500, F1C600).
>>
>>
On Sun, Nov 18, 2018 at 05:17:02PM +0300, Mesih Kilinc wrote:
> Add option for Allwinner ARMv5 SoCs and SoC F1C100s (which has a die
> used for many new F-series products, including F1C100A, F1C100s, F1C200s,
> F1C500, F1C600).
>
> Signed-off-by: Icenowy Zheng
> Signed-off-by: Mesih Kilinc
>
On Sun, Nov 18, 2018 at 05:17:12PM +0300, Mesih Kilinc wrote:
> F1C100s is one product with the suniv die, which has a 32MiB co-packaged
> DDR1 DRAM chip. As we have the support for suniv pin controller and CCU now,
> add a
> initial DTSI for it.
>
> Signed-off-by: Icenowy Zheng
>
Hi,
On Sun, Nov 18, 2018 at 05:16:59PM +0300, Mesih Kilinc wrote:
> This is the second version of RFC patchset for Allwinner ARMv5 F1C100s
> SoC. Icenowy (author of the initial patchset) allowed me to continue.
> For patch 1~3 which introduces first ARMv5 Allwinner SoC I looked
> freescale,imx
Hi,
On Sun, Nov 18, 2018 at 05:17:04PM +0300, Mesih Kilinc wrote:
> The new F-series SoCs (suniv) from Allwinner use an stripped version of
> the interrupt controller in A10/A13.
>
> Add support for it in irq-sun4i driver.
>
> Signed-off-by: Icenowy Zheng
> Signed-off-by: Mesih Kilinc
> ---
>
On Sun, Nov 18, 2018 at 05:17:07PM +0300, Mesih Kilinc wrote:
> The suniv chip (newer F-series Allwinner SoCs) is based on ARM926EJ-S
> CPU, thus it has no architecture timer.
>
> Register sun4i_timer as sched_clock on it.
>
> Signed-off-by: Icenowy Zheng
> Signed-off-by: Mesih Kilinc
This
Hi,
On Sun, Nov 18, 2018 at 05:17:00PM +0300, Mesih Kilinc wrote:
> Allwinner also has some ARMv5 SoCs.
>
> In order to add support for them, add a CONFIG_ARCH_SUNXI_V7 bool config
> which is selected when a ARMv7 soc is selected, and make CONFIG_ARCH_SUNXI
> a common option which is selected by
Hi,
On Sun, Nov 18, 2018 at 05:17:03PM +0300, Mesih Kilinc wrote:
> Add compatible string for Alwinner suniv F1C100s SoC interrupt
> controller which is stripped version of sun4i
>
> Signed-off-by: Mesih Kilinc
> ---
> .../devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt | 5
>
On Sun, Nov 18, 2018 at 05:17:10PM +0300, Mesih Kilinc wrote:
> Add compatiple string for Allwinner suniv F1C100s CCU.
> Add clock and reset definitions.
>
> Signed-off-by: Mesih Kilinc
> ---
> .../devicetree/bindings/clock/sunxi-ccu.txt| 1 +
>
On Tue, Nov 20, 2018 at 6:53 PM Maxime Ripard wrote:
>
> On Mon, Nov 19, 2018 at 04:28:29PM +0530, Jagan Teki wrote:
> > On Mon, Nov 19, 2018 at 1:57 PM Maxime Ripard
> > wrote:
> > >
> > > On Fri, Nov 16, 2018 at 10:09:05PM +0530, Jagan Teki wrote:
> > > > Loop N1 instruction delay for burst
On Tue, Nov 20, 2018 at 4:26 PM Maxime Ripard wrote:
>
> On Thu, Nov 15, 2018 at 08:51:04PM +0530, Jagan Teki wrote:
> > > > drivers/clk/sunxi-ng/ccu_nkm.c | 3 +++
> > > > drivers/clk/sunxi-ng/ccu_nkm.h | 1 +
> > > > 2 files changed, 4 insertions(+)
> > > >
> > > > diff --git
On Thu, Nov 15, 2018 at 08:51:04PM +0530, Jagan Teki wrote:
> > > drivers/clk/sunxi-ng/ccu_nkm.c | 3 +++
> > > drivers/clk/sunxi-ng/ccu_nkm.h | 1 +
> > > 2 files changed, 4 insertions(+)
> > >
> > > diff --git a/drivers/clk/sunxi-ng/ccu_nkm.c
> > > b/drivers/clk/sunxi-ng/ccu_nkm.c
> > > index
On Mon, Nov 19, 2018 at 04:52:17PM +0530, Jagan Teki wrote:
> On Mon, Nov 19, 2018 at 2:02 PM Maxime Ripard
> wrote:
> >
> > On Fri, Nov 16, 2018 at 10:09:08PM +0530, Jagan Teki wrote:
> > > Allwinner MIPI DSI DRQ set value can be varied with respective
> > > video modes.
> > > - burst mode the
On Tue, Nov 20, 2018 at 8:02 PM Maxime Ripard wrote:
>
> On Mon, Nov 19, 2018 at 04:52:17PM +0530, Jagan Teki wrote:
> > On Mon, Nov 19, 2018 at 2:02 PM Maxime Ripard
> > wrote:
> > >
> > > On Fri, Nov 16, 2018 at 10:09:08PM +0530, Jagan Teki wrote:
> > > > Allwinner MIPI DSI DRQ set value can
On Tue, Nov 20, 2018 at 9:29 PM Maxime Ripard wrote:
>
> On Tue, Nov 20, 2018 at 07:06:30PM +0530, Jagan Teki wrote:
> > On Tue, Nov 20, 2018 at 6:53 PM Maxime Ripard
> > wrote:
> > >
> > > On Mon, Nov 19, 2018 at 04:28:29PM +0530, Jagan Teki wrote:
> > > > On Mon, Nov 19, 2018 at 1:57 PM
On Tue, Nov 20, 2018 at 9:15 PM Maxime Ripard wrote:
>
> On Mon, Nov 19, 2018 at 04:30:37PM +0530, Jagan Teki wrote:
> > On Mon, Nov 19, 2018 at 2:00 PM Maxime Ripard
> > wrote:
> > >
> > > On Fri, Nov 16, 2018 at 10:09:07PM +0530, Jagan Teki wrote:
> > > > Burst mode display timings are
On Tue, Nov 20, 2018 at 9:27 PM Maxime Ripard wrote:
>
> On Thu, Nov 15, 2018 at 11:19:53PM +0530, Jagan Teki wrote:
> > On Thu, Nov 15, 2018 at 3:26 PM Maxime Ripard
> > wrote:
> > >
> > > Hi,
> > >
> > > On Tue, Nov 13, 2018 at 04:46:15PM +0530, Jagan Teki wrote:
> > > > The horizontal and
On Mon, Nov 19, 2018 at 04:30:37PM +0530, Jagan Teki wrote:
> On Mon, Nov 19, 2018 at 2:00 PM Maxime Ripard
> wrote:
> >
> > On Fri, Nov 16, 2018 at 10:09:07PM +0530, Jagan Teki wrote:
> > > Burst mode display timings are different from convectional
> > > video mode so update the horizontal and
On Thu, Nov 15, 2018 at 11:19:53PM +0530, Jagan Teki wrote:
> On Thu, Nov 15, 2018 at 3:26 PM Maxime Ripard
> wrote:
> >
> > Hi,
> >
> > On Tue, Nov 13, 2018 at 04:46:15PM +0530, Jagan Teki wrote:
> > > The horizontal and vertical back porch calculation in BSP
> > > code is simply following the
On Mon, Nov 19, 2018 at 05:06:32PM +0530, Jagan Teki wrote:
> On Mon, Nov 19, 2018 at 2:08 PM Maxime Ripard
> wrote:
> >
> > On Fri, Nov 16, 2018 at 10:09:10PM +0530, Jagan Teki wrote:
> > > Probe tcon0 during dsi_bind, so-that the tcon attributes like
> > > divider value, clock rate can get
On Tue, Nov 20, 2018 at 07:06:30PM +0530, Jagan Teki wrote:
> On Tue, Nov 20, 2018 at 6:53 PM Maxime Ripard
> wrote:
> >
> > On Mon, Nov 19, 2018 at 04:28:29PM +0530, Jagan Teki wrote:
> > > On Mon, Nov 19, 2018 at 1:57 PM Maxime Ripard
> > > wrote:
> > > >
> > > > On Fri, Nov 16, 2018 at
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