On Mon, Dec 10, 2018 at 09:47:19PM +0530, Jagan Teki wrote:
> Video start delay can be computed by subtracting total vertical
> timing with front porch timing and with adding 1 delay line for TCON.
>
> BSP code form BPI-M64-bsp is computing video start delay as
> (from linux-sunxi/
>
On Tue, Dec 11, 2018 at 10:19 PM Maxime Ripard
wrote:
>
> On Mon, Dec 10, 2018 at 09:47:19PM +0530, Jagan Teki wrote:
> > Video start delay can be computed by subtracting total vertical
> > timing with front porch timing and with adding 1 delay line for TCON.
> >
> > BSP code form BPI-M64-bsp is
On Mon, Dec 3, 2018 at 6:25 AM Heiko Stuebner wrote:
>
> Am Dienstag, 27. November 2018, 08:42:49 CET schrieb Icenowy Zheng:
> > Allwinner H6 SoC uses a Mali T720 GPU, which is one of the GPUs in the
> > Midgard GPU product line.
> >
> > Add binding for the H6 Mali Midgard GPU.
> >
> >
ST7701 designed for small and medium sizes of TFT LCD display, is
capable of supporting up to 480RGBX864 in resolution. It provides
several system interfaces like MIPI/RGB/SPI.
Currently added support for Techstar TS8550B which is ST7701 based
480x854, 2-lane MIPI DSI LCD panel.
Driver now
Techstar TS8550B MIPI DSI panel is 480x854, 2-lane MIPI DSI LCD panel
with inbuilt ST7701 chip.
The default regulator names in ST7701 chip is renamed in Techstar TS8550B
so, add specific binding names for them.
Signed-off-by: Jagan Teki
---
Changes for v5:
- found the chip from vendor, so added
On Mon, Dec 10, 2018 at 05:22:42PM +0530, Jagan Teki wrote:
> Allwinner A64 CSI has single channel time-multiplexed BT.656
> CMOS sensor interface like H3 but work by lowering clock than
> default mod clock.
>
> So use separate compatibe to support it.
>
> Signed-off-by: Jagan Teki
> ---
>
On Tue, Dec 11, 2018 at 9:14 PM Maxime Ripard wrote:
>
> On Mon, Dec 10, 2018 at 05:22:43PM +0530, Jagan Teki wrote:
> > The default CSI_SCLK seems unable to drive the sensor to capture
> > the image, so update it to working clock rate 300MHz for A64.
> >
> > Signed-off-by: Jagan Teki
> > ---
>
On Mon, Dec 10, 2018 at 09:47:27PM +0530, Jagan Teki wrote:
> Minimum PLL used for MIPI is 500MHz, as per manual, but
> lowering the min rate by 300MHz can result proper working
> nkms divider with the help of desired dclock rate from
> panel driver.
>
> Signed-off-by: Jagan Teki
> Acked-by:
On 11/12/18 10:20 PM, Maxime Ripard wrote:
On Tue, Dec 11, 2018 at 10:05:43PM +0530, Jagan Teki wrote:
On 11/12/18 10:02 PM, Maxime Ripard wrote:
On Mon, Dec 10, 2018 at 09:47:27PM +0530, Jagan Teki wrote:
Minimum PLL used for MIPI is 500MHz, as per manual, but
lowering the min rate by
On Mon, Dec 10, 2018 at 05:22:43PM +0530, Jagan Teki wrote:
> The default CSI_SCLK seems unable to drive the sensor to capture
> the image, so update it to working clock rate 300MHz for A64.
>
> Signed-off-by: Jagan Teki
> ---
> drivers/media/platform/sunxi/sun6i-csi/sun6i_csi.c | 5 +
> 1
On Tue, Dec 11, 2018 at 10:05:43PM +0530, Jagan Teki wrote:
>
>
> On 11/12/18 10:02 PM, Maxime Ripard wrote:
> > On Mon, Dec 10, 2018 at 09:47:27PM +0530, Jagan Teki wrote:
> > > Minimum PLL used for MIPI is 500MHz, as per manual, but
> > > lowering the min rate by 300MHz can result proper
From: Olliver Schinagl
The current axp20x names the ramping register 'scal' which probably
means scaling. Since the register really has nothing to do with
scaling, but really is the voltage ramp we rename it appropriately.
Signed-off-by: Olliver Schinagl
Signed-off-by: Priit Laes
From: Olliver Schinagl
The AXP209 supports ramping up voltages on several regulators such as
DCDC2 and LDO3.
This patch adds preliminary support for the regulator-ramp-delay property
for these 2 regulators. Note that the voltage ramp only works when
regulator is already enabled. E.g. when going
From: Olliver Schinagl
In the past, there have been words on various lists that if LDO3 is
disabled in u-boot, but enabled in the DTS, the axp209 driver would
fail to continue/hang. Several enable/disable patches have been
issues to devicetree's in both the kernel and u-boot to address
this
From: Olliver Schinagl
The OLinuXino Lime2 has a big capacitor on its LDO3 output. It is
actually too large, causing the PMIC to shutdown when toggling the LDO3.
By enabling soft-start and ramp delay we increase the time for the
capacitor to charge lowering the current drain on the power
From: Olliver Schinagl
Add the bitops.h header as we need it, alphabetize header order.
Signed-off-by: Olliver Schinagl
Signed-off-by: Priit Laes
Acked-for-MFD-by: Lee Jones
---
drivers/mfd/axp20x.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git
From: Olliver Schinagl
The AXP20X_OFF define is an actual specific bit, define it as such.
Signed-off-by: Olliver Schinagl
Signed-off-by: Priit Laes
Acked-for-MFD-by: Lee Jones
---
drivers/mfd/axp20x.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mfd/axp20x.c
This is a second edition of a series that implements voltage
ramping for AXP209 DCDC2 and LDO3 regulators and software
based soft-start for AXP209 LDO3 regulator.
Both features are needed to work around a PMIC shutdown when
toggling LDO3 on certain boards with high capacitance on the
LDO3 output.
From: Olliver Schinagl
In the past, there have been words on various lists that if LDO3 is
disabled in u-boot, but enabled in the DTS, the axp209 driver would
fail to continue/hang. Several enable/disable patches have been
issues to devicetree's in both the kernel and u-boot to address
this
From: Olliver Schinagl
The AXP209 supports ramping up voltages on several regulators such as
DCDC2 and LDO3, therefore we can use the standard 'regulator-ramp-delay'
property for those 2 regulators.
Note that the voltage ramp only works when the regulator is already
enabled. E.g. when going
Hi,
I frequently have to flash Allwinner devices (V40 based), and I am
wondering if anybody has figured out how to enter FEL mode via USB (without
pressing buttons, shorting pins, or using an SD card).
PhoenixSuit can do this, if you click "Upgrade" it will reboot to FEL mode.
Then, when it
On Tue, Nov 27, 2018 at 03:42:48PM +0800, Icenowy Zheng wrote:
> Some SoCs adds a bus clock gate to the Mali Midgard GPU.
>
> Add the binding for the bus clock.
>
> Signed-off-by: Icenowy Zheng
> ---
> Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt | 6 ++
> 1 file changed, 6
Hi Priit and Olliver,
On Tue, Dec 11, 2018 at 5:42 AM Priit Laes wrote:
>
> From: Olliver Schinagl
>
> The AXP209 supports ramping up voltages on several regulators such as
> DCDC2 and LDO3.
>
> This patch adds preliminary support for the regulator-ramp-delay property
> for these 2 regulators.
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