On Sat, Jul 13, 2019 at 11:46:34AM +0800, Icenowy Zheng wrote:
> Lichee zero plus is a core board made by Sipeed, which includes on-board
> TF slot or SMT SD NAND, and optional SPI NOR or eMMC, a UART debug
> header, a microUSB slot and a gold finger connector for expansion. It
> can use either
On Sat, Jul 13, 2019 at 11:46:33AM +0800, Icenowy Zheng wrote:
> The Lichee Zero Plus is a core board made by Sipeed, with a microUSB
> connector on it, TF slot or WSON8 SD chip, optional eMMC or SPI Flash.
> It has a gold finger connector for expansion, and UART is available from
> reserved pins
于 2019年7月20日 GMT+08:00 下午5:48:14, Maxime Ripard 写到:
>On Sat, Jul 13, 2019 at 11:46:32AM +0800, Icenowy Zheng wrote:
>> The Allwinner S3/S3L/V3 SoCs all share the same die with the V3s SoC,
>> but with more GPIO wired out of the package.
>>
>> Add DTSI files for these SoCs. The DTSI file for V3
Hi
On Sat, Jul 20, 2019 at 11:32 AM Maxime Ripard
wrote:
>
> On Sat, Jul 20, 2019 at 12:46:27PM +0530, Jagan Teki wrote:
> > On Sat, Jul 20, 2019 at 12:28 PM Maxime Ripard
> > wrote:
> > >
> > > On Thu, Jul 11, 2019 at 07:43:16PM +0200, Michael Nazzareno Trimarchi
> > > wrote:
> > > > > >
On Sat, Jul 13, 2019 at 11:46:29AM +0800, Icenowy Zheng wrote:
> Despite Allwinner V3 and V3s shares the same die, one peripheral (I2S)
> is only available on V3, and thus the clocks is not declared for V3s
> CCU.
>
> Add a V3 CCU compatible string to the binding to prepare for a CCU
> driver that
On Sat, Jul 13, 2019 at 11:46:28AM +0800, Icenowy Zheng wrote:
> The user manual of V3/V3s/S3 declares a PLL_DDR1, however it's forgot
> when developing the V3s CCU driver.
>
> Add back the missing PLL_DDR1.
>
> Fixes: d0f11d14b0bc ("clk: sunxi-ng: add support for V3s CCU")
> Signed-off-by:
On Sat, Jul 13, 2019 at 11:46:30AM +0800, Icenowy Zheng wrote:
> The MMC2 clock slices are currently not defined in V3s CCU driver, which
> makes MMC2 not working.
>
> Fix this issue.
>
> Fixes: d0f11d14b0bc ("clk: sunxi-ng: add support for V3s CCU")
> Signed-off-by: Icenowy Zheng
> ---
> New
On Sat, Jul 13, 2019 at 11:46:32AM +0800, Icenowy Zheng wrote:
> The Allwinner S3/S3L/V3 SoCs all share the same die with the V3s SoC,
> but with more GPIO wired out of the package.
>
> Add DTSI files for these SoCs. The DTSI file for V3 just replaces the
> pinctrl compatible string, and the
于 2019年7月20日 GMT+08:00 下午5:44:49, Maxime Ripard 写到:
>On Sat, Jul 13, 2019 at 11:46:30AM +0800, Icenowy Zheng wrote:
>> The MMC2 clock slices are currently not defined in V3s CCU driver,
>which
>> makes MMC2 not working.
>>
>> Fix this issue.
>>
>> Fixes: d0f11d14b0bc ("clk: sunxi-ng: add
On Sat, Jul 13, 2019 at 11:46:31AM +0800, Icenowy Zheng wrote:
> + [CLK_MMC1] = _clk.common.hw,
> + [CLK_MMC1_SAMPLE] = _sample_clk.common.hw,
> + [CLK_MMC1_OUTPUT] = _output_clk.common.hw,
> + [CLK_MMC2] =
于 2019年7月20日 GMT+08:00 下午6:13:18, Maxime Ripard 写到:
>On Sat, Jul 13, 2019 at 11:46:33AM +0800, Icenowy Zheng wrote:
>> The Lichee Zero Plus is a core board made by Sipeed, with a microUSB
>> connector on it, TF slot or WSON8 SD chip, optional eMMC or SPI
>Flash.
>> It has a gold finger
Dne sobota, 20. julij 2019 ob 07:42:55 CEST je Maxime Ripard napisal(a):
> On Sat, Jul 13, 2019 at 02:03:43PM +0200, Jernej Skrabec wrote:
> > In order to correctly convert image between YUV and RGB, you have to
> > know color encoding and color range. This patch set adds appropriate
> >
On Sat, Jul 20, 2019 at 12:46:27PM +0530, Jagan Teki wrote:
> On Sat, Jul 20, 2019 at 12:28 PM Maxime Ripard
> wrote:
> >
> > On Thu, Jul 11, 2019 at 07:43:16PM +0200, Michael Nazzareno Trimarchi wrote:
> > > > > tcon-pixel clock is the rate that you want to achive on display side
> > > > > and
On Thu, Jul 11, 2019 at 07:43:16PM +0200, Michael Nazzareno Trimarchi wrote:
> > > tcon-pixel clock is the rate that you want to achive on display side
> > > and if you have 4 lanes 32bit or lanes and different bit number that
> > > you need to have a clock that is able to put outside bits and
On Sat, Jul 20, 2019 at 12:28 PM Maxime Ripard
wrote:
>
> On Thu, Jul 11, 2019 at 07:43:16PM +0200, Michael Nazzareno Trimarchi wrote:
> > > > tcon-pixel clock is the rate that you want to achive on display side
> > > > and if you have 4 lanes 32bit or lanes and different bit number that
> > > >
Hi
On Sat., 20 Jul. 2019, 8:58 am Maxime Ripard,
wrote:
> On Thu, Jul 11, 2019 at 07:43:16PM +0200, Michael Nazzareno Trimarchi
> wrote:
> > > > tcon-pixel clock is the rate that you want to achive on display side
> > > > and if you have 4 lanes 32bit or lanes and different bit number that
> >
On Sat, Jul 20, 2019 at 12:46 PM Jagan Teki wrote:
>
> On Sat, Jul 20, 2019 at 12:28 PM Maxime Ripard
> wrote:
> >
> > On Thu, Jul 11, 2019 at 07:43:16PM +0200, Michael Nazzareno Trimarchi wrote:
> > > > > tcon-pixel clock is the rate that you want to achive on display side
> > > > > and if you
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