[linux-sunxi] Re: Allwinner H3 boot from eMMC boot partition

2019-06-14 Thread Roman Beránek
I have no experience with H3 itself, but A64 boots from these partitions in agreement with the eMMC 5.1 (JESD84) specs. Unlike booting from the user partition (the usual case), here BROM expects BOOT0/SPL to be located right at the first sector. On Thursday, May 23, 2019 at 8:13:40 AM UTC+2,

Re: [linux-sunxi] Re: [PATCH v3 1/2] arm64: arch_timer: Workaround for Allwinner A64 timer instability

2019-12-12 Thread Roman Beránek
On Wednesday, December 4, 2019 at 5:19:23 AM UTC+1, Vasily Khoruzhick wrote: > > On Mon, Jan 14, 2019 at 1:25 AM Marc Zyngier > wrote: > > > > Hi Samuel, > > Hi Samuel, > > > On 13/01/2019 02:17, Samuel Holland wrote: > > > The Allwinner A64 SoC is known[1] to have an unstable

[linux-sunxi] Feasibility of using DE2 rotate core to rotate display output?

2020-01-28 Thread Roman Beránek
A good portion of LCD panels available on the market has a portrait orientation. Although the screen rotation can be performed in userspace, a system-wide solution would be much welcome. Seeing the DE2 rotate core be involved in the recently submitted media driver for rotating CSI camera input,

[linux-sunxi] Re: [PATCH] pwm: sun4i: Round delay time up to a nearest jiffy

2021-04-29 Thread Roman Beránek
Hello Uwe, On Thu, Apr 29, 2021 at 2:04 PM Uwe Kleine-König wrote: > > Hello Roman, > > On Wed, Apr 28, 2021 at 02:14:31PM +0200, Roman Beránek wrote: > > Correct, the output may stay in an active state. I only discovered this > > bug as I investigated a report of u

[linux-sunxi] Re: [PATCH] pwm: sun4i: Round delay time up to a nearest jiffy

2021-04-28 Thread Roman Beránek
Hello Uwe, Correct, the output may stay in an active state. I only discovered this bug as I investigated a report of unreliable screen timeout. The period we use the PWM with is 50 us. The PWMx_RDY bit stays 0 well after the last period ends, so if the bit has any function at all, this one is

[linux-sunxi] Re: [PATCH] pwm: sun4i: Round delay time up to a nearest jiffy

2021-04-28 Thread Roman Beránek
Hello Uwe, Correct, the output may stay in an active state. I only discovered this bug as I investigated a report of unreliable screen timeout. The period we use the PWM with is 50 us. The PWMx_RDY bit stays 0 well after the last period ends, so if the bit has any function at all, this one is