On Fri, 2014-02-28 at 15:18 -0800, Dan Williams wrote:
Given that root hub port peers are already established, external hub peer
ports can be determined by traversing the device topology:
1/ ascend to the parent hub and find the upstream port_dev
2/ walk -peer to find the peer port
3/
On Fri, 2014-02-28 at 16:29 -0800, Dan Williams wrote:
On Fri, 2014-02-28 at 15:18 -0800, Dan Williams wrote:
ACPI identifies peer ports by setting their 'group_token' and
'group_position' _PLD data to the same value. If a platform has tier
mismatch [1] , ACPI can override the default
On Fri, 2014-02-28 at 15:18 -0800, Dan Williams wrote:
The usb topology after this change will have symlinks between usb3 ports
and their usb2 peers, for example:
usb2/2-1/2-1:1.0/2-1-port1/peer = ../../../../usb3/3-1/3-1:1.0/3-1-port1
usb2/2-1/2-1:1.0/2-1-port2/peer =
On Fri, 2014-02-28 at 15:18 -0800, Dan Williams wrote:
ClearPortFeature(PORT_POWER) on a usb3 port places the port in either a
DSPORT.Powered-off-detect / DSPORT.Powered-off-reset loop, or the
DSPORT.Powered-off state. There is no way to ensure that RX
terminations will persist in this state,
Hi,
On Mon, Mar 03, 2014 at 05:09:27PM -0600, dingu...@altera.com wrote:
From: Dinh Nguyen dingu...@altera.com
Remove reading the fifo sizes from dts in platform.c
Add dwc2_calculate_dynamic_fifo
Conflicts:
arch/arm/boot/dts/socfpga.dtsi
drivers/staging/dwc2/core.c
if
On Tue, Mar 4, 2014 at 5:47 AM, Sarah Sharp
sarah.a.sh...@linux.intel.com wrote:
Greg, Dave, Freddy, question about cross-subsystem reverts below:
On Fri, Feb 28, 2014 at 04:15:12PM -0500, Alan Stern wrote:
On Fri, 28 Feb 2014, Sarah Sharp wrote:
When testing 3.14-rc1 with a USB 3.0 Lexar
On Mon, Mar 03, 2014 at 05:09:28PM -0600, dingu...@altera.com wrote:
From: Dinh Nguyen dingu...@altera.com
Moves the s3c-hsotg driver into the dwc2 folder and use the dwc2 defines in
hw.h. The s3c-hostg driver will now be built with a kconfig option under
the dwc2 kconfig. USB_DWC2_HOST and
On Mon, Mar 03, 2014 at 05:09:29PM -0600, dingu...@altera.com wrote:
From: Dinh Nguyen dingu...@altera.com
This patch moves the data structures that are in the s3c-hsotg source into
core.h. This is a necessary step towards unifying the s3c-hsotg and dwc2 into
a single DRD.
Signed-off-by:
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA512
On 3/3/14 8:42 PM, Felipe Balbi wrote:
Hi,
On Mon, Mar 03, 2014 at 05:09:27PM -0600, dingu...@altera.com wrote:
From: Dinh Nguyen dingu...@altera.com
Remove reading the fifo sizes from dts in platform.c
Add dwc2_calculate_dynamic_fifo
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA512
Hi Felipe,
On 3/3/14 8:46 PM, Felipe Balbi wrote:
On Mon, Mar 03, 2014 at 05:09:28PM -0600, dingu...@altera.com wrote:
From: Dinh Nguyen dingu...@altera.com
Moves the s3c-hsotg driver into the dwc2 folder and use the dwc2
defines in
hw.h. The
On Mon, Mar 03, 2014 at 08:54:30PM -0600, Dinh Nguyen wrote:
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA512
On 3/3/14 8:42 PM, Felipe Balbi wrote:
Hi,
On Mon, Mar 03, 2014 at 05:09:27PM -0600, dingu...@altera.com wrote:
From: Dinh Nguyen dingu...@altera.com
Remove reading the
On 3/3/14 5:09 PM, dingu...@altera.com wrote:
From: Dinh Nguyen dingu...@altera.com
Hi,
This is a shortened version of the v1 patch to combine the dwc2/s3c-hsotg into
a single dual-role driver. The series will only move the s3c-hsotg driver into
the dwc2 folder, use the defines in the dwc2
From: Dinh Nguyen dingu...@altera.com
Hi,
Apologies for sending the wrong 1st patch of this series.
---
This is a shortened version of the v1 patch to combine the dwc2/s3c-hsotg into
a single dual-role driver. The series will only move the s3c-hsotg driver into
the dwc2 folder, use the defines
From: Dinh Nguyen dingu...@altera.com
In preparation of combining the dwc2/s3c-hsotg driver in a single DRD driver,
the defines in dwc2/hw.h needs to get updated so that the s3c-hsotg driver can
use them.
Signed-off-by: Dinh Nguyen dingu...@altera.com
Cc: Greg Kroah-Hartman
From: Dinh Nguyen dingu...@altera.com
Moves the s3c-hsotg driver into the dwc2 folder and use the dwc2 defines in
hw.h. The s3c-hostg driver will now be built with a kconfig option under
the dwc2 kconfig. USB_DWC2_HOST and USB_S3C_HSOTG are mutually exclusive
build options.
Signed-off-by: Dinh
From: dingu...@altera.com [mailto:dingu...@altera.com]
Sent: Monday, March 03, 2014 2:20 PM
From: Dinh Nguyen dingu...@altera.com
The dwc2 IP on the SOCFPGA cannot use the default HW configured
FIFO sizes. The total FIFO depth as read from GHWCFG3 reports 0x1f80 or 8064
32-bit words. But
Hi Paul,
On 3/3/14 9:14 PM, Paul Zimmerman wrote:
From: dingu...@altera.com [mailto:dingu...@altera.com]
Sent: Monday, March 03, 2014 2:20 PM
From: Dinh Nguyen dingu...@altera.com
The dwc2 IP on the SOCFPGA cannot use the default HW configured
FIFO sizes. The total FIFO depth as read from
From: Dinh Nguyen dingu...@altera.com
The dwc2 IP on the SOCFPGA cannot use the default HW configured
FIFO sizes. The total FIFO depth as read from GHWCFG3 reports 0x1f80 or 8064
32-bit words. But the GRXFSIZ, GNPTXFSIZ, and HPTXFSIZ register defaults
to 0x2000 or 8192 32-bit words. So the driver
When the request length is aligned to maxpacketsize, sometimes
the return length ret the user space requested len.
At that time, we will use min_t(size_t, ret, len) to limit the
size in case of user data buffer overflow.
But we need return the min_t(size_t, ret, len) to tell the user
space
Hello Balbi,
-Original Message-
From: Felipe Balbi [mailto:ba...@ti.com]
Sent: Tuesday, March 04, 2014 12:30 AM
To: Liu, Chuansheng
Cc: ba...@ti.com; gre...@linuxfoundation.org; min...@mina86.com;
linux-usb@vger.kernel.org; linux-ker...@vger.kernel.org; Cohen, David A;
Zhuang, Jin
101 - 120 of 120 matches
Mail list logo
