[linux-yocto][v6.1/standard/preempt-rt/nxp-sdk-6.1/nxp-soc][PATCH] ARM: imx: use raw_spin_lock instead of spin_lock
CPU: 0 PID: 0 Comm: swapper/0 Tainted: GW
5.15.78-rt48-yocto-preempt-rt #1
Hardware name: Freescale i.MX7 Dual (Device Tree)
[<80110f4c>] (unwind_backtrace) from [<8010aef8>] (show_stack+0x18/0x1c)
[<8010aef8>] (show_stack) from [<80be4998>] (dump_stack_lvl+0x40/0x4c)
[<80be4998>] (dump_stack_lvl) from [<8015297c>] (__might_resched+0x16c/0x1f0)
[<8015297c>] (__might_resched) from [<80bf2d8c>] (rt_spin_lock+0x34/0x80)
[<80bf2d8c>] (rt_spin_lock) from [<8011e350>] (imx_set_cpu_jump+0x20/0x70)
[<8011e350>] (imx_set_cpu_jump) from [<8011bd64>]
(imx7d_enter_low_power_idle+0x2e4/0x30c)
[<8011bd64>] (imx7d_enter_low_power_idle) from [<80897bb8>]
(cpuidle_enter_state+0xe8/0x2f0)
[<80897bb8>] (cpuidle_enter_state) from [<80897e18>] (cpuidle_enter+0x3c/0x50)
[<80897e18>] (cpuidle_enter) from [<8015a748>] (do_idle+0x234/0x264)
[<8015a748>] (do_idle) from [<8015aa88>] (cpu_startup_entry+0x20/0x28)
[<8015aa88>] (cpu_startup_entry) from [<81001138>] (start_kernel+0x5b8/0x69c)
[<81001138>] (start_kernel) from [<>] (0x0)
Signed-off-by: Xiaolei Wang
Signed-off-by: Bruce Ashfield
---
arch/arm/mach-imx/src.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/arch/arm/mach-imx/src.c b/arch/arm/mach-imx/src.c
index 2a2fc431d5e7..affaa0428315 100644
--- a/arch/arm/mach-imx/src.c
+++ b/arch/arm/mach-imx/src.c
@@ -35,7 +35,7 @@
#define BP_SRC_A7RCR1_A7_CORE1_ENABLE 1
static void __iomem *src_base;
-static DEFINE_SPINLOCK(src_lock);
+static DEFINE_RAW_SPINLOCK(src_lock);
static bool m4_is_enabled;
static const int sw_reset_bits[5] = {
@@ -64,11 +64,11 @@ static int imx_src_reset_module(struct reset_controller_dev
*rcdev,
bit = 1 << sw_reset_bits[sw_reset_idx];
- spin_lock_irqsave(_lock, flags);
+ raw_spin_lock_irqsave(_lock, flags);
val = readl_relaxed(src_base + SRC_SCR);
val |= bit;
writel_relaxed(val, src_base + SRC_SCR);
- spin_unlock_irqrestore(_lock, flags);
+ raw_spin_unlock_irqrestore(_lock, flags);
timeout = jiffies + msecs_to_jiffies(1000);
while (readl(src_base + SRC_SCR) & bit) {
@@ -89,7 +89,7 @@ void imx_enable_cpu(int cpu, bool enable)
u32 mask, val;
cpu = cpu_logical_map(cpu);
- spin_lock(_lock);
+ raw_spin_lock(_lock);
if (cpu_is_imx7d()) {
/* enable core */
if (enable)
@@ -106,12 +106,12 @@ void imx_enable_cpu(int cpu, bool enable)
val |= 1 << (BP_SRC_SCR_CORE1_RST + cpu - 1);
writel_relaxed(val, src_base + SRC_SCR);
}
- spin_unlock(_lock);
+ raw_spin_unlock(_lock);
}
void imx_set_cpu_jump(int cpu, void *jump_addr)
{
- spin_lock(_lock);
+ raw_spin_lock(_lock);
cpu = cpu_logical_map(cpu);
if (cpu_is_imx7d())
writel_relaxed(__pa_symbol(jump_addr),
@@ -119,7 +119,7 @@ void imx_set_cpu_jump(int cpu, void *jump_addr)
else
writel_relaxed(__pa_symbol(jump_addr),
src_base + SRC_GPR1 + cpu * 8);
- spin_unlock(_lock);
+ raw_spin_unlock(_lock);
}
u32 imx_get_cpu_arg(int cpu)
@@ -172,7 +172,7 @@ void __init imx_src_init(void)
* force warm reset sources to generate cold reset
* for a more reliable restart
*/
- spin_lock(_lock);
+ raw_spin_lock(_lock);
val = readl_relaxed(src_base + SRC_SCR);
/* bit 4 is m4c_non_sclr_rst on i.MX6SX */
@@ -184,7 +184,7 @@ void __init imx_src_init(void)
val &= ~(1 << BP_SRC_SCR_WARM_RESET_ENABLE);
writel_relaxed(val, src_base + SRC_SCR);
- spin_unlock(_lock);
+ raw_spin_unlock(_lock);
}
static const struct of_device_id imx_src_dt_ids[] = {
--
2.25.1
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[linux-yocto][v6.1/standard/preempt-rt/nxp-sdk-6.1/nxp-soc & v6.1/standard/nxp-sdk-6.1/nxp-soc][PATCH 2/2] drm/bridge: adv7533: Limit supported clocks
Refer to commit 323751dadfbe("MLK-21958-13: drm/bridge: adv7511: Limit
supported clocks")
Add Limit supported clocks for adv7533, Some modes are not working with this
converter.
This will cause hdmi link down, so add this workround patch to solve this
problem.
Signed-off-by: Xiaolei Wang
---
drivers/gpu/drm/bridge/adv7511/adv7533.c | 31
1 file changed, 31 insertions(+)
diff --git a/drivers/gpu/drm/bridge/adv7511/adv7533.c
b/drivers/gpu/drm/bridge/adv7511/adv7533.c
index 7316aa092f9b..b09ceb994123 100644
--- a/drivers/gpu/drm/bridge/adv7511/adv7533.c
+++ b/drivers/gpu/drm/bridge/adv7511/adv7533.c
@@ -24,6 +24,26 @@ static const struct reg_sequence
adv7533_cec_fixed_registers[] = {
{ 0x05, 0xc8 },
};
+/*
+ * TODO: Currently, filter-out unsupported modes by their clocks.
+ * Need to find a better way to do this.
+ * These are the pixel clocks that the converter can handle successfully.
+ */
+
+static const int valid_clocks[] = {
+ 148500,
+ 135000,
+ 132000,
+ 119000,
+ 108000,
+ 78750,
+ 74250,
+ 65000,
+ 49500,
+ 4,
+ 31500,
+};
+
static void adv7511_dsi_config_timing_gen(struct adv7511 *adv)
{
struct drm_display_mode *mode = >curr_mode;
@@ -136,6 +156,8 @@ enum drm_mode_status adv7533_mode_valid(struct adv7511 *adv,
unsigned long max_lane_freq;
struct mipi_dsi_device *dsi = adv->dsi;
u8 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
+ size_t i, num_modes = ARRAY_SIZE(valid_clocks);
+ bool clock_ok = false;
/* Check max clock for either 7533 or 7535 */
if (mode->clock > (adv->type == ADV7533 ? 8 : 148500))
@@ -147,6 +169,15 @@ enum drm_mode_status adv7533_mode_valid(struct adv7511
*adv,
if (mode->clock * bpp > max_lane_freq * adv->num_dsi_lanes)
return MODE_CLOCK_HIGH;
+ for (i = 0; i < num_modes; i++)
+ if (mode->clock == valid_clocks[i]) {
+ clock_ok = true;
+ break;
+ }
+
+ if (!clock_ok)
+ return MODE_NOCLOCK;
+
return MODE_OK;
}
--
2.25.1
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[linux-yocto][v6.1/standard/preempt-rt/nxp-sdk-6.1/nxp-soc & v6.1/standard/nxp-sdk-6.1/nxp-soc][PATCH 1/2] LF-8851: dmaengine: imx-sdma: sdma driver code optimization
From: Joy Zou
commit e708cbc250efab668507628d49bfec578b94f3ed from
https://github.com/nxp-imx/linux-imx.git lf-6.1.y
The bluetooth starts to use sdma before sdma driver initialization done.
It will cause NULL pointer access.
This patch adds sdma is_on check in order to avoid accessing NULL pointer.
Reviewed-by: Shengjiu Wang
Signed-off-by: Joy Zou
Signed-off-by: Xiaolei Wang
---
drivers/dma/imx-sdma.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index a5d5aa7b70ce..97269f6d5eec 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -2125,8 +2125,8 @@ static int sdma_config_write(struct dma_chan *chan,
sdmac->watermark_level = 0;
sdma_get_pc(sdmac, sdmac->peripheral_type);
- if (!sdmac->sdma->fw_loaded && sdmac->is_ram_script) {
- dev_warn_once(sdmac->sdma->dev, "sdma firmware not ready!\n");
+ if (!sdmac->sdma->is_on || (!sdmac->sdma->fw_loaded &&
sdmac->is_ram_script)) {
+ dev_warn_once(sdmac->sdma->dev, "sdma or sdma firmware not
ready!\n");
return -EPERM;
}
--
2.25.1
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[linux-yocto]: [kernel for intel-socfpga]: usb: dwc2: combine platform specific data for Intel Agilex and Stratix10
From: Limeng Hi Bruce, This patch is used to combine platform specific data for Intel Agilex and Stratix10. Could you please help to merge it into linux-ycoto kernel repo, both standard and rt branches v6.1/standard/intel-sdk-6.1/intel-socfpga v6.1/standard/preempt-rt/intel-sdk-6.1/intel-socfpga diffstat info as below: Documentation/devicetree/bindings/usb/dwc2.yaml |2 ++ arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi |4 ++-- drivers/usb/dwc2/params.c |6 -- 3 files changed, 8 insertions(+), 4 deletions(-) thanks, Limeng -=-=-=-=-=-=-=-=-=-=-=- Links: You receive all messages sent to this group. View/Reply Online (#12860): https://lists.yoctoproject.org/g/linux-yocto/message/12860 Mute This Topic: https://lists.yoctoproject.org/mt/100189630/21656 Group Owner: linux-yocto+ow...@lists.yoctoproject.org Unsubscribe: https://lists.yoctoproject.org/g/linux-yocto/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[linux-yocto] [PATCH] usb: dwc2: combine platform specific data for Intel Agilex and Stratix10
Intel Stratix10 is very the same with Agilex platform, the DWC2 IP on
the Stratix platform also does not support clock-gating. So, based on
commit 3d8d3504d233("usb: dwc2: Add platform specific data for
Intel's Agilex"), combine platform specific data for Intel Agilex and
Stratix10 together. In additional, in order to avoid breaking the old
device tree, keep compatible string "intel,socfpga-agilex-hsotg" unchanged.
Signed-off-by: Meng Li
---
Documentation/devicetree/bindings/usb/dwc2.yaml | 2 ++
arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 4 ++--
drivers/usb/dwc2/params.c | 6 --
3 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/usb/dwc2.yaml
b/Documentation/devicetree/bindings/usb/dwc2.yaml
index dc4988c0009c..c98ca98d5033 100644
--- a/Documentation/devicetree/bindings/usb/dwc2.yaml
+++ b/Documentation/devicetree/bindings/usb/dwc2.yaml
@@ -51,6 +51,7 @@ properties:
- amlogic,meson-gxbb-usb
- amlogic,meson-g12a-usb
- intel,socfpga-agilex-hsotg
+ - intel,socfpga-hsotg
- const: snps,dwc2
- const: amcc,dwc-otg
- const: apm,apm82181-dwc-otg
@@ -64,6 +65,7 @@ properties:
- const: snps,dwc2
- const: samsung,s3c6400-hsotg
- const: intel,socfpga-agilex-hsotg
+ - const: intel,socfpga-hsotg
reg:
maxItems: 1
diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
index ea788a920eab..c5a51636f657 100644
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
@@ -490,7 +490,7 @@ usbphy0: usbphy@0 {
};
usb0: usb@ffb0 {
- compatible = "snps,dwc2";
+ compatible = "intel,socfpga-hsotg", "snps,dwc2";
reg = <0xffb0 0x4>;
interrupts = <0 93 4>;
phys = <>;
@@ -504,7 +504,7 @@ usb0: usb@ffb0 {
};
usb1: usb@ffb4 {
- compatible = "snps,dwc2";
+ compatible = "intel,socfpga-hsotg", "snps,dwc2";
reg = <0xffb4 0x4>;
interrupts = <0 94 4>;
phys = <>;
diff --git a/drivers/usb/dwc2/params.c b/drivers/usb/dwc2/params.c
index 8eab5f38b110..6bb27a24e9e1 100644
--- a/drivers/usb/dwc2/params.c
+++ b/drivers/usb/dwc2/params.c
@@ -93,7 +93,7 @@ static void dwc2_set_s3c6400_params(struct dwc2_hsotg *hsotg)
p->phy_utmi_width = 8;
}
-static void dwc2_set_socfpga_agilex_params(struct dwc2_hsotg *hsotg)
+static void dwc2_set_socfpga_params(struct dwc2_hsotg *hsotg)
{
struct dwc2_core_params *p = >params;
@@ -266,7 +266,9 @@ const struct of_device_id dwc2_of_match_table[] = {
{ .compatible = "st,stm32mp15-hsotg",
.data = dwc2_set_stm32mp15_hsotg_params },
{ .compatible = "intel,socfpga-agilex-hsotg",
- .data = dwc2_set_socfpga_agilex_params },
+ .data = dwc2_set_socfpga_params },
+ { .compatible = "intel,socfpga-hsotg",
+ .data = dwc2_set_socfpga_params },
{},
};
MODULE_DEVICE_TABLE(of, dwc2_of_match_table);
--
2.34.1
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[linux-yocto][linux-yocto v6.1] add s25fl064l support for marvell cn96xx
Hi Bruce, These 2 patches are for Cypress flash s25fl064l used by customer. Please help to merge them into our linux-yocto repo. repo: linux-yocto branch: v6.1/standard/cn-sdkv5.15/octeon v6.1/standard/preempt-rt/cn-sdkv5.15/octeon Thanks, Ruiqiang -=-=-=-=-=-=-=-=-=-=-=- Links: You receive all messages sent to this group. View/Reply Online (#12857): https://lists.yoctoproject.org/g/linux-yocto/message/12857 Mute This Topic: https://lists.yoctoproject.org/mt/100189437/21656 Group Owner: linux-yocto+ow...@lists.yoctoproject.org Unsubscribe: https://lists.yoctoproject.org/g/linux-yocto/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
[linux-yocto] [PATCH 2/2] mtd: spi-nor: Use CLSR command for FL-L chips
From: Yaliang Wang
S25FL{064|128|256}L chips can't recover from errors, when there are
program error or erase error, P_ERR or E_ERR bit will set to one, WIP
bit will remain set to one, A Clear Status Register command must be sent
to return the device to STANDBY state.
The error first recorded in commit ("mtd: spi-nor: Recover
from Spansion/Cypress errors"). Whlie FL-L chips shifted P_ERR or E_ERR
bits to Status Register 2, which causing the current recover process
doesn't work any more after enabling using CLSR.
Signed-off-by: Yaliang Wang
Upstream-Status: Backport [Wind River Case 00112304]
Signed-off-by: Kalle Pirinen
[RQ: Apply patch to spansion.c.]
Signed-off-by: Ruiqiang Hao
---
drivers/mtd/spi-nor/spansion.c | 91 ++
1 file changed, 70 insertions(+), 21 deletions(-)
diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c
index 5853b1232f9b..b2e220e6b111 100644
--- a/drivers/mtd/spi-nor/spansion.c
+++ b/drivers/mtd/spi-nor/spansion.c
@@ -495,37 +495,84 @@ static void spansion_nor_clear_sr(struct spi_nor *nor)
dev_dbg(nor->dev, "error %d clearing SR\n", ret);
}
+/**
+ * spi_nor_s25fl_l_read_sr2() - Read the Status Register 2 using the
+ * SPINOR_OP_RDSR2_FL_L (07h) command.
+ * @nor: pointer to 'struct spi_nor'.
+ * @sr2: pointer to DMA-able buffer where the value of the
+ * Status Register 2 will be written.
+ *
+ * Return: 0 on success, -errno otherwise.
+ */
+static int spi_nor_s25fl_l_read_sr2(struct spi_nor *nor, u8 *sr2)
+{
+ int ret;
+
+ if (nor->spimem) {
+ struct spi_mem_op op =
+ SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDSR2_FL_L, 1),
+ SPI_MEM_OP_NO_ADDR,
+ SPI_MEM_OP_NO_DUMMY,
+ SPI_MEM_OP_DATA_IN(1, sr2, 1));
+
+ ret = spi_mem_exec_op(nor->spimem, );
+ } else {
+ ret = nor->controller_ops->read_reg(nor, SPINOR_OP_RDSR2_FL_L,
+ sr2, 1);
+ }
+
+ if (ret)
+ dev_dbg(nor->dev, "error %d reading SR2\n", ret);
+
+ return ret;
+}
+
/*
- * Cypress FL-L series devices have redesigned the status register,
- * P_ERR and E_ERR bits are shifted to the status register 2.
+ * spi_nor_s25fl_l_sr_ready() - Query the Status Register to see if the flash
+ * is ready for new commands. Used by Cypress FL-L series chips.
+ * @nor: pointer to 'struct spi_nor'.
+ *
+ * Return: 1 if ready, 0 if not ready, -errno on errors.
*/
static int spi_nor_s25fl_l_sr_ready(struct spi_nor *nor)
{
- u8 sr1, sr2;
+ u8 *sr = nor->bouncebuf;
int ret;
- ret = nor->controller_ops->read_reg(nor, SPINOR_OP_RDSR, , 1);
- if (ret < 0) {
- pr_err("error %d reading SR\n", (int) ret);
+ ret = spi_nor_read_sr(nor, sr);
+ if (ret)
return ret;
- }
- ret = nor->controller_ops->read_reg(nor, SPINOR_OP_RDSR2_FL_L, , 1);
- if (ret < 0) {
- pr_err("error %d reading SR2\n", (int) ret);
+
+ /**
+* P_ERR and E_ERR bits are located in the Status Register 2
+* of Cypress FL-L series chips.
+*/
+ ret = spi_nor_s25fl_l_read_sr2(nor, [1]);
+ if (ret)
return ret;
- }
- if (nor->flags & SNOR_F_USE_CLSR && sr2 & (SR_E_ERR | SR_P_ERR)) {
- if (sr2 & SR_E_ERR)
+ if (nor->flags & SNOR_F_USE_CLSR && sr[1] & (SR_E_ERR | SR_P_ERR)) {
+ if (sr[1] & SR_E_ERR)
dev_err(nor->dev, "Erase Error occurred\n");
else
dev_err(nor->dev, "Programming Error occurred\n");
- nor->controller_ops->write_reg(nor, SPINOR_OP_CLSR, NULL, 0);
+ spi_nor_clear_sr(nor);
+
+ /*
+* WEL bit remains set to one when an erase or page program
+* error occurs. Issue a Write Disable command to protect
+* against inadvertent writes that can possibly corrupt the
+* contents of the memory.
+*/
+ ret = spi_nor_write_disable(nor);
+ if (ret)
+ return ret;
+
return -EIO;
}
- return !(sr1 & SR_WIP);
+ return !(sr[0] & SR_WIP);
}
/**
@@ -538,13 +585,15 @@ static int spi_nor_s25fl_l_sr_ready(struct spi_nor *nor)
static int spansion_nor_sr_ready_and_clear(struct spi_nor *nor)
{
int ret;
- const struct flash_info *tmpinfo = (nor->info == NULL) ? nor->info :
spi_nor_read_id(nor);
+ const struct flash_info *tmpinfo = nor->info ? nor->info :
spi_nor_read_id(nor);
- if (!IS_ERR_OR_NULL(tmpinfo)){
- if (!strcmp(tmpinfo->name, "s25fl064l") ||
!strcmp(tmpinfo->name, "s25fl128l") || !strcmp(tmpinfo->name, "s25fl256l")){
-
[linux-yocto] [PATCH 1/2] mtd/spi-nor: enable USE_CLSR capability for Cypress FL-L product family
From: Yaliang Wang
In Cypress FL-L product family, P_ERR or E_ERR bits are shifted to SR2V,
and are actually being used. Which means we need cope this special
condition accordingly.
Signed-off-by: Yaliang Wang
[RQ: adjust code structure to fit kernel v6.1.]
Signed-off-by: Ruiqiang Hao
---
drivers/mtd/spi-nor/spansion.c | 46 +++---
include/linux/mtd/spi-nor.h| 1 +
2 files changed, 44 insertions(+), 3 deletions(-)
diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c
index 7e7c68fc7776..5853b1232f9b 100644
--- a/drivers/mtd/spi-nor/spansion.c
+++ b/drivers/mtd/spi-nor/spansion.c
@@ -441,13 +441,13 @@ static const struct flash_info spansion_nor_parts[] = {
NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ) },
{ "s25fl064l", INFO(0x016017, 0, 64 * 1024, 128)
NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
- FIXUP_FLAGS(SPI_NOR_4B_OPCODES) },
+ FIXUP_FLAGS(SPI_NOR_4B_OPCODES | USE_CLSR) },
{ "s25fl128l", INFO(0x016018, 0, 64 * 1024, 256)
NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
- FIXUP_FLAGS(SPI_NOR_4B_OPCODES) },
+ FIXUP_FLAGS(SPI_NOR_4B_OPCODES | USE_CLSR) },
{ "s25fl256l", INFO(0x016019, 0, 64 * 1024, 512)
NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
- FIXUP_FLAGS(SPI_NOR_4B_OPCODES) },
+ FIXUP_FLAGS(SPI_NOR_4B_OPCODES | USE_CLSR) },
{ "s25hl512t", INFO6(0x342a1a, 0x0f0390, 256 * 1024, 256)
PARSE_SFDP
MFR_FLAGS(USE_CLSR)
@@ -495,6 +495,39 @@ static void spansion_nor_clear_sr(struct spi_nor *nor)
dev_dbg(nor->dev, "error %d clearing SR\n", ret);
}
+/*
+ * Cypress FL-L series devices have redesigned the status register,
+ * P_ERR and E_ERR bits are shifted to the status register 2.
+ */
+static int spi_nor_s25fl_l_sr_ready(struct spi_nor *nor)
+{
+ u8 sr1, sr2;
+ int ret;
+
+ ret = nor->controller_ops->read_reg(nor, SPINOR_OP_RDSR, , 1);
+ if (ret < 0) {
+ pr_err("error %d reading SR\n", (int) ret);
+ return ret;
+ }
+ ret = nor->controller_ops->read_reg(nor, SPINOR_OP_RDSR2_FL_L, , 1);
+ if (ret < 0) {
+ pr_err("error %d reading SR2\n", (int) ret);
+ return ret;
+ }
+
+ if (nor->flags & SNOR_F_USE_CLSR && sr2 & (SR_E_ERR | SR_P_ERR)) {
+ if (sr2 & SR_E_ERR)
+ dev_err(nor->dev, "Erase Error occurred\n");
+ else
+ dev_err(nor->dev, "Programming Error occurred\n");
+
+ nor->controller_ops->write_reg(nor, SPINOR_OP_CLSR, NULL, 0);
+ return -EIO;
+ }
+
+ return !(sr1 & SR_WIP);
+}
+
/**
* spansion_nor_sr_ready_and_clear() - Query the Status Register to see if the
* flash is ready for new commands and clear it if there are any errors.
@@ -505,6 +538,13 @@ static void spansion_nor_clear_sr(struct spi_nor *nor)
static int spansion_nor_sr_ready_and_clear(struct spi_nor *nor)
{
int ret;
+ const struct flash_info *tmpinfo = (nor->info == NULL) ? nor->info :
spi_nor_read_id(nor);
+
+ if (!IS_ERR_OR_NULL(tmpinfo)){
+ if (!strcmp(tmpinfo->name, "s25fl064l") ||
!strcmp(tmpinfo->name, "s25fl128l") || !strcmp(tmpinfo->name, "s25fl256l")){
+ return spi_nor_s25fl_l_sr_ready(nor);
+ }
+ }
ret = spi_nor_read_sr(nor, nor->bouncebuf);
if (ret)
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index fb8a0b8ed242..c21d4aa2be6d 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -87,6 +87,7 @@
/* Used for Spansion flashes only. */
#define SPINOR_OP_BRWR 0x17/* Bank register write */
+#define SPINOR_OP_RDSR2_FL_L 0x07/* Read status register 2 */
/* Used for Micron flashes only. */
#define SPINOR_OP_RD_EVCR 0x65/* Read EVCR register */
--
2.35.5
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