From: Quanyang Wang
Add kernel-cache files for Aptiv sousa and fl platforms.
Signed-off-by: Quanyang Wang
---
Hi Bruce,
Would you please help merge this patch to the branch:
yocto-5.15
Thanks,
Quanyang
---
bsp/aptiv-s32g/aptiv-cvc-fl-preempt-rt.scc| 7 +
From: Quanyang Wang
This patch comes from the patch:
meta-cvc-fl/recipes-kernel/linux/linux-s32/0001-ESL-427-Linux-S32-cvc-support+cleanup.patch
Modifications as below:
1. Change usb phy from "usb-nop-xceiv" to "usb-phy-ulpi-generic".
2. Add "can17_19_en-hog" to enable can17~19.
3. Add
From: Quanyang Wang
The device nodes of "qspi" and "gmac0" are not supported in linux, so we
need to disable them to eliminate error log while booting.
Signed-off-by: Quanyang Wang
---
arch/arm64/boot/dts/freescale/s32gxxxa-cvc-fl.dtsi | 6 --
1 file changed, 4 insertions(+), 2
From: Quanyang Wang
Add pinctrls for pfe0/1/2 interfaces for Aptiv-FL board. Note that
RTL9010 phys need to be configured at u-boot.
This patch comes from:
meta-cvc-fl/recipes-kernel/linux/linux-s32/0001-ESL-427-Linux-S32-cvc-support+cleanup.patch
Signed-off-by: Quanyang Wang
---
From: Quanyang Wang
Simply copied from s32g2xxa-evb-pfems.dts.
Signed-off-by: Quanyang Wang
---
.../dts/freescale/s32g274a-aptiv-pfems.dts| 21 +++
1 file changed, 21 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/s32g274a-aptiv-pfems.dts
diff --git
From: Quanyang Wang
This patch comes from:
meta-aptiv/recipes-aptiv/linux-s32/files/0001-disable-dma-coherent-for-pfe-for-cut-1.1-compat.patch
Signed-off-by: Quanyang Wang
---
arch/arm64/boot/dts/freescale/s32g274a-aptiv.dts | 1 +
1 file changed, 1 insertion(+)
diff --git
From: Quanyang Wang
Set "status" properties of pfe relevant device nodes to be "okay" to
enable these devices.
Signed-off-by: Quanyang Wang
---
.../boot/dts/freescale/s32g274a-aptiv.dts | 42 +++
1 file changed, 42 insertions(+)
diff --git
From: Olaf Benninghaus
Add new dts file for Aptiv CVC board.
And this patch is based on:
recipes-kernel/linux-s32/files/fsl-s32g274a-aptiv.dts
Signed-off-by: Olaf Benninghaus
Signed-off-by: Quanyang Wang
---
arch/arm64/boot/dts/freescale/Makefile| 1 +
From: Quanyang Wang
Add pinctrl assignment for flexcan3. And the pin CAN17_19_EN which
is wired out from TCA9539's pin[13], add a device-tree node
s32g_can17_19_en to enable CAN17~19 which correspond flexcan1~3.
Signed-off-by: Quanyang Wang
---
.../boot/dts/freescale/s32g274a-aptiv.dts |
From: Quanyang Wang
Hi Bruce,
Would you please help merge these 9 patches to the branches:
v5.15/standard/preempt-rt/nxp-sdk-5.10/nxp-s32g
v5.15/standard/nxp-sdk-5.10/nxp-s32g
Thanks,
Quanyang
Olaf Benninghaus (1):
dts: Aptiv: Add new dts for Aptiv CVC board
Quanyang Wang
From: Quanyang Wang
This patch is based on the file 0001-enable-CAN0_STB-pullup.patch
at layer meta-aptiv/recipes-aptiv/linux-s32/files/.
Signed-off-by: Olaf Benninghaus
[Quanyang: add pull-up of GPIO9 for CAN0_EN.]
Signed-off-by: Quanyang Wang
---
Hi Bruce,
On 3/1/23 23:27, Bruce Ashfield wrote:
In message: [linux-yocto][v5.15/standard/preempt-rt/sdkv5.15/xlnx-soc]
xlnx-soc: update to SDK 2022.02
on 27/02/2023 Quanyang Wang wrote:
Hi Bruce,
Would you please help merge the patches to the 2 branches:
From: Quanyang Wang
This patch is to add scc/cfg meta to build and boot Xilinx Versal
platforms.
Signed-off-by: Quanyang Wang
---
Hi Bruce,
Would you please help merge this patch to the branch:
yocto-5.15
Thanks,
Quanyang
---
.../xilinx-versal-preempt-rt.scc | 9 +
Hi Bruce,
Would you please help merge the patches to the 2 branches:
v5.15/standard/preempt-rt/sdkv5.15/xlnx-soc
v5.15/standard/sdkv5.15/xlnx-soc
Thanks,
Quanyang
The following changes since commit ee2f99d1f2467ebc250895caf1e5bfdd5a91bd56:
Merge branch 'v5.15/standard/base' into
From: Quanyang Wang
In upstream commit 5c294de36e7f ("Revert "usb: dwc3: disable USB core
PHY management""), dwc3_xhci_plat_priv is deleted. But when this commit
is merged into yocto, this struct is still there. So deleting this
struct to fix compile error.
Signed-off-by: Quanyang Wang
---
Hi
From: Zqiang
This change is similar to the following patch,
it also suitable for arm.
[
Author: Steven Rostedt (VMware)
Email: rost...@goodmis.org
Subject: tracing/arm64: Have max stack tracer handle the case of return address
after data
Date: Fri, 9 Aug 2019 02:15:05 +
Most archs (well
From: Quanyang Wang
The kernel option CONFIG_FS_CONFIGFS is needed by the feature DTB
Overlay. So we need bring it back.
Signed-off-by: Quanyang Wang
---
Hi Bruce,
Would you please help merge this patch to the branch:
yocto-5.15
Thanks,
Quanyang
---
bsp/xilinx-zynqmp/xilinx-zynqmp.cfg
From: Quanyang Wang
commit a7e02f7796c163ac8297b30223bf24bade9f8a50 upstream
When running xrandr to change resolution of DP, the kmemleak as below
can be observed:
unreferenced object 0x00080a351000 (size 256):
comm "Xorg", pid 248, jiffies 4294899614 (age 19.960s)
hex dump (first 32
From: Quanyang Wang
The irq functions "siul2_gpio_irq_unmask" and "siul2_gpio_irq_mask"
use spin_lock in preempt-rt kernel, it will cause the error that
calling a sleeping function in an atomic context.
Use raw spinlock to fix this issue.
Upstream-Status: Pending
Signed-off-by: Quanyang Wang
From: Quanyang Wang
Hi Bruce,
Would you please help merge these 3 patches to the branches:
v5.15/standard/preempt-rt/nxp-sdk-5.10/nxp-s32g
v5.15/standard/nxp-sdk-5.10/nxp-s32g
Thanks,
Quanyang
Quanyang Wang (3):
gpio: s32: force regmap use raw spinlock
gpio: s32: switch
From: Quanyang Wang
The functions "siul2_gpio_dir_in" and "siul2_gpio_free" have been
registered to be callbacks as "gc->direction_input" and "gc->free".
When the callbacks "irq_chip->irq_set_type/irq_unmask/irq_mask"
are called, the caller should guarantee that it will call
gc->direction_input
From: Quanyang Wang
The regmap subsystem use mutex lock as its default lock but this will
cause the error that calling sleeping functions in an atomic context
since the irq callbacks "irq_set_type/irq_mask/irq_unmask" for
siul2-s32cc are all using regmap_update_bits.
Add use_raw_spinlock flag
From: Quanyang Wang
Add generic ulpi usb phy kernel option.
Signed-off-by: Quanyang Wang
---
Hi Bruce,
Would you please help merge this patch to the branch:
yocto-5.15
Thanks,
Quanyang
---
bsp/nxp-s32g/nxp-s32g.cfg | 1 +
1 file changed, 1 insertion(+)
diff --git
From: Quanyang Wang
Add initialization for the structure usb_phy.
And a series of operations "flush-stop-reset" is needed so that we can
access usb phy via ULPI interface.
And otg_set_vbus is called after the host mode is determined because
we need call ulpi_set_vbus to set vbus via it.
From: Quanyang Wang
This driver is for generic ulpi usb phys.
Signed-off-by: Quanyang Wang
---
drivers/usb/phy/Kconfig| 8
drivers/usb/phy/Makefile | 1 +
drivers/usb/phy/phy-ulpi-generic.c | 76 ++
3 files changed, 85 insertions(+)
From: Quanyang Wang
Since a new usb phy driver for ulpi otg phys is introduced, we switch to
it instead of using "Nop USB Transceiver driver". This is because that
we shouldn't rely on the usb phy initialization in u-boot.
Signed-off-by: Quanyang Wang
---
From: Quanyang Wang
Add new ulpi IDs which are available on S32G-EVB and Aptiv boards.
Signed-off-by: Quanyang Wang
---
drivers/usb/phy/phy-ulpi.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/usb/phy/phy-ulpi.c b/drivers/usb/phy/phy-ulpi.c
index e683a37e3a7a..cbf3fb1a1d47
From: Quanyang Wang
Hi Bruce,
Would you please help merge these 4 patches to the branches:
v5.15/standard/preempt-rt/nxp-sdk-5.10/nxp-s32g
v5.15/standard/nxp-sdk-5.10/nxp-s32g
Thanks,
Quanyang
Quanyang Wang (4):
usb: phy: Add ulpi IDs for NXP SAF1508 and ST STULPI01A
usb:
From: Quanyang Wang
CONFIG_ARM_CCI_PMU depends on PERF_EVENTS which is not enabled for
preempt-rt, so the building warning as below can be caught:
[NOTE]: 'CONFIG_ARM_CCI_PMU' last val (y) and .config val (n) do not match
[INFO]: CONFIG_ARM_CCI_PMU : n
[INFO]: raw config text:
From: Quanyang Wang
Add xilinx-zynqmp-preempt-rt.scc to enable preempt-rt for xilinx-zynqmp.
Signed-off-by: Quanyang Wang
Signed-off-by: Bruce Ashfield
---
Hi Bruce,
Would you please help merge this patch to the branch:
yocto-5.15
It's picked up from yocto-5.10.
Thanks,
Quanyang
---
Hi Bruce,
This patch is for v5.15, I wrote a wrong kernel version in Subject.
Thanks,
Quanyang
On 5/31/22 15:49, quanyang.wang wrote:
From: Adam Borowski
commit e5b5d25444e9ee3ae439720e62769517d331fa39 upstream.
Address of a field inside a struct can't possibly be null; gcc-12 warns
about
From: Adam Borowski
commit e5b5d25444e9ee3ae439720e62769517d331fa39 upstream.
Address of a field inside a struct can't possibly be null; gcc-12 warns
about this.
Signed-off-by: Adam Borowski
Signed-off-by: Rafael J. Wysocki
---
Hi Bruce,
Would you please help merge this patch to the
From: Quanyang Wang
The commit bd7f84708ea02 ("usb: dwc3: gadget: Return proper request
status") loses part of mainline commit. Let's bring it back.
And it fixes the compile warning:
drivers/usb/dwc3/gadget.c:2944:6: warning: unused variable ‘request_status’
[-Wunused-variable]
2944 | int
From: Quanyang Wang
Hi Bruce,
Would you please help merge these 3 patches to the branches:
v5.15/standard/preempt-rt/nxp-sdk-5.10/nxp-s32g
v5.15/standard/nxp-sdk-5.10/nxp-s32g
Thanks,
Quanyang
Quanyang Wang (3):
mtd: spi-nor: macronix: allow using mx25uw512 in Octal DTR mode
From: Quanyang Wang
Because of upstream commit 0e30f47232ab57 ("mtd: spi-nor: add support
for DTR protocol"), the 8-8-8 DTR mode read opcode needs to be adjusted
to be "(code << 8) | code" or (code << 8 | ~ code) according to the cmd
opcode extension which is clarified as "repeat" or "revert".
From: Quanyang Wang
There are 80 LUTs in qspi controller, and every 5 LUTs form a sequence
to generate a valid flash transaction. A sequence corresponds to a LUT
config. And the maximum of LUT configs are 16.
Now the implimentation of s32g qspi driver is that one type of cmd
opcode occupies one
From: Quanyang Wang
Set reading setting for read proto SNOR_PROTO_8_8_8_DTR with 10 dummy
cicles (will be doubled to be 20 in spi_nor_spimem_read_data) and
special read command "0xEE".
Set nor->cmd_ext_type to be SPI_NOR_EXT_REPEAT because the function
spi_nor_get_cmd_ext will check this, or
From: Quanyang Wang
The phy->id is an unique id under _ida after calling phy_create,
but the s32g serdes driver uses it to save lane_id (0 or 1), this results
that phy->id is not unique anymore and will trigger calltrace as below
for being freed multiple times.
[ 129.135513] ida_free called
Hi Paul,
On 4/27/22 22:52, Paul Gortmaker wrote:
[[linux-yocto][v5.15/standard/preempt-rt/nxp-sdk-5.10/nxp-s32g][PATCH] s32g:
serdes: add new function get_lane_id to retrieve lane_id] On 27/04/2022 (Wed
19:32) quanyang.wang wrote:
From: Quanyang Wang
The phy->id is an unique id under _
From: Quanyang Wang
The phy->id is an unique id under _ida after calling phy_create,
but the s32g serdes driver uses it to save lane_id (0 or 1), this results
that phy->id is not unique anymore and will trigger calltrace as below
for being freed multiple times.
[ 129.135513] ida_free called
From: Quanyang Wang
Because of the upstream commit e4c777fd8c371 ("amba: Make the remove callback
return void"), we need change the return type of sp804_wdt_axxia_remove
from "int" to "void".
Signed-off-by: Quanyang Wang
---
Hi Bruce,
Would you please help merge this patch to the branches to:
From: Quanyang Wang
Bring back modifications caused by commit 2c357e027725 ("ASoC: xilinx:
xlnx_formatter_pcm: Handle sysclk setting") to fix compile error.
Signed-off-by: Quanyang Wang
---
sound/soc/xilinx/xlnx_formatter_pcm.c | 2 ++
1 file changed, 2 insertions(+)
diff --git
From: Quanyang Wang
Fix compile errors which introduced by commit bbd91cdb620e ("net: axienet:
fix RX ring refill allocation failure handling"). It's because there is
a redundant bracket.
Signed-off-by: Quanyang Wang
---
drivers/net/ethernet/xilinx/xilinx_axienet_main.c | 5 ++---
1 file
From: Quanyang Wang
Hi Bruce,
Would you please help merge these 3 patches to the branches:
v5.10/standard/sdkv5.10/xlnx-soc
v5.10/standard/preempt-rt/sdkv5.10/xlnx-soc
Thanks,
Quanyang
Quanyang Wang (3):
xhci: bring back modification of declarition of xhci_handshake
ASoC: xilinx: add
From: Quanyang Wang
There is a compile error introduced by commit 811f40351949 ("xhci: make
xhci_handshake timeout for xhci_reset() adjustable") and it's caused by
the modification in the declarition of xhci_handshake is missing. Let's
bring it back to fix compile error.
Signed-off-by: Quanyang
Hi Bruce,
Would you please help create a new branch
v5.15/standard/nxp-sdk-5.10/nxp-s32g in linux-yocto
and apply the patches as below to this new branch?
The following changes since commit c9f3902d8069e32a8928153a38d8f6115194d128:
aufs: reduce overhead for "code present but disabled" use
Hi Bruce,
Would you please help create a new branch
v5.15/standard/preempt-rt/nxp-sdk-5.10/nxp-s32g in linux-yocto
and apply the patches as below to this new branch?
The following changes since commit 29d051cc421a76432897019edc33edae35b16e39:
aufs: update compile fix for v5.15+ preempt-rt
Hi Amit,
On 4/7/22 19:40, Amit Kumar Mahapatra wrote:
Hello Quanyang,
-Original Message-
From: Quanyang Wang
Sent: Friday, March 11, 2022 5:20 PM
To: Amit Kumar Kumar Mahapatra ; Bruce
; Michal Simek
Cc: linux-yocto@lists.yoctoproject.org
Subject: Re: [PATCH 6/7] Revert "mtd:
Hi Amit,
On 3/11/22 19:31, Amit Kumar Kumar Mahapatra wrote:
Hello Quanyang,
-Original Message-
From: quanyang.w...@windriver.com
Sent: Tuesday, October 19, 2021 1:46 PM
To: Bruce ; michal.si...@xilinx.com
Cc: linux-yocto@lists.yoctoproject.org; amit.kumar-mahapa...@xilinx.com
From: Quanyang Wang
In the document "S32G2 Reference Manual" Section 38.1.4, it says that
"QuadSPI AHB region h-1FFF is non-cacheable". So we
shouldn't use ioremap_cache to map this region since the system will
consider this region as normal cacheable memory. Let's use devm_ioremap
On Mon, Feb 7, 2022 at 11:31 PM Quanyang Wang
wrote:
Ping.
On 2/7/22 13:52, quanyang.wang wrote:
From: Quanyang Wang
When merging mainline commit bb193e3db8b8 ("net: axienet: fix for TX busy
handling"), the old function axienet_check_tx_bd_space was brought back,
so we need to delete
Ping.
On 2/7/22 13:52, quanyang.wang wrote:
From: Quanyang Wang
When merging mainline commit bb193e3db8b8 ("net: axienet: fix for TX busy
handling"), the old function axienet_check_tx_bd_space was brought back,
so we need to delete it to fix compile error.
When merging mainl
From: Quanyang Wang
When merging mainline commit bb193e3db8b8 ("net: axienet: fix for TX busy
handling"), the old function axienet_check_tx_bd_space was brought back,
so we need to delete it to fix compile error.
When merging mainline commit 95978df6fa32 ("net: axienet: add missing
memory
From: Quanyang Wang
When merging mainline commit bb193e3db8b8 ("net: axienet: fix for TX busy
handling"), the old function axienet_check_tx_bd_space was brought back,
so we need to delete it to fix compile error.
When merging mainline commit 95978df6fa32 ("net: axienet: add missing
memory
From: Quanyang Wang
The unit-address of cpu4 wasn't changed to match the reg value along
with other cpus. This patch is to fix this.
Reported-by: Mikael Beckius
Signed-off-by: Quanyang Wang
---
Hi Bruce,
Would you please help merge this patche to
linux-yocto
From: Quanyang Wang
Since graphic system use /dev/input/eventX as input device, we need
enable CONFIG_INPUT_EVDEV kernel option.
Signed-off-by: Quanyang Wang
---
Hi Bruce,
Would you please help merge this patch to branches:
yocto-kernel-cache yocto-5.10
yocto-kernel-cache master
Thanks,
From: Quanyang Wang
The macro AXXIA_DEBUG_UART_VIRT is defined to be 0xf008 which
is not in vmalloc zone (0xf080-0xff80), and it will trigger
warning as below:
BUG: mapping for 0x201008 at 0xf008 out of vmalloc space
So change the value to be 0xf088 to avoid this
From: Quanyang Wang
There should be one "@" between node-name and unit-address.
Signed-off-by: Quanyang Wang
---
Hi Bruce,
Would you please help merge this patch to the following linux-yocto branches:
v5.10/standard/preempt-rt/sdkv5.10/xlnx-soc
v5.10/standard/sdkv5.10/xlnx-soc
Thanks,
From: Quanyang Wang
Add xilinx-zynqmp-preempt-rt.scc to enable preempt-rt for xilinx-zynqmp.
Signed-off-by: Quanyang Wang
---
bsp/xilinx-zynqmp/xilinx-zynqmp-preempt-rt.scc | 9 +
1 file changed, 9 insertions(+)
create mode 100644 bsp/xilinx-zynqmp/xilinx-zynqmp-preempt-rt.scc
diff
From: Quanyang Wang
CONFIG_ARM_CCI_PMU depends on PERF_EVENTS which is not enabled for
preempt-rt, so the building warning as below can be caught:
[NOTE]: 'CONFIG_ARM_CCI_PMU' last val (y) and .config val (n) do not match
[INFO]: CONFIG_ARM_CCI_PMU : n
[INFO]: raw config text:
From: Quanyang Wang
The BP feature for n25q128a11 is dropped by the SDK commit 65ffd1e667c0
("mtd: spi-nor: Update flags for serial NOR flash devices"). Let's bring
it back to enable flash_lock/unlock at zc702 board.
Signed-off-by: Quanyang Wang
---
Hi Bruce,
Would you please help merge this
ping.
On 11/8/21 9:15 AM, quanyang.wang wrote:
Hi Bruce,
Would you please help merge this pull request to linux-yocto
v5.10/standard/sdkv5.10/xlnx-soc ?
There are 17 patches in this pull request and they are all picked from
git://github.com/Xilinx/linux-xlnx.git xlnx_rebase_v5.10
From: Quanyang Wang
If the size of array stack_var is 1024, it will trigger the build
warning as below:
arch/arm/mach-axxia/ddr_retention.c:220:1: warning: the frame size of 1032
bytes is larger than 1024 bytes [-Wframe-larger-than=]
220 | }
| ^
Since substracting 1K for 4 times from
From: Quanyang Wang
This reverts commit b48ce4a44d42a7b92f13c8d64a53d23cd6689222.
The intent of exercise_stack_ptr is to keep the 4K-size stack of
ncp_ddr_shutdown in L2 cache for the later usage.
But using heap will break this. So revert it now.
Reported-by: Mikael Beckius
Signed-off-by:
From: Quanyang Wang
When running the command:
#echo 1 > /proc/driver/axxia_ddr_retention_reset
the function usleep_range is called at an atomic context, using udelay
can avoid the calltrace as below:
BUG: scheduling while atomic: sh/519/0x0002
Modules linked in:
CPU: 12 PID: 519
From: Quanyang Wang
Hi Bruce,
Would you please help merge these 3 patches to the braches:
linux-yocto v5.10/standard/preempt-rt/sdkv5.10/axxia
linux-yocto v5.10/standard/sdkv5.10/axxia
Thanks,
Quanyang
Quanyang Wang (3):
Revert "arm: axxia: ddr_retention: use malloc/free to fix
Hi Bruce,
Would you please help merge this pull request to linux-yocto
v5.10/standard/sdkv5.10/xlnx-soc ?
There are 17 patches in this pull request and they are all picked from
git://github.com/Xilinx/linux-xlnx.git xlnx_rebase_v5.10
No modification on them.
Thanks,
Quanyang
The
From: Quanyang Wang
Change all unit-address for cpus to match the reg value.
Reported-by: Mikael Beckius
Signed-off-by: Quanyang Wang
---
arch/arm64/boot/dts/intel/axm5608-cpus.dtsi | 8 +++
arch/arm64/boot/dts/intel/axm5612-cpus.dtsi | 16 +++---
From: Quanyang Wang
Hi Bruce,
Would you please help merge these 2 patches to
linux-yocto v5.10/standard/preempt-rt/sdkv5.10/axxia
linux-yocto v5.10/standard/sdkv5.10/axxia
Thanks,
Quanyang
Quanyang Wang (2):
arm: dts: axxia: the unit-address should match the reg value
ARM64: dts: axxia:
From: Quanyang Wang
Change all unit-address for cpus to match the reg value.
Reported-by: Mikael Beckius
Signed-off-by: Quanyang Wang
---
arch/arm/boot/dts/axm5508-cpus.dtsi | 8
arch/arm/boot/dts/axm5512-cpus.dtsi | 16
arch/arm/boot/dts/axm5516-cpus.dtsi | 22
Hi Micke
On 11/4/21 5:33 PM, Beckius, Mikael wrote:
Hello Quanyang!
I spent some with the mpidr when creating a runtime fixup for customer
boards with a fixed dtb and I got the impression that the unit-address
should match the reg value?
Thank you for pointing this out.
I will send a
From: Quanyang Wang
In the commit 996ca36db0e5 ("arm64: zynqmp: adjust qspi flash partition"),
I adjust the partition "qspi-rootfs" to cover the address 0x1e0.
But this address is used to store the parameters for u-boot v2019.2 by
default. Erase this partition will corrupt parameters data.
From: Quanyang Wang
This reverts commit 634a317469fe7d6b59d41d5cf5b59fc827864741.
The commit ("mtd: spi-nor: Simplify odd address handling in read for
dual parallel mode") introduces an issue that passes an odd address to
spi driver. When "nor->isparallel && (from & 1)" is true, running "++buf"
From: Quanyang Wang
This reverts commit 9f2e5a64a4621d8986af9d5ac063ce77ec7fe279.
Now the code for flash lock/unlock in linux-yocto can work with
zynqmp/zc706/zc702 boards and the SDK patches break them. let's
revert it.
Signed-off-by: Quanyang Wang
---
drivers/mtd/spi-nor/core.c | 133
From: Quanyang Wang
This reverts commit d2944ea38702eb5b3efcbd36bffcb35dffd7fe15.
Now the code for flash lock/unlock in linux-yocto can work with
zynqmp/zc706/zc702 boards and the SDK patches break them. let's
revert it.
Signed-off-by: Quanyang Wang
---
drivers/mtd/spi-nor/core.c| 21
From: Quanyang Wang
When enabling dual mode for 2 flashes, spi_nor_sr_lock/unlock/is_locked
can handle it since the variables including mtd_size/sector_size/ofs/len
are both doubled and this will not affect the calculation of BP bits
value.
Signed-off-by: Quanyang Wang
---
From: Quanyang Wang
There are 16MBx2 flashes at zcu102 revA board, so adjust the total size
of partitions to 32MB. This is also for flash_lock/unlock since the top
sectors in flash must be visible in order to be locked/unlocked.
And adjust the order and size of partitions to make sure that the
From: Quanyang Wang
There are mt25qu512a(64MB)x2 flashes at zcu102 rev1.0 board. So we add
an overlay partition node to enlarge the total flash size to 128MB.
And this is also for flash_lock/unlock since the top sectors in flash
must be visible in order to be locked/unlocked.
Signed-off-by:
From: Quanyang Wang
The flash "mt25qu512a" supports Block Protection feature. According to
the datasheet, the features as below are supported:
- 4-bit BP
- BP3 in bit6 of SR
- Top/Bottom area
So add appropriate flags for this flash to enable flash_lock/unlock.
Signed-off-by: Quanyang Wang
From: Quanyang Wang
Hi Bruce & Michal,
Would you please help review and merge these patches to the branch:
linux-yocto v5.10/standard/sdkv5.10/xlnx-soc
This series fix the flash lock/unlock issue at zcu102/zc706/zc702 board.
The patch "mtd: spi-nor: swp: fix unlock lower area
From: Quanyang Wang
Hi Bruce,
Would you please help merge this 2 patches to the branches of
linux-yocto:
v5.10/standard/preempt-rt/sdkv5.10/axxia
v5.10/standard/sdkv5.10/axxia
Thanks,
Quanyang
Quanyang Wang (2):
arm-ccn: only disable HN-I node reporting error for axm56xx
axxia: don't
From: Quanyang Wang
The commit da1913558259 ("arm-ccn: disable HN-I node reporting error
to MN node") is a workaround for the issue caused by ATF running in
axm56xx platforms. And it breaks A53 (Waco/6700) systems. So add
the condition check to fix this.
Signed-off-by: Quanyang Wang
---
From: Quanyang Wang
Axm55xx which supports LPAE has a physical memory range that is larger
than 4G. And the USB controller only supports 32-bit DMA mask. This
means if block subsystem passes an address beyond 4G to USB for a DMA
operation, it will result failure unless calling swiotlb to provide
From: Manish Narani
commit 124b11cc4f6276e9e435802b160c368f35f59e1a upstream.
The clocks are configured by devm_clk_bulk_get_all() in this driver. In
case of any error the clocks freeing will be handled automatically.
There is no need to explicitly free the clocks. Fix the same.
Fixes:
+Ivar
On 10/8/21 2:04 PM, quanyang.wang wrote:
From: Ivar Holmqvist
When adding support for mcdma the free_tx_chain function was
accidentally broken. The loop that scans the tx descriptors
for completed buffers does not increment the consumer index
tx_bd_ci, that is done by the caller in bulk
From: Ivar Holmqvist
When adding support for mcdma the free_tx_chain function was
accidentally broken. The loop that scans the tx descriptors
for completed buffers does not increment the consumer index
tx_bd_ci, that is done by the caller in bulk, so the check
for completed buffers always failed
Hi Bruce,
Would you please help merge this pull request to linux-yocto
v5.10/standard/sdkv5.10/xlnx-soc ?
There are 185 patches in this pull request and they are all picked from
git://github.com/Xilinx/linux-xlnx.git xlnx_rebase_v5.10
No modification on them.
Thanks,
Quanyang
The
From: Quanyang Wang
The "smp_store_release" is defined in include/asm-generic/barrier.h
which is included by arch/microblaze/include/asm/barrier.h.
When we use gcc to preprocess asm-offsets.c to .i file, we can see that
none of the header files included before list.h contains "asm/barrier.h",
On 9/29/21 9:41 PM, quanyang.wang wrote:
From: Quanyang Wang
The "smp_store_release" is defined in include/asm-generic/barrier.h
which is included by arch/microblaze/include/asm/barrier.h.
When we use gcc to propress
Oh, it should be "preprocess". I will send a V2 patch
From: Quanyang Wang
This reverts commit ab3bdf9a2e54f682a95c05538af71e0e6ef8223d.
Since the commit ("microblaze: add to ")
has fixed the compile error for microblaze, let's bring back the
mainline patch which introduces list_del_init_careful.
Signed-off-by: Quanyang Wang
---
From: Quanyang Wang
The "smp_store_release" is defined in include/asm-generic/barrier.h
which is included by arch/microblaze/include/asm/barrier.h.
When we use gcc to propress asm-offsets.c to .i file, we can see that
none of the header files included before list.h contains "asm/barrier.h",
From: Quanyang Wang
Hi Michal & Bruce,
Would you please help review these 2 patches?
There is a compile error for xilinx BSP when yocto kernel bump to .69.
block/blk-iocost.c:1407:2: error: implicit declaration of function
‘list_del_init_careful’; did you mean ‘hlist_del_init_rcu’?
From: Quanyang Wang
The spi controller pl022 supports interrupt/dma/poll modes. But in
interrupt/dma modes, there is calltrace as below which indicates that
the driver calls sleeping function under atomic context:
BUG: sleeping function called from invalid context at drivers/spi/spi.c:1211
From: Quanyang Wang
According to Documentation/devicetree/bindings/arm/cpus.yaml, the reg
property should represent for MPIDR[23:0] register bits but not the
hwcpu index.
Reported-by: Mikael Beckius
Signed-off-by: Quanyang Wang
---
arch/arm/boot/dts/axm5508-cpus.dtsi | 8
From: Quanyang Wang
Hi Bruce,
Would you please help merge this patch to the branches of
linux-yocto:
v5.10/standard/preempt-rt/sdkv5.10/axxia
v5.10/standard/sdkv5.10/axxia
Thanks,
Quanyang
Quanyang Wang (2):
arm: axxia: axxia-gic: pass mpdir to get_logical_index
arm: dts: axxia: change
From: Quanyang Wang
The function get_logical_index is used to retrieve cpu index from mpidr,
but irq_cpuid[irqid] is not mpidr but logical cpu. So we need to use
cpu_logical_map to transform "logical cpu" to mpidr first.
Signed-off-by: Quanyang Wang
---
arch/arm/mach-axxia/axxia-gic.c | 2 +-
From: Quanyang Wang
Use set/vlear/test_bit() APIs can simplify the code.
Signed-off-by: Quanyang Wang
---
arch/arm/mach-axxia/hotplug.c | 16 +---
1 file changed, 5 insertions(+), 11 deletions(-)
diff --git a/arch/arm/mach-axxia/hotplug.c b/arch/arm/mach-axxia/hotplug.c
index
From: Quanyang Wang
The function irq_finalize_oneshot is called after local_bh_disable()
in irq_forced_thread_fn, and there is operation sequences as below:
-> local_bh_disable() <= Will call rcu_read_lock() to increase
rcu_preempt_depth()
-> irq_finalize_oneshot
From: Quanyang Wang
The ARM's ccn-504 consists of MN/DT/HN-I/SBSX/HN-F/RN-I/XP components.
And HN-I/SBSX/HN-F/RN-F/XP will report error event to MN component.
But in ccn driver arm-ccn.c, it only registers 2 handlers to handle
events from DT(pmu) and HN-F(l3 cache edac). So when there is an
From: Quanyang Wang
Disable CONFIG_CC_OPTIMIZE_FOR_SIZE and CONFIG_FUNCTION_GRAPH_TRACER to
fix the warning when do_kernel_configcheck:
[NOTE]: 'CONFIG_FUNCTION_GRAPH_TRACER' last val (y) and .config val (n) do not
match
[INFO]: CONFIG_FUNCTION_GRAPH_TRACER : n ## .config: 4212
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