[linux-yocto] [PATCH] Revert "cgroup: Disable cgroup "memory" by default"

[Meng.Li]

From: Limeng 

This reverts commit 42647e31456a0736141b8566bd22894670c1c7a7.

It is not reasonable to disable a common cgroup feature.
Now, there is enough memory on raspberrypi 4 platform.

Signed-off-by: Meng Li 
---
 kernel/cgroup/cgroup.c | 30 --
 1 file changed, 30 deletions(-)

diff --git a/kernel/cgroup/cgroup.c b/kernel/cgroup/cgroup.c
index f199722519bb..080561bb8a4b 100644
--- a/kernel/cgroup/cgroup.c
+++ b/kernel/cgroup/cgroup.c
@@ -5705,8 +5705,6 @@ int __init cgroup_init_early(void)
 }
 
 static u16 cgroup_disable_mask __initdata;
-static u16 cgroup_enable_mask __initdata;
-static int __init cgroup_disable(char *str);
 
 /**
  * cgroup_init - cgroup initialization
@@ -5746,12 +5744,6 @@ int __init cgroup_init(void)
 
mutex_unlock(_mutex);
 
-   /* Apply an implicit disable... */
-   cgroup_disable("memory");
-
-   /* ...knowing that an explicit enable will override it. */
-   cgroup_disable_mask &= ~cgroup_enable_mask;
-
for_each_subsys(ss, ssid) {
if (ss->early_init) {
struct cgroup_subsys_state *css =
@@ -6171,28 +6163,6 @@ static int __init cgroup_disable(char *str)
 }
 __setup("cgroup_disable=", cgroup_disable);
 
-static int __init cgroup_enable(char *str)
-{
-   struct cgroup_subsys *ss;
-   char *token;
-   int i;
-
-   while ((token = strsep(, ",")) != NULL) {
-   if (!*token)
-   continue;
-
-   for_each_subsys(ss, i) {
-   if (strcmp(token, ss->name) &&
-   strcmp(token, ss->legacy_name))
-   continue;
-
-   cgroup_enable_mask |= 1 << i;
-   }
-   }
-   return 1;
-}
-__setup("cgroup_enable=", cgroup_enable);
-
 void __init __weak enable_debug_cgroup(void) { }
 
 static int __init enable_cgroup_debug(char *str)
-- 
2.17.1

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[linux-yocto] [linux-yocto-dev]: [kernel standard/bcm-2xxx-rpi]: bcm-2xxx-rpi: Revert "cgroup: Disable cgroup "memory" by default"

[Meng.Li]

From: Limeng 

Hi Bruce,

After kts test, we found out cgroup case failed. 
The reason is that raspberrypi SDK kernel disable cgroup "memory" feature.

It is not reasonable to disable a common cgroup feature.
Because there is enough memory on latest raspberrypi 4 platform.

Could you please help to merge this patch into branch standard/bcm-2xxx-rpi, 
linux-ycoto-dev kernel.

diffstat info ad below:

 cgroup.c |   30 --
 1 file changed, 30 deletions(-)


thanks,
Limeng
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[linux-yocto] [PATCH 2/2] driver: usb: otg: fix build warning

[Meng.Li]

From: Limeng 

Fix in file dwc_otg_pcd_intr.c
It is not reasonable to set the size of an array with a variable.
So, instead of define array directly, use kmalloc() to apply
memory space, and free it with kfree().

Fix in file dwc_otg_hcd_linux.c
Use the correct format string to output warning information.

Signed-off-by: Meng Li 
---
 drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c | 4 ++--
 drivers/usb/host/dwc_otg/dwc_otg_pcd_intr.c  | 6 --
 2 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c 
b/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c
index 08a3e41038a3..b2bb701f187e 100644
--- a/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c
+++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c
@@ -482,8 +482,8 @@ static void hcd_init_fiq(void *cookie)
otg_dev->os_dep.mphi_base + 0x1f0;
dwc_otg_hcd->fiq_state->mphi_regs.swirq_clr =
otg_dev->os_dep.mphi_base + 0x1f4;
-   DWC_WARN("Fake MPHI regs_base at 0x%08x",
-(int)dwc_otg_hcd->fiq_state->mphi_regs.base);
+   DWC_WARN("Fake MPHI regs_base at %px",
+dwc_otg_hcd->fiq_state->mphi_regs.base);
} else {
dwc_otg_hcd->fiq_state->mphi_regs.ctrl =
otg_dev->os_dep.mphi_base + 0x4c;
diff --git a/drivers/usb/host/dwc_otg/dwc_otg_pcd_intr.c 
b/drivers/usb/host/dwc_otg/dwc_otg_pcd_intr.c
index e55ea9c74be4..8e88f6898998 100644
--- a/drivers/usb/host/dwc_otg/dwc_otg_pcd_intr.c
+++ b/drivers/usb/host/dwc_otg/dwc_otg_pcd_intr.c
@@ -3377,7 +3377,7 @@ void predict_nextep_seq( dwc_otg_core_if_t * core_if)
dtknq1_data_t dtknqr1;
uint32_t in_tkn_epnums[4];
uint8_t seqnum[MAX_EPS_CHANNELS];
-   uint8_t intkn_seq[TOKEN_Q_DEPTH];
+   uint8_t *intkn_seq;
grstctl_t resetctl = {.d32 = 0 };
uint8_t temp;
int ndx = 0;
@@ -3390,6 +3390,8 @@ void predict_nextep_seq( dwc_otg_core_if_t * core_if)
 
DWC_DEBUGPL(DBG_PCD,"dev_token_q_depth=%d\n",TOKEN_Q_DEPTH);
 
+   intkn_seq = kmalloc(TOKEN_Q_DEPTH, GFP_KERNEL);
+
/* Read the DTKNQ Registers */
for (i = 0; i < DTKNQ_REG_CNT; i++) {
in_tkn_epnums[i] = DWC_READ_REG32(addr);
@@ -3530,7 +3532,7 @@ void predict_nextep_seq( dwc_otg_core_if_t * core_if)
resetctl.b.intknqflsh = 1;
DWC_WRITE_REG32(_if->core_global_regs->grstctl, resetctl.d32);
 
-
+   kfree(intkn_seq);
 }
 
 /**
-- 
2.17.1

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[linux-yocto] [linux-yocto-5.2]: [kernel v5.2/standard/bcm-2xxx-rpi]: bcm-2xxx-rpi: fix build warning

[Meng.Li]

From: Limeng 

Hi Bruce,

I fix some building warnings for raspberrypi plarform.

Could you please help to merge the 2 patches into branch 
v5.2/standard/bcm-2xxx-rpi, linux-ycoto kernel.

diffstat info ad below:

 dma/bcm2835-dma.c|2 +-
 usb/host/dwc_otg/dwc_otg_hcd_linux.c |4 ++--
 usb/host/dwc_otg/dwc_otg_pcd_intr.c  |6 --
 3 files changed, 7 insertions(+), 5 deletions(-)

thanks,
Limeng
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[linux-yocto] [PATCH 1/2] driver: bcm2835-dma: fix build warning

[Meng.Li]

From: Limeng 

refer to raspberrypi SDK kernel, branch rpi-5.4.y, commit
e89769eb3d4b("bcm2835-dma: Add proper 40-bit DMA support").
Add a casting before using variable base to fix the build
warning.

Signed-off-by: Meng Li 
---
 drivers/dma/bcm2835-dma.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/dma/bcm2835-dma.c b/drivers/dma/bcm2835-dma.c
index 1e2c597e038f..acbcbb68c22b 100644
--- a/drivers/dma/bcm2835-dma.c
+++ b/drivers/dma/bcm2835-dma.c
@@ -1178,7 +1178,7 @@ static int bcm2835_dma_probe(struct platform_device *pdev)
return PTR_ERR(base);
 
/* The set of channels can be split across multiple instances. */
-   chan_start = ((u32)base / BCM2835_DMA_CHAN_SIZE) & 0xf;
+   chan_start = ((u32)(uintptr_t)base / BCM2835_DMA_CHAN_SIZE) & 0xf;
base -= BCM2835_DMA_CHAN(chan_start);
chan_count = resource_size(res) / BCM2835_DMA_CHAN_SIZE;
chan_end = min(chan_start + chan_count,
-- 
2.17.1

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[linux-yocto] [PATCH] dma-direct: Temporary DMA fix on arm64

[Meng.Li]

From: Phil Elwell 

commit 370e6f18b566f7880f538f5d9e9ca2953389b446 from
https://github.com/raspberrypi/linux.git

See: https://github.com/raspberrypi/linux/issues/3251

Signed-off-by: Phil Elwell 
Signed-off-by: Meng Li 
---
 kernel/dma/direct.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/kernel/dma/direct.c b/kernel/dma/direct.c
index 9912be7..bf1846a 100644
--- a/kernel/dma/direct.c
+++ b/kernel/dma/direct.c
@@ -379,7 +379,7 @@ int dma_direct_supported(struct device *dev, u64 mask)
if (IS_ENABLED(CONFIG_ZONE_DMA))
min_mask = DMA_BIT_MASK(ARCH_ZONE_DMA_BITS);
else
-   min_mask = DMA_BIT_MASK(32);
+   min_mask = DMA_BIT_MASK(30);
 
min_mask = min_t(u64, min_mask, (max_pfn - 1) << PAGE_SHIFT);
 
-- 
2.7.4

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[linux-yocto] [linux-yocto-5.2]: [kernel v5.2/standard/bcm-2xxx-rpi]: bcm-2xxx-rpi: dma-direct: Temporary DMA fix on arm64

[Meng.Li]

From: Limeng 

Hi Bruce,

After bts test, we found out dma case failed. 
Because below commit is pushed into mainline kernel
66bdb1478fd1("swiotlb: Use dma_direct_supported() for swiotlb_ops")
But raspberrypi SDK kernel haven't done corresponding modification to 
compatible with mainline
There is only a Temporary fixing for DMA. So, I got it to fix the DMA 
initialization issue temporarily.

Could you please help to merge this patch into branch 
v5.2/standard/bcm-2xxx-rpi, linux-ycoto kernel.

diffstat info ad below:

 direct.c |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)


thanks,
Limeng
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[linux-yocto] [PATCH] Revert "cgroup: Disable cgroup "memory" by default"

[Meng.Li]

From: Limeng 

This reverts commit bf6bf37699fcba93dbcf88e97c45c0b835d2dd4c.

It is not reasonable to disable a common cgroup feature.
Now, there is enough memory on raspberrypi 4 platform.

Signed-off-by: Meng Li 
---
 kernel/cgroup/cgroup.c | 30 --
 1 file changed, 30 deletions(-)

diff --git a/kernel/cgroup/cgroup.c b/kernel/cgroup/cgroup.c
index 81292f2f0da9..d2cba714d3ee 100644
--- a/kernel/cgroup/cgroup.c
+++ b/kernel/cgroup/cgroup.c
@@ -5661,8 +5661,6 @@ int __init cgroup_init_early(void)
 }
 
 static u16 cgroup_disable_mask __initdata;
-static u16 cgroup_enable_mask __initdata;
-static int __init cgroup_disable(char *str);
 
 /**
  * cgroup_init - cgroup initialization
@@ -5703,12 +5701,6 @@ int __init cgroup_init(void)
 
mutex_unlock(_mutex);
 
-   /* Apply an implicit disable... */
-   cgroup_disable("memory");
-
-   /* ...knowing that an explicit enable will override it. */
-   cgroup_disable_mask &= ~cgroup_enable_mask;
-
for_each_subsys(ss, ssid) {
if (ss->early_init) {
struct cgroup_subsys_state *css =
@@ -6125,28 +6117,6 @@ static int __init cgroup_disable(char *str)
 }
 __setup("cgroup_disable=", cgroup_disable);
 
-static int __init cgroup_enable(char *str)
-{
-   struct cgroup_subsys *ss;
-   char *token;
-   int i;
-
-   while ((token = strsep(, ",")) != NULL) {
-   if (!*token)
-   continue;
-
-   for_each_subsys(ss, i) {
-   if (strcmp(token, ss->name) &&
-   strcmp(token, ss->legacy_name))
-   continue;
-
-   cgroup_enable_mask |= 1 << i;
-   }
-   }
-   return 1;
-}
-__setup("cgroup_enable=", cgroup_enable);
-
 void __init __weak enable_debug_cgroup(void) { }
 
 static int __init enable_cgroup_debug(char *str)
-- 
2.23.0

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[linux-yocto] [linux-yocto-5.2]: [kernel v5.2/standard/bcm-2xxx-rpi]: bcm-2xxx-rpi: Revert "cgroup: Disable cgroup "memory" by default"

[Meng.Li]

From: Limeng 

Hi Bruce,

After kts test, we found out cgroup case failed. 
The reason is that raspberrypi SDK kernel disable cgroup "memory" feature.

It is not reasonable to disable a common cgroup feature.
Because there is enough memory on latest raspberrypi 4 platform.

Could you please help to merge this patch into branch 
v5.2/standard/bcm-2xxx-rpi, linux-ycoto kernel.

diffstat info ad below:

 cgroup.c |   30 --
 1 file changed, 30 deletions(-)


thanks,
Limeng
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[linux-yocto] : [kernel-cache yocto-5.2/master]: renesas-rcar: remove CONFIG_DRM_PANEL_LVDS kernel configure

[Meng.Li]

From: Limeng 

Hi Bruce,

I want to update renesas-rcar bsp kernel configure.

Could you please merge this patch into yocto-kernel-cache, branches are 
yocto-5.2 and master?

0001-renesas-rcar-remove-CONFIG_DRM_PANEL_LVDS-kernel-con.patch

 renesas-rcar.cfg |1 -
 1 file changed, 1 deletion(-)


thanks,
Limeng
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[linux-yocto] [PATCH] renesas-rcar: remove CONFIG_DRM_PANEL_LVDS kernel configure

[Meng.Li]

From: Limeng 

There is no LVDS panel supported on renesas-rcar platform,
So, delete CONFIG_DRM_PANEL_LVDS from kernel configure file.

Signed-off-by: Meng Li 
---
 bsp/renesas-rcar/renesas-rcar.cfg | 1 -
 1 file changed, 1 deletion(-)

diff --git a/bsp/renesas-rcar/renesas-rcar.cfg 
b/bsp/renesas-rcar/renesas-rcar.cfg
index 0e59e903..32c08355 100644
--- a/bsp/renesas-rcar/renesas-rcar.cfg
+++ b/bsp/renesas-rcar/renesas-rcar.cfg
@@ -81,7 +81,6 @@ CONFIG_DRM_I2C_ADV7511_CEC=y
 CONFIG_DRM_DW_HDMI=y
 CONFIG_DRM_DUMB_VGA_DAC=y
 CONFIG_DRM_THINE_THC63LVD1024=y
-CONFIG_DRM_PANEL_LVDS=y
 CONFIG_DRM_DW_HDMI_I2S_AUDIO=y
 
 # Sound configuration
-- 
2.23.0

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[linux-yocto] [PATCH] Revert "arm64: dts: r8a7795: Add CPUIdle support for all CPU core"

[Meng.Li]

From: Limeng 

This reverts commit c93bf81feabf89b5ee77838d3bb62825d04dab09.

Support cpu ilde feature, there are still other related patches
need to be applied, but as a basic BSP, it doesn't recommend to
merge lots of patches to standard/base branch.
In addtional, only get one patch of cpu ilde feature cause system
unstable, so revert it.

Signed-off-by: Meng Li 
---
 arch/arm64/boot/dts/renesas/r8a7795.dtsi | 32 
 1 file changed, 32 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi 
b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index 7596216409cd..097538cc4b1f 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -155,7 +155,6 @@
power-domains = < R8A7795_PD_CA57_CPU0>;
next-level-cache = <_CA57>;
enable-method = "psci";
-   cpu-idle-states = <_SLEEP_0>;
clocks = < CPG_CORE R8A7795_CLK_Z>;
operating-points-v2 = <_opp>;
capacity-dmips-mhz = <1024>;
@@ -169,7 +168,6 @@
power-domains = < R8A7795_PD_CA57_CPU1>;
next-level-cache = <_CA57>;
enable-method = "psci";
-   cpu-idle-states = <_SLEEP_0>;
clocks = < CPG_CORE R8A7795_CLK_Z>;
operating-points-v2 = <_opp>;
capacity-dmips-mhz = <1024>;
@@ -183,7 +181,6 @@
power-domains = < R8A7795_PD_CA57_CPU2>;
next-level-cache = <_CA57>;
enable-method = "psci";
-   cpu-idle-states = <_SLEEP_0>;
clocks = < CPG_CORE R8A7795_CLK_Z>;
operating-points-v2 = <_opp>;
capacity-dmips-mhz = <1024>;
@@ -197,7 +194,6 @@
power-domains = < R8A7795_PD_CA57_CPU3>;
next-level-cache = <_CA57>;
enable-method = "psci";
-   cpu-idle-states = <_SLEEP_0>;
clocks = < CPG_CORE R8A7795_CLK_Z>;
operating-points-v2 = <_opp>;
capacity-dmips-mhz = <1024>;
@@ -211,7 +207,6 @@
power-domains = < R8A7795_PD_CA53_CPU0>;
next-level-cache = <_CA53>;
enable-method = "psci";
-   cpu-idle-states = <_SLEEP_1>;
clocks = < CPG_CORE R8A7795_CLK_Z2>;
operating-points-v2 = <_opp>;
capacity-dmips-mhz = <535>;
@@ -224,7 +219,6 @@
power-domains = < R8A7795_PD_CA53_CPU1>;
next-level-cache = <_CA53>;
enable-method = "psci";
-   cpu-idle-states = <_SLEEP_1>;
clocks = < CPG_CORE R8A7795_CLK_Z2>;
operating-points-v2 = <_opp>;
capacity-dmips-mhz = <535>;
@@ -237,7 +231,6 @@
power-domains = < R8A7795_PD_CA53_CPU2>;
next-level-cache = <_CA53>;
enable-method = "psci";
-   cpu-idle-states = <_SLEEP_1>;
clocks = < CPG_CORE R8A7795_CLK_Z2>;
operating-points-v2 = <_opp>;
capacity-dmips-mhz = <535>;
@@ -250,7 +243,6 @@
power-domains = < R8A7795_PD_CA53_CPU3>;
next-level-cache = <_CA53>;
enable-method = "psci";
-   cpu-idle-states = <_SLEEP_1>;
clocks = < CPG_CORE R8A7795_CLK_Z2>;
operating-points-v2 = <_opp>;
capacity-dmips-mhz = <535>;
@@ -269,30 +261,6 @@
cache-unified;
cache-level = <2>;
};
-
-   idle-states {
-   entry-method = "psci";
-
-   CPU_SLEEP_0: cpu-sleep-0 {
-   compatible = "arm,idle-state";
-   arm,psci-suspend-param = <0x001>;
-   local-timer-stop;
-   entry-latency-us = <400>;
-   exit-latency-us = <500>;
-   min-residency-us = <4000>;
-   status = "okay";
-   };
-
-   CPU_SLEEP_1: cpu-sleep-1 {
-   compatible = "arm,idle-state";
-   arm,psci-suspend-param = <0x001>;
-   local-timer-stop;
-   entry-latency-us = <700>;
-   exit-latency-us = <700>;
-  

[linux-yocto] [linux-yocto-v5.2]: [kernel v5.2/standard/base]: Revert "arm64: dts: r8a7795: Add CPUIdle support for all CPU core"

[Meng.Li]

From: Limeng 

Hi Bruce,

Some days ago, I sent a patch to add CPUIdle feature for renesas-rcar platform. 
This patch only add cpu-idle-states property
in dts file. But after testing, we find out it causes kernel unstable when run 
some stress testing cases.
So, I think maybe I omit other cpuidle related patches.
I intend to revert this patch firstly, and submit all patches related with cpu 
idle featue in later.

0001-Revert-arm64-dts-r8a7795-Add-CPUIdle-support-for-all.patch

Could you please merge this patch into linux-yocto branch are 
v5.2/standard/base?

 r8a7795.dtsi |   32 
 1 file changed, 32 deletions(-)

thanks,
Limeng
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[linux-yocto] [PATCH 5/5] arm64: dts: r8a7795-h3ulcb: Add reserved memory regions

[Meng.Li]

From: Yusuke Goda 

commit 1d40ccc5723b9b3028829194c422a01cf8afd2a3 from
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas-bsp.git

This patch adds reserved memory regions:
  - Lossy Decompression
   48 MiB : 0x005400 -> 0x0056ff
  - Default CMA area
  400 MiB : 0x005700 -> 0x006fff
  - CMA area for MMP
  256 MiB : 0x007000 -> 0x007fff

Signed-off-by: Yusuke Goda 
[takeshi.kihara.df: fix W=1 dtc unit_address_vs_reg warnings]
Signed-off-by: Takeshi Kihara 
Signed-off-by: Meng Li 
---
 .../arm64/boot/dts/renesas/r8a7795-h3ulcb.dts | 29 ++-
 1 file changed, 28 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts 
b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
index 54515eaf0310..b9088a4e0a4a 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
@@ -2,7 +2,7 @@
 /*
  * Device Tree Source for the H3ULCB (R-Car Starter Kit Premier) board
  *
- * Copyright (C) 2016 Renesas Electronics Corp.
+ * Copyright (C) 2016-2017 Renesas Electronics Corp.
  * Copyright (C) 2016 Cogent Embedded, Inc.
  */
 
@@ -34,6 +34,33 @@
device_type = "memory";
reg = <0x7 0x 0x0 0x4000>;
};
+
+   reserved-memory {
+   #address-cells = <2>;
+   #size-cells = <2>;
+   ranges;
+
+   /* device specific region for Lossy Decompression */
+   lossy_decompress: linux,lossy_decompress@5400 {
+   no-map;
+   reg = <0x 0x5400 0x0 0x0300>;
+   };
+
+   /* global autoconfigured region for contiguous allocations */
+   linux,cma@5700 {
+   compatible = "shared-dma-pool";
+   reusable;
+   reg = <0x 0x5700 0x0 0x1900>;
+   linux,cma-default;
+   };
+
+   /* device specific region for contiguous allocations */
+   mmp_reserved: linux,multimedia@7000 {
+   compatible = "shared-dma-pool";
+   reusable;
+   reg = <0x 0x7000 0x0 0x1000>;
+   };
+   };
 };
 
  {
-- 
2.17.1

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[linux-yocto] [PATCH 3/5] pci: pcie-rcar: add regulators support

[Meng.Li]

From: Andrey Gusakov 

Add PCIe regulators for KingFisher board.

Signed-off-by: Meng Li 
---
 arch/arm64/boot/dts/renesas/ulcb-kf.dtsi | 47 +
 drivers/pci/controller/pcie-rcar.c   | 64 
 2 files changed, 111 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi 
b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
index 8986a7e6e099..82e463c32a37 100644
--- a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
+++ b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
@@ -50,6 +50,25 @@
startup-delay-us = <7>;
enable-active-high;
};
+
+   mpcie_3v3: regulator-mpcie_3v3 {
+   compatible = "regulator-fixed";
+   regulator-name = "mPCIe 3v3";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   gpio = <_exp_77 14 GPIO_ACTIVE_HIGH>;
+   enable-active-high;
+   };
+
+   mpcie_1v8: regulator-mpcie_1v8 {
+   compatible = "regulator-fixed";
+   regulator-name = "mPCIe 1v8";
+   regulator-min-microvolt = <180>;
+   regulator-max-microvolt = <180>;
+   gpio = <_exp_77 15 GPIO_ACTIVE_HIGH>;
+   startup-delay-us = <20>;
+   enable-active-high;
+   };
 };
 
  {
@@ -241,6 +260,31 @@
interrupt-controller;
interrupt-parent = <>;
interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
+
+   mpcie_wake {
+   gpio-hog;
+   gpios = <0 GPIO_ACTIVE_HIGH>;
+   output-low;
+   line-name = "mPCIe WAKE#";
+   };
+   mpcie_wdisable {
+   gpio-hog;
+   gpios = <1 GPIO_ACTIVE_HIGH>;
+   output-high;
+   line-name = "mPCIe W_DISABLE";
+   };
+   mpcie_clreq {
+   gpio-hog;
+   gpios = <2 GPIO_ACTIVE_HIGH>;
+   input;
+   line-name = "mPCIe CLKREQ#";
+   };
+   mpcie_ovc {
+   gpio-hog;
+   gpios = <3 GPIO_ACTIVE_HIGH>;
+   input;
+   line-name = "mPCIe OVC";
+   };
};
 };
 
@@ -259,6 +303,9 @@
 
  {
status = "okay";
+
+   pcie3v3-supply = <_3v3>;
+   pcie1v8-supply = <_1v8>;
 };
 
  {
diff --git a/drivers/pci/controller/pcie-rcar.c 
b/drivers/pci/controller/pcie-rcar.c
index f6a669a9af41..8e7e714e33fd 100644
--- a/drivers/pci/controller/pcie-rcar.c
+++ b/drivers/pci/controller/pcie-rcar.c
@@ -14,6 +14,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -151,6 +152,8 @@ struct rcar_pcie {
struct list_headresources;
int root_bus_nr;
struct clk  *bus_clk;
+   struct regulator*pcie3v3; /* 3.3V power supply */
+   struct regulator*pcie1v8; /* 1.8V power supply */
struct  rcar_msi msi;
 };
 
@@ -1120,6 +1123,36 @@ static const struct of_device_id rcar_pcie_of_match[] = {
{},
 };
 
+static int rcar_pcie_set_vpcie(struct rcar_pcie *pcie)
+{
+   struct device *dev = pcie->dev;
+   int err;
+
+   if (!IS_ERR(pcie->pcie3v3)) {
+   err = regulator_enable(pcie->pcie3v3);
+   if (err) {
+   dev_err(dev, "fail to enable vpcie3v3 regulator\n");
+   goto err_out;
+   }
+   }
+
+   if (!IS_ERR(pcie->pcie1v8)) {
+   err = regulator_enable(pcie->pcie1v8);
+   if (err) {
+   dev_err(dev, "fail to enable vpcie1v8 regulator\n");
+   goto err_disable_3v3;
+   }
+   }
+
+   return 0;
+
+err_disable_3v3:
+   if (!IS_ERR(pcie->pcie3v3))
+   regulator_disable(pcie->pcie3v3);
+err_out:
+   return err;
+}
+
 static int rcar_pcie_probe(struct platform_device *pdev)
 {
struct device *dev = >dev;
@@ -1138,6 +1171,31 @@ static int rcar_pcie_probe(struct platform_device *pdev)
pcie->dev = dev;
platform_set_drvdata(pdev, pcie);
 
+   pcie->pcie3v3 = devm_regulator_get_optional(dev, "pcie3v3");
+   if (IS_ERR(pcie->pcie3v3)) {
+   if (PTR_ERR(pcie->pcie3v3) == -EPROBE_DEFER) {
+   pci_free_host_bridge(bridge);
+   return -EPROBE_DEFER;
+   }
+   dev_info(dev, "no pcie3v3 regulator found\n");
+   }
+
+   pcie->pcie1v8 = devm_regulator_get_optional(dev, "pcie1v8");
+   if (IS_ERR(pcie->pcie1v8)) {
+   if (PTR_ERR(pcie->pcie1v8) == -EPROBE_DEFER) {
+   pci_free_host_bridge(bridge);
+   return -EPROBE_DEFER;
+  

[linux-yocto] [PATCH 4/5] arm64: dts: r8a7795: Add CPUIdle support for all CPU core

[Meng.Li]

From: Takeshi Kihara 

commit 3c3b44c752c4eef9a29694f4262934445c5f5da9 from
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas-bsp.git

This patch enables CPUIdle (Core shutdown) support for R-Car H3.

Signed-off-by: Takeshi Kihara 
Signed-off-by: Meng Li 
---
 arch/arm64/boot/dts/renesas/r8a7795.dtsi | 32 
 1 file changed, 32 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi 
b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index 95deff66eeb6..ab36cb8a680c 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -155,6 +155,7 @@
power-domains = < R8A7795_PD_CA57_CPU0>;
next-level-cache = <_CA57>;
enable-method = "psci";
+   cpu-idle-states = <_SLEEP_0>;
dynamic-power-coefficient = <854>;
clocks = < CPG_CORE R8A7795_CLK_Z>;
operating-points-v2 = <_opp>;
@@ -169,6 +170,7 @@
power-domains = < R8A7795_PD_CA57_CPU1>;
next-level-cache = <_CA57>;
enable-method = "psci";
+   cpu-idle-states = <_SLEEP_0>;
clocks = < CPG_CORE R8A7795_CLK_Z>;
operating-points-v2 = <_opp>;
capacity-dmips-mhz = <1024>;
@@ -182,6 +184,7 @@
power-domains = < R8A7795_PD_CA57_CPU2>;
next-level-cache = <_CA57>;
enable-method = "psci";
+   cpu-idle-states = <_SLEEP_0>;
clocks = < CPG_CORE R8A7795_CLK_Z>;
operating-points-v2 = <_opp>;
capacity-dmips-mhz = <1024>;
@@ -195,6 +198,7 @@
power-domains = < R8A7795_PD_CA57_CPU3>;
next-level-cache = <_CA57>;
enable-method = "psci";
+   cpu-idle-states = <_SLEEP_0>;
clocks = < CPG_CORE R8A7795_CLK_Z>;
operating-points-v2 = <_opp>;
capacity-dmips-mhz = <1024>;
@@ -208,6 +212,7 @@
power-domains = < R8A7795_PD_CA53_CPU0>;
next-level-cache = <_CA53>;
enable-method = "psci";
+   cpu-idle-states = <_SLEEP_1>;
#cooling-cells = <2>;
dynamic-power-coefficient = <277>;
clocks = < CPG_CORE R8A7795_CLK_Z2>;
@@ -222,6 +227,7 @@
power-domains = < R8A7795_PD_CA53_CPU1>;
next-level-cache = <_CA53>;
enable-method = "psci";
+   cpu-idle-states = <_SLEEP_1>;
clocks = < CPG_CORE R8A7795_CLK_Z2>;
operating-points-v2 = <_opp>;
capacity-dmips-mhz = <535>;
@@ -234,6 +240,7 @@
power-domains = < R8A7795_PD_CA53_CPU2>;
next-level-cache = <_CA53>;
enable-method = "psci";
+   cpu-idle-states = <_SLEEP_1>;
clocks = < CPG_CORE R8A7795_CLK_Z2>;
operating-points-v2 = <_opp>;
capacity-dmips-mhz = <535>;
@@ -246,6 +253,7 @@
power-domains = < R8A7795_PD_CA53_CPU3>;
next-level-cache = <_CA53>;
enable-method = "psci";
+   cpu-idle-states = <_SLEEP_1>;
clocks = < CPG_CORE R8A7795_CLK_Z2>;
operating-points-v2 = <_opp>;
capacity-dmips-mhz = <535>;
@@ -264,6 +272,30 @@
cache-unified;
cache-level = <2>;
};
+
+   idle-states {
+   entry-method = "psci";
+
+   CPU_SLEEP_0: cpu-sleep-0 {
+   compatible = "arm,idle-state";
+   arm,psci-suspend-param = <0x001>;
+   local-timer-stop;
+   entry-latency-us = <400>;
+   exit-latency-us = <500>;
+   min-residency-us = <4000>;
+   status = "okay";
+   };
+
+   CPU_SLEEP_1: cpu-sleep-1 {
+   compatible = "arm,idle-state";
+   arm,psci-suspend-param = <0x001>;
+   local-timer-stop;
+   entry-latency-us = <700>;
+   exit-latency-us = <700>;
+   min-residency-us = <5000>;
+   status 

[linux-yocto] [PATCH 2/5] driver: net: can: disable clock when it is in enable status

[Meng.Li]

From: Limeng 

If disable a clock when it is already in disable status, there
will be a warning trace generated. So, it is need to confirm
whether what status the clock is in before disable it.

Signed-off-by: Meng Li 
---
 drivers/net/can/rcar/rcar_can.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/net/can/rcar/rcar_can.c b/drivers/net/can/rcar/rcar_can.c
index bf5adea9c0a3..b136a238f7eb 100644
--- a/drivers/net/can/rcar/rcar_can.c
+++ b/drivers/net/can/rcar/rcar_can.c
@@ -15,6 +15,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 #define RCAR_CAN_DRV_NAME  "rcar_can"
@@ -859,7 +860,9 @@ static int __maybe_unused rcar_can_suspend(struct device 
*dev)
writew(ctlr, >regs->ctlr);
priv->can.state = CAN_STATE_SLEEPING;
 
-   clk_disable(priv->clk);
+   if(__clk_is_enabled(priv->clk))
+   clk_disable(priv->clk);
+
return 0;
 }
 
-- 
2.17.1

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[linux-yocto] [linux-yocto-dev]: [kernel standard/base]: renesas-rcar: add some patches to improve features on renesas-rcar platform

[Meng.Li]

From: Limeng 

Hi Bruce,

I am working on BSP renesas-rcar platform, and intend to merge this BSP 
supporting into yocto community.
Below 5 patches are used to improve gpio, CAN BUS, audio and PCIe features

0001-arch-arm64-dts-Set-gpio5-pin9-as-input-by-default.patch
0002-driver-net-can-disable-clock-when-it-is-in-enable-st.patch
0003-pci-pcie-rcar-add-regulators-support.patch
0004-arm64-dts-r8a7795-Add-CPUIdle-support-for-all-CPU-co.patch
0005-arm64-dts-r8a7795-h3ulcb-Add-reserved-memory-regions.patch

Could you please merge the 5 patches into linux-yocto-dev, branch is 
standard/base?

 arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts |   29 ++-
 arch/arm64/boot/dts/renesas/r8a7795.dtsi   |   32 
 arch/arm64/boot/dts/renesas/ulcb-kf.dtsi   |   56 +
 drivers/net/can/rcar/rcar_can.c|5 +
 drivers/pci/controller/pcie-rcar.c |   64 +
 5 files changed, 184 insertions(+), 2 deletions(-)


thanks,
Limeng
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[linux-yocto] [PATCH 1/5] arch: arm64: dts: Set gpio5-pin9 as input by default

[Meng.Li]

From: Limeng 

The gpio5-pin9 is used as the interrupt pin of i2c external
gpio chip, so set this pin as input by default.

Signed-off-by: Meng Li 
---
 arch/arm64/boot/dts/renesas/ulcb-kf.dtsi | 9 +
 1 file changed, 9 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi 
b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
index 202177706cde..8986a7e6e099 100644
--- a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
+++ b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
@@ -205,6 +205,15 @@
};
 };
 
+ {
+   gpio_exp_77_int {
+   gpio-hog;
+   gpios = <9 0>;
+   input;
+   line-name = "gpio-exp-77-int";
+   };
+};
+
  {
i2cswitch4: i2c-switch@71 {
compatible = "nxp,pca9548";
-- 
2.17.1

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[linux-yocto] [PATCH 3/5] pci: pcie-rcar: add regulators support

[Meng.Li]

From: Andrey Gusakov 

Add PCIe regulators for KingFisher board.

Signed-off-by: Meng Li 
---
 arch/arm64/boot/dts/renesas/ulcb-kf.dtsi | 47 +
 drivers/pci/controller/pcie-rcar.c   | 64 
 2 files changed, 111 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi 
b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
index 8986a7e6e099..82e463c32a37 100644
--- a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
+++ b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
@@ -50,6 +50,25 @@
startup-delay-us = <7>;
enable-active-high;
};
+
+   mpcie_3v3: regulator-mpcie_3v3 {
+   compatible = "regulator-fixed";
+   regulator-name = "mPCIe 3v3";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   gpio = <_exp_77 14 GPIO_ACTIVE_HIGH>;
+   enable-active-high;
+   };
+
+   mpcie_1v8: regulator-mpcie_1v8 {
+   compatible = "regulator-fixed";
+   regulator-name = "mPCIe 1v8";
+   regulator-min-microvolt = <180>;
+   regulator-max-microvolt = <180>;
+   gpio = <_exp_77 15 GPIO_ACTIVE_HIGH>;
+   startup-delay-us = <20>;
+   enable-active-high;
+   };
 };
 
  {
@@ -241,6 +260,31 @@
interrupt-controller;
interrupt-parent = <>;
interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
+
+   mpcie_wake {
+   gpio-hog;
+   gpios = <0 GPIO_ACTIVE_HIGH>;
+   output-low;
+   line-name = "mPCIe WAKE#";
+   };
+   mpcie_wdisable {
+   gpio-hog;
+   gpios = <1 GPIO_ACTIVE_HIGH>;
+   output-high;
+   line-name = "mPCIe W_DISABLE";
+   };
+   mpcie_clreq {
+   gpio-hog;
+   gpios = <2 GPIO_ACTIVE_HIGH>;
+   input;
+   line-name = "mPCIe CLKREQ#";
+   };
+   mpcie_ovc {
+   gpio-hog;
+   gpios = <3 GPIO_ACTIVE_HIGH>;
+   input;
+   line-name = "mPCIe OVC";
+   };
};
 };
 
@@ -259,6 +303,9 @@
 
  {
status = "okay";
+
+   pcie3v3-supply = <_3v3>;
+   pcie1v8-supply = <_1v8>;
 };
 
  {
diff --git a/drivers/pci/controller/pcie-rcar.c 
b/drivers/pci/controller/pcie-rcar.c
index f6a669a9af41..8e7e714e33fd 100644
--- a/drivers/pci/controller/pcie-rcar.c
+++ b/drivers/pci/controller/pcie-rcar.c
@@ -14,6 +14,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -151,6 +152,8 @@ struct rcar_pcie {
struct list_headresources;
int root_bus_nr;
struct clk  *bus_clk;
+   struct regulator*pcie3v3; /* 3.3V power supply */
+   struct regulator*pcie1v8; /* 1.8V power supply */
struct  rcar_msi msi;
 };
 
@@ -1120,6 +1123,36 @@ static const struct of_device_id rcar_pcie_of_match[] = {
{},
 };
 
+static int rcar_pcie_set_vpcie(struct rcar_pcie *pcie)
+{
+   struct device *dev = pcie->dev;
+   int err;
+
+   if (!IS_ERR(pcie->pcie3v3)) {
+   err = regulator_enable(pcie->pcie3v3);
+   if (err) {
+   dev_err(dev, "fail to enable vpcie3v3 regulator\n");
+   goto err_out;
+   }
+   }
+
+   if (!IS_ERR(pcie->pcie1v8)) {
+   err = regulator_enable(pcie->pcie1v8);
+   if (err) {
+   dev_err(dev, "fail to enable vpcie1v8 regulator\n");
+   goto err_disable_3v3;
+   }
+   }
+
+   return 0;
+
+err_disable_3v3:
+   if (!IS_ERR(pcie->pcie3v3))
+   regulator_disable(pcie->pcie3v3);
+err_out:
+   return err;
+}
+
 static int rcar_pcie_probe(struct platform_device *pdev)
 {
struct device *dev = >dev;
@@ -1138,6 +1171,31 @@ static int rcar_pcie_probe(struct platform_device *pdev)
pcie->dev = dev;
platform_set_drvdata(pdev, pcie);
 
+   pcie->pcie3v3 = devm_regulator_get_optional(dev, "pcie3v3");
+   if (IS_ERR(pcie->pcie3v3)) {
+   if (PTR_ERR(pcie->pcie3v3) == -EPROBE_DEFER) {
+   pci_free_host_bridge(bridge);
+   return -EPROBE_DEFER;
+   }
+   dev_info(dev, "no pcie3v3 regulator found\n");
+   }
+
+   pcie->pcie1v8 = devm_regulator_get_optional(dev, "pcie1v8");
+   if (IS_ERR(pcie->pcie1v8)) {
+   if (PTR_ERR(pcie->pcie1v8) == -EPROBE_DEFER) {
+   pci_free_host_bridge(bridge);
+   return -EPROBE_DEFER;
+  

[linux-yocto] [PATCH 5/5] arm64: dts: r8a7795-h3ulcb: Add reserved memory regions

[Meng.Li]

From: Yusuke Goda 

commit 1d40ccc5723b9b3028829194c422a01cf8afd2a3 from
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas-bsp.git

This patch adds reserved memory regions:
  - Lossy Decompression
   48 MiB : 0x005400 -> 0x0056ff
  - Default CMA area
  400 MiB : 0x005700 -> 0x006fff
  - CMA area for MMP
  256 MiB : 0x007000 -> 0x007fff

Signed-off-by: Yusuke Goda 
[takeshi.kihara.df: fix W=1 dtc unit_address_vs_reg warnings]
Signed-off-by: Takeshi Kihara 
Signed-off-by: Meng Li 
---
 .../arm64/boot/dts/renesas/r8a7795-h3ulcb.dts | 29 ++-
 1 file changed, 28 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts 
b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
index 54515eaf0310..b9088a4e0a4a 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
@@ -2,7 +2,7 @@
 /*
  * Device Tree Source for the H3ULCB (R-Car Starter Kit Premier) board
  *
- * Copyright (C) 2016 Renesas Electronics Corp.
+ * Copyright (C) 2016-2017 Renesas Electronics Corp.
  * Copyright (C) 2016 Cogent Embedded, Inc.
  */
 
@@ -34,6 +34,33 @@
device_type = "memory";
reg = <0x7 0x 0x0 0x4000>;
};
+
+   reserved-memory {
+   #address-cells = <2>;
+   #size-cells = <2>;
+   ranges;
+
+   /* device specific region for Lossy Decompression */
+   lossy_decompress: linux,lossy_decompress@5400 {
+   no-map;
+   reg = <0x 0x5400 0x0 0x0300>;
+   };
+
+   /* global autoconfigured region for contiguous allocations */
+   linux,cma@5700 {
+   compatible = "shared-dma-pool";
+   reusable;
+   reg = <0x 0x5700 0x0 0x1900>;
+   linux,cma-default;
+   };
+
+   /* device specific region for contiguous allocations */
+   mmp_reserved: linux,multimedia@7000 {
+   compatible = "shared-dma-pool";
+   reusable;
+   reg = <0x 0x7000 0x0 0x1000>;
+   };
+   };
 };
 
  {
-- 
2.17.1

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[linux-yocto] [PATCH 4/5] arm64: dts: r8a7795: Add CPUIdle support for all CPU core

[Meng.Li]

From: Takeshi Kihara 

commit 3c3b44c752c4eef9a29694f4262934445c5f5da9 from
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas-bsp.git

This patch enables CPUIdle (Core shutdown) support for R-Car H3.

Signed-off-by: Takeshi Kihara 
Signed-off-by: Meng Li 
---
 arch/arm64/boot/dts/renesas/r8a7795.dtsi | 32 
 1 file changed, 32 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi 
b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index 95deff66eeb6..ab36cb8a680c 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -155,6 +155,7 @@
power-domains = < R8A7795_PD_CA57_CPU0>;
next-level-cache = <_CA57>;
enable-method = "psci";
+   cpu-idle-states = <_SLEEP_0>;
dynamic-power-coefficient = <854>;
clocks = < CPG_CORE R8A7795_CLK_Z>;
operating-points-v2 = <_opp>;
@@ -169,6 +170,7 @@
power-domains = < R8A7795_PD_CA57_CPU1>;
next-level-cache = <_CA57>;
enable-method = "psci";
+   cpu-idle-states = <_SLEEP_0>;
clocks = < CPG_CORE R8A7795_CLK_Z>;
operating-points-v2 = <_opp>;
capacity-dmips-mhz = <1024>;
@@ -182,6 +184,7 @@
power-domains = < R8A7795_PD_CA57_CPU2>;
next-level-cache = <_CA57>;
enable-method = "psci";
+   cpu-idle-states = <_SLEEP_0>;
clocks = < CPG_CORE R8A7795_CLK_Z>;
operating-points-v2 = <_opp>;
capacity-dmips-mhz = <1024>;
@@ -195,6 +198,7 @@
power-domains = < R8A7795_PD_CA57_CPU3>;
next-level-cache = <_CA57>;
enable-method = "psci";
+   cpu-idle-states = <_SLEEP_0>;
clocks = < CPG_CORE R8A7795_CLK_Z>;
operating-points-v2 = <_opp>;
capacity-dmips-mhz = <1024>;
@@ -208,6 +212,7 @@
power-domains = < R8A7795_PD_CA53_CPU0>;
next-level-cache = <_CA53>;
enable-method = "psci";
+   cpu-idle-states = <_SLEEP_1>;
#cooling-cells = <2>;
dynamic-power-coefficient = <277>;
clocks = < CPG_CORE R8A7795_CLK_Z2>;
@@ -222,6 +227,7 @@
power-domains = < R8A7795_PD_CA53_CPU1>;
next-level-cache = <_CA53>;
enable-method = "psci";
+   cpu-idle-states = <_SLEEP_1>;
clocks = < CPG_CORE R8A7795_CLK_Z2>;
operating-points-v2 = <_opp>;
capacity-dmips-mhz = <535>;
@@ -234,6 +240,7 @@
power-domains = < R8A7795_PD_CA53_CPU2>;
next-level-cache = <_CA53>;
enable-method = "psci";
+   cpu-idle-states = <_SLEEP_1>;
clocks = < CPG_CORE R8A7795_CLK_Z2>;
operating-points-v2 = <_opp>;
capacity-dmips-mhz = <535>;
@@ -246,6 +253,7 @@
power-domains = < R8A7795_PD_CA53_CPU3>;
next-level-cache = <_CA53>;
enable-method = "psci";
+   cpu-idle-states = <_SLEEP_1>;
clocks = < CPG_CORE R8A7795_CLK_Z2>;
operating-points-v2 = <_opp>;
capacity-dmips-mhz = <535>;
@@ -264,6 +272,30 @@
cache-unified;
cache-level = <2>;
};
+
+   idle-states {
+   entry-method = "psci";
+
+   CPU_SLEEP_0: cpu-sleep-0 {
+   compatible = "arm,idle-state";
+   arm,psci-suspend-param = <0x001>;
+   local-timer-stop;
+   entry-latency-us = <400>;
+   exit-latency-us = <500>;
+   min-residency-us = <4000>;
+   status = "okay";
+   };
+
+   CPU_SLEEP_1: cpu-sleep-1 {
+   compatible = "arm,idle-state";
+   arm,psci-suspend-param = <0x001>;
+   local-timer-stop;
+   entry-latency-us = <700>;
+   exit-latency-us = <700>;
+   min-residency-us = <5000>;
+   status 

[linux-yocto] [PATCH 1/5] arch: arm64: dts: Set gpio5-pin9 as input by default

[Meng.Li]

From: Limeng 

The gpio5-pin9 is used as the interrupt pin of i2c external
gpio chip, so set this pin as input by default.

Signed-off-by: Meng Li 
---
 arch/arm64/boot/dts/renesas/ulcb-kf.dtsi | 9 +
 1 file changed, 9 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi 
b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
index 202177706cde..8986a7e6e099 100644
--- a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
+++ b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
@@ -205,6 +205,15 @@
};
 };
 
+ {
+   gpio_exp_77_int {
+   gpio-hog;
+   gpios = <9 0>;
+   input;
+   line-name = "gpio-exp-77-int";
+   };
+};
+
  {
i2cswitch4: i2c-switch@71 {
compatible = "nxp,pca9548";
-- 
2.17.1

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[linux-yocto] [linux-yocto-v5.2]: [kernel standard/base]: renesas-rcar: add some patches to improve features on renesas-rcar platform

[Meng.Li]

From: Limeng 

Hi Bruce,

I am working on BSP renesas-rcar platform, and intend to merge this BSP 
supporting into yocto community.
Below 4 patches are used to improve gpio, CAN BUS, audio and PCIe features
This first patch is from mainline upstream, the other 3 patches merged into 
linux-yocto-dev(standard/base) some days ago.

0001-arm64-dts-renesas-ulcb-kf-Add-support-for-TI-WL1837.patch
0002-arch-arm64-dts-Set-gpio5-pin9-as-input-by-default.patch
0003-driver-net-can-disable-clock-when-it-is-in-enable-st.patch
0004-pci-pcie-rcar-add-regulators-support.patch

Could you please merge the 4 patches into linux-yocto, branch is 
v5.2/standard/base?

 arch/arm64/boot/dts/renesas/ulcb-kf.dtsi |  105 +++
 drivers/net/can/rcar/rcar_can.c  |5 +
 drivers/pci/controller/pcie-rcar.c   |   64 ++
 3 files changed, 173 insertions(+), 1 deletion(-)


thanks,
Limeng
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[linux-yocto] [PATCH 2/5] driver: net: can: disable clock when it is in enable status

[Meng.Li]

From: Limeng 

If disable a clock when it is already in disable status, there
will be a warning trace generated. So, it is need to confirm
whether what status the clock is in before disable it.

Signed-off-by: Meng Li 
---
 drivers/net/can/rcar/rcar_can.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/net/can/rcar/rcar_can.c b/drivers/net/can/rcar/rcar_can.c
index bf5adea9c0a3..b136a238f7eb 100644
--- a/drivers/net/can/rcar/rcar_can.c
+++ b/drivers/net/can/rcar/rcar_can.c
@@ -15,6 +15,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 #define RCAR_CAN_DRV_NAME  "rcar_can"
@@ -859,7 +860,9 @@ static int __maybe_unused rcar_can_suspend(struct device 
*dev)
writew(ctlr, >regs->ctlr);
priv->can.state = CAN_STATE_SLEEPING;
 
-   clk_disable(priv->clk);
+   if(__clk_is_enabled(priv->clk))
+   clk_disable(priv->clk);
+
return 0;
 }
 
-- 
2.17.1

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[linux-yocto] [PATCH] arm64: dts: r8a7795: Add CPUIdle support for all CPU core

[Meng.Li]

From: Takeshi Kihara 

commit 3c3b44c752c4eef9a29694f4262934445c5f5da9 from
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas-bsp.git

This patch enables CPUIdle (Core shutdown) support for R-Car H3.

Signed-off-by: Takeshi Kihara 
Signed-off-by: Meng Li 
---
 arch/arm64/boot/dts/renesas/r8a7795.dtsi | 32 
 1 file changed, 32 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi 
b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index e8c3d5f..7fe7428 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -123,6 +123,7 @@
power-domains = < R8A7795_PD_CA57_CPU0>;
next-level-cache = <_CA57>;
enable-method = "psci";
+   cpu-idle-states = <_SLEEP_0>;
clocks = < CPG_CORE R8A7795_CLK_Z>;
operating-points-v2 = <_opp>;
capacity-dmips-mhz = <1024>;
@@ -135,6 +136,7 @@
power-domains = < R8A7795_PD_CA57_CPU1>;
next-level-cache = <_CA57>;
enable-method = "psci";
+   cpu-idle-states = <_SLEEP_0>;
clocks = < CPG_CORE R8A7795_CLK_Z>;
operating-points-v2 = <_opp>;
capacity-dmips-mhz = <1024>;
@@ -147,6 +149,7 @@
power-domains = < R8A7795_PD_CA57_CPU2>;
next-level-cache = <_CA57>;
enable-method = "psci";
+   cpu-idle-states = <_SLEEP_0>;
clocks = < CPG_CORE R8A7795_CLK_Z>;
operating-points-v2 = <_opp>;
capacity-dmips-mhz = <1024>;
@@ -159,6 +162,7 @@
power-domains = < R8A7795_PD_CA57_CPU3>;
next-level-cache = <_CA57>;
enable-method = "psci";
+   cpu-idle-states = <_SLEEP_0>;
clocks = < CPG_CORE R8A7795_CLK_Z>;
operating-points-v2 = <_opp>;
capacity-dmips-mhz = <1024>;
@@ -171,6 +175,7 @@
power-domains = < R8A7795_PD_CA53_CPU0>;
next-level-cache = <_CA53>;
enable-method = "psci";
+   cpu-idle-states = <_SLEEP_1>;
clocks = < CPG_CORE R8A7795_CLK_Z2>;
operating-points-v2 = <_opp>;
capacity-dmips-mhz = <535>;
@@ -182,6 +187,7 @@
power-domains = < R8A7795_PD_CA53_CPU1>;
next-level-cache = <_CA53>;
enable-method = "psci";
+   cpu-idle-states = <_SLEEP_1>;
clocks = < CPG_CORE R8A7795_CLK_Z2>;
operating-points-v2 = <_opp>;
capacity-dmips-mhz = <535>;
@@ -193,6 +199,7 @@
power-domains = < R8A7795_PD_CA53_CPU2>;
next-level-cache = <_CA53>;
enable-method = "psci";
+   cpu-idle-states = <_SLEEP_1>;
clocks = < CPG_CORE R8A7795_CLK_Z2>;
operating-points-v2 = <_opp>;
capacity-dmips-mhz = <535>;
@@ -204,6 +211,7 @@
power-domains = < R8A7795_PD_CA53_CPU3>;
next-level-cache = <_CA53>;
enable-method = "psci";
+   cpu-idle-states = <_SLEEP_1>;
clocks = < CPG_CORE R8A7795_CLK_Z2>;
operating-points-v2 = <_opp>;
capacity-dmips-mhz = <535>;
@@ -221,6 +229,30 @@
cache-unified;
cache-level = <2>;
};
+
+   idle-states {
+   entry-method = "psci";
+
+   CPU_SLEEP_0: cpu-sleep-0 {
+   compatible = "arm,idle-state";
+   arm,psci-suspend-param = <0x001>;
+   local-timer-stop;
+   entry-latency-us = <400>;
+   exit-latency-us = <500>;
+   min-residency-us = <4000>;
+   status = "okay";
+   };
+
+   CPU_SLEEP_1: cpu-sleep-1 {
+   compatible = "arm,idle-state";
+   arm,psci-suspend-param = <0x001>;
+   local-timer-stop;
+   entry-latency-us = <700>;
+   exit-latency-us = <700>;
+   min-residency-us = <5000>;
+   status = 

[linux-yocto] [linux-yocto-v5.2]: [kernel standard/base]: renesas-rcar: arm64: dts: r8a7795: Add CPUIdle support for all CPU core

[Meng.Li]

From: Limeng 

Hi Bruce,

I get below patch from SDK kernel to support cpu idle feature, and intend to 
merge it into yocto community.

0001-arm64-dts-r8a7795-Add-CPUIdle-support-for-all-CPU-co.patch

Could you please merge this patch into linux-yocto, branch is 
v5.2/standard/base?

 r8a7795.dtsi |   32 
 1 file changed, 32 insertions(+)


thanks,
Limeng
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[linux-yocto] [PATCH 683/925] arm64: dts: r8a7795-h3ulcb: Add reserved memory regions

[Meng.Li]

From: Yusuke Goda 

commit 1d40ccc5723b9b3028829194c422a01cf8afd2a3 from
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas-bsp.git

This patch adds reserved memory regions:
  - Lossy Decompression
   48 MiB : 0x005400 -> 0x0056ff
  - Default CMA area
  400 MiB : 0x005700 -> 0x006fff
  - CMA area for MMP
  256 MiB : 0x007000 -> 0x007fff

Signed-off-by: Yusuke Goda 
[takeshi.kihara.df: fix W=1 dtc unit_address_vs_reg warnings]
Signed-off-by: Takeshi Kihara 
Signed-off-by: Meng Li 
---
 arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts | 29 +-
 1 file changed, 28 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts 
b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
index 54515ea..b9088a4 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
+++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts
@@ -2,7 +2,7 @@
 /*
  * Device Tree Source for the H3ULCB (R-Car Starter Kit Premier) board
  *
- * Copyright (C) 2016 Renesas Electronics Corp.
+ * Copyright (C) 2016-2017 Renesas Electronics Corp.
  * Copyright (C) 2016 Cogent Embedded, Inc.
  */
 
@@ -34,6 +34,33 @@
device_type = "memory";
reg = <0x7 0x 0x0 0x4000>;
};
+
+   reserved-memory {
+   #address-cells = <2>;
+   #size-cells = <2>;
+   ranges;
+
+   /* device specific region for Lossy Decompression */
+   lossy_decompress: linux,lossy_decompress@5400 {
+   no-map;
+   reg = <0x 0x5400 0x0 0x0300>;
+   };
+
+   /* global autoconfigured region for contiguous allocations */
+   linux,cma@5700 {
+   compatible = "shared-dma-pool";
+   reusable;
+   reg = <0x 0x5700 0x0 0x1900>;
+   linux,cma-default;
+   };
+
+   /* device specific region for contiguous allocations */
+   mmp_reserved: linux,multimedia@7000 {
+   compatible = "shared-dma-pool";
+   reusable;
+   reg = <0x 0x7000 0x0 0x1000>;
+   };
+   };
 };
 
  {
-- 
2.7.4

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[linux-yocto] [linux-yocto-v5.2/dev]: [kernel v5.2/standard/base and standard/base]: renesas-rcar: arm64: dts: r8a7795-h3ulcb: Add reserved memory regions

[Meng.Li]

From: Limeng 

Hi Bruce,

I get below patch from SDK kernel to support reserved memory for renesas 
platform firmware that is integrated in bootloader, and intend to merge it into 
yocto community.

0001-arm64-dts-r8a7795-h3ulcb-Add-reserved-memory-regions.patch

Could you please merge this patch into linux-yocto and linux-yocto-dev, branch 
are v5.2/standard/base and standard/base?

 r8a7795-h3ulcb.dts |   29 -
 1 file changed, 28 insertions(+), 1 deletion(-)


thanks,
Limeng
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[linux-yocto] [PATCH] arm64: dts: r8a7795: Add CPUIdle support for all CPU core

[Meng.Li]

From: Takeshi Kihara 

commit 3c3b44c752c4eef9a29694f4262934445c5f5da9 from
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas-bsp.git

This patch enables CPUIdle (Core shutdown) support for R-Car H3.

Signed-off-by: Takeshi Kihara 
Signed-off-by: Meng Li 
---
 arch/arm64/boot/dts/renesas/r8a7795.dtsi | 32 
 1 file changed, 32 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi 
b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index e8c3d5f..7fe7428 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -123,6 +123,7 @@
power-domains = < R8A7795_PD_CA57_CPU0>;
next-level-cache = <_CA57>;
enable-method = "psci";
+   cpu-idle-states = <_SLEEP_0>;
clocks = < CPG_CORE R8A7795_CLK_Z>;
operating-points-v2 = <_opp>;
capacity-dmips-mhz = <1024>;
@@ -135,6 +136,7 @@
power-domains = < R8A7795_PD_CA57_CPU1>;
next-level-cache = <_CA57>;
enable-method = "psci";
+   cpu-idle-states = <_SLEEP_0>;
clocks = < CPG_CORE R8A7795_CLK_Z>;
operating-points-v2 = <_opp>;
capacity-dmips-mhz = <1024>;
@@ -147,6 +149,7 @@
power-domains = < R8A7795_PD_CA57_CPU2>;
next-level-cache = <_CA57>;
enable-method = "psci";
+   cpu-idle-states = <_SLEEP_0>;
clocks = < CPG_CORE R8A7795_CLK_Z>;
operating-points-v2 = <_opp>;
capacity-dmips-mhz = <1024>;
@@ -159,6 +162,7 @@
power-domains = < R8A7795_PD_CA57_CPU3>;
next-level-cache = <_CA57>;
enable-method = "psci";
+   cpu-idle-states = <_SLEEP_0>;
clocks = < CPG_CORE R8A7795_CLK_Z>;
operating-points-v2 = <_opp>;
capacity-dmips-mhz = <1024>;
@@ -171,6 +175,7 @@
power-domains = < R8A7795_PD_CA53_CPU0>;
next-level-cache = <_CA53>;
enable-method = "psci";
+   cpu-idle-states = <_SLEEP_1>;
clocks = < CPG_CORE R8A7795_CLK_Z2>;
operating-points-v2 = <_opp>;
capacity-dmips-mhz = <535>;
@@ -182,6 +187,7 @@
power-domains = < R8A7795_PD_CA53_CPU1>;
next-level-cache = <_CA53>;
enable-method = "psci";
+   cpu-idle-states = <_SLEEP_1>;
clocks = < CPG_CORE R8A7795_CLK_Z2>;
operating-points-v2 = <_opp>;
capacity-dmips-mhz = <535>;
@@ -193,6 +199,7 @@
power-domains = < R8A7795_PD_CA53_CPU2>;
next-level-cache = <_CA53>;
enable-method = "psci";
+   cpu-idle-states = <_SLEEP_1>;
clocks = < CPG_CORE R8A7795_CLK_Z2>;
operating-points-v2 = <_opp>;
capacity-dmips-mhz = <535>;
@@ -204,6 +211,7 @@
power-domains = < R8A7795_PD_CA53_CPU3>;
next-level-cache = <_CA53>;
enable-method = "psci";
+   cpu-idle-states = <_SLEEP_1>;
clocks = < CPG_CORE R8A7795_CLK_Z2>;
operating-points-v2 = <_opp>;
capacity-dmips-mhz = <535>;
@@ -221,6 +229,30 @@
cache-unified;
cache-level = <2>;
};
+
+   idle-states {
+   entry-method = "psci";
+
+   CPU_SLEEP_0: cpu-sleep-0 {
+   compatible = "arm,idle-state";
+   arm,psci-suspend-param = <0x001>;
+   local-timer-stop;
+   entry-latency-us = <400>;
+   exit-latency-us = <500>;
+   min-residency-us = <4000>;
+   status = "okay";
+   };
+
+   CPU_SLEEP_1: cpu-sleep-1 {
+   compatible = "arm,idle-state";
+   arm,psci-suspend-param = <0x001>;
+   local-timer-stop;
+   entry-latency-us = <700>;
+   exit-latency-us = <700>;
+   min-residency-us = <5000>;
+   status = 

[linux-yocto] [linux-yocto-dev]: [kernel standard/base]: renesas-rcar: arm64: dts: r8a7795: Add CPUIdle support for all CPU core

[Meng.Li]

From: Limeng 

Hi Bruce,

I get below patch from SDK kernel to support cpu idle feature, and intend to 
merge it into yocto community.

0001-arm64-dts-r8a7795-Add-CPUIdle-support-for-all-CPU-co.patch

Could you please merge this patch into linux-yocto-dev, branch is standard/base?

 r8a7795.dtsi |   32 
 1 file changed, 32 insertions(+)


thanks,
Limeng
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[linux-yocto] [linux-yocto-v5.2]: [kernel standard/base]: renesas-rcar: arm64: dts: r8a7795: Add CPUIdle support for all CPU core

[Meng.Li]

From: Limeng 

Hi Bruce,

I get below patch from SDK kernel to support cpu idle feature, and intend to 
merge it into yocto community.

0001-arm64-dts-r8a7795-Add-CPUIdle-support-for-all-CPU-co.patch

Could you please merge this patch into linux-yocto, branch is 
v5.2/standard/base?

 r8a7795.dtsi |   32 
 1 file changed, 32 insertions(+)


thanks,
Limeng
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[linux-yocto] [PATCH] arm64: dts: r8a7795: Add CPUIdle support for all CPU core

[Meng.Li]

From: Takeshi Kihara 

commit 3c3b44c752c4eef9a29694f4262934445c5f5da9 from
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas-bsp.git

This patch enables CPUIdle (Core shutdown) support for R-Car H3.

Signed-off-by: Takeshi Kihara 
Signed-off-by: Meng Li 
---
 arch/arm64/boot/dts/renesas/r8a7795.dtsi | 32 
 1 file changed, 32 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi 
b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index e8c3d5f..7fe7428 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -123,6 +123,7 @@
power-domains = < R8A7795_PD_CA57_CPU0>;
next-level-cache = <_CA57>;
enable-method = "psci";
+   cpu-idle-states = <_SLEEP_0>;
dynamic-power-coefficient = <854>;
clocks = < CPG_CORE R8A7795_CLK_Z>;
operating-points-v2 = <_opp>;
@@ -135,6 +136,7 @@
power-domains = < R8A7795_PD_CA57_CPU1>;
next-level-cache = <_CA57>;
enable-method = "psci";
+   cpu-idle-states = <_SLEEP_0>;
clocks = < CPG_CORE R8A7795_CLK_Z>;
operating-points-v2 = <_opp>;
capacity-dmips-mhz = <1024>;
@@ -147,6 +149,7 @@
power-domains = < R8A7795_PD_CA57_CPU2>;
next-level-cache = <_CA57>;
enable-method = "psci";
+   cpu-idle-states = <_SLEEP_0>;
clocks = < CPG_CORE R8A7795_CLK_Z>;
operating-points-v2 = <_opp>;
capacity-dmips-mhz = <1024>;
@@ -159,6 +162,7 @@
power-domains = < R8A7795_PD_CA57_CPU3>;
next-level-cache = <_CA57>;
enable-method = "psci";
+   cpu-idle-states = <_SLEEP_0>;
clocks = < CPG_CORE R8A7795_CLK_Z>;
operating-points-v2 = <_opp>;
capacity-dmips-mhz = <1024>;
@@ -171,6 +175,7 @@
power-domains = < R8A7795_PD_CA53_CPU0>;
next-level-cache = <_CA53>;
enable-method = "psci";
+   cpu-idle-states = <_SLEEP_1>;
#cooling-cells = <2>;
dynamic-power-coefficient = <277>;
clocks = < CPG_CORE R8A7795_CLK_Z2>;
@@ -182,6 +187,7 @@
power-domains = < R8A7795_PD_CA53_CPU1>;
next-level-cache = <_CA53>;
enable-method = "psci";
+   cpu-idle-states = <_SLEEP_1>;
clocks = < CPG_CORE R8A7795_CLK_Z2>;
operating-points-v2 = <_opp>;
capacity-dmips-mhz = <535>;
@@ -193,6 +199,7 @@
power-domains = < R8A7795_PD_CA53_CPU2>;
next-level-cache = <_CA53>;
enable-method = "psci";
+   cpu-idle-states = <_SLEEP_1>;
clocks = < CPG_CORE R8A7795_CLK_Z2>;
operating-points-v2 = <_opp>;
capacity-dmips-mhz = <535>;
@@ -204,6 +211,7 @@
power-domains = < R8A7795_PD_CA53_CPU3>;
next-level-cache = <_CA53>;
enable-method = "psci";
+   cpu-idle-states = <_SLEEP_1>;
clocks = < CPG_CORE R8A7795_CLK_Z2>;
operating-points-v2 = <_opp>;
capacity-dmips-mhz = <535>;
@@ -221,6 +229,30 @@
cache-unified;
cache-level = <2>;
};
+
+   idle-states {
+   entry-method = "psci";
+
+   CPU_SLEEP_0: cpu-sleep-0 {
+   compatible = "arm,idle-state";
+   arm,psci-suspend-param = <0x001>;
+   local-timer-stop;
+   entry-latency-us = <400>;
+   exit-latency-us = <500>;
+   min-residency-us = <4000>;
+   status = "okay";
+   };
+
+   CPU_SLEEP_1: cpu-sleep-1 {
+   compatible = "arm,idle-state";
+   arm,psci-suspend-param = <0x001>;
+   local-timer-stop;
+   entry-latency-us = <700>;
+   exit-latency-us = <700>;
+   min-residency-us = <5000>;
+   status = 

[linux-yocto] : [kernel v5.2/standard/bcm-2xxx-rpi]: bcm-2xxx-rpi: add patches for improving raspberrypi 4b platform

[Meng.Li]

From: Limeng 

Hi Bruce,

I am working on BSP bcm-2xxx-rpi platform, and intend to merge this BSP 
supporting into yocto community.
Some days ago, I submit a pull request for this BSP.
Now, there are still 81 below patches for improve this BSP

Could you please help to merge the 81 patches into linux-ycoto-5.2 kernel, 
branch v5.2/standard/bcm-2xxx-rpi?


The following changes since commit 69ce9ac46cd152ce73456e8cca5520e3cb0d6157:

  build/arm64: Add rules for .dtbo files for dts overlays (2019-09-16 14:50:55 
+0800)

are available in the Git repository at:

  https://github.com/limeng-linux/linux-yocto-5.2.git v5.2/standard/bcm-2xxx-rpi

for you to fetch changes up to 4b7ea76eac44bb3d07b53d24cbe578c47a074b93:

  arm64: dma-mapping: Fix IOMMU breakage (2019-09-17 18:49:42 +0800)


Aman Gupta (2):
  staging: bcm2835-codec: add support for 
V4L2_CID_MPEG_VIDEO_FORCE_KEY_FRAME
  staging: bcm2835-codec: remove unnecessary padding on encoder input

Chen-Yu Tsai (3):
  staging: bcm2835-codec: switch to multi-planar API
  staging: bcm2835-codec: implement V4L2_CID_MIN_BUFFERS_FOR_CAPTURE
  staging: bcm2835-codec: set device_caps in struct video_device

Dave Stevenson (24):
  staging: bcm2835_camera: Ensure all buffers are returned on disable
  drm/vc4: Query firmware for custom HDMI mode
  drm/vc4: Pass the drm vrefresh to the firmware on mode set
  drm/vc4: Add support for margins to fkms
  drm/vc4: Ensure zpos is always initialised
  drm/vc4: Add "Broadcast RGB" connector property
  drm/vc4: fkms: Set default state margin at reset
  drm/modes: Don't apply cmdline's rotation if it wasn't specified
  configs: Add CONFIG_FRAMEBUFFER_CONSOLE_ROTATION to Pi configs
  drm/vc4: Resolve the vblank warnings on mode switching
  drm/vc4: Remove unused mode variable
  staging:bcm2835-codec: Expand logging on format setting
  staging: bcm2835-codec: Correct bytesperline on format changed
  drm/vc4: Add missing NULL check to vc4_crtc_consume_event
  media: dt-bindings: Add binding for the Sony IMX219 sensor
  media: i2c: Add driver for Sony IMX219 sensor
  defconfigs: Add Sony IMX219 driver to RPi defconfigs
  dtoverlays: Add overlay for the Sony IMX219 image sensor.
  overlays: mcp23017: rename the GPIO pins node with the device
  overlays: mcp23017: Add option for not connecting the int GPIO
  v4l2: Add a Greyworld AWB mode.
  staging: bcm2835-camera: Add greyworld AWB mode
  staging: bcm2835-codec: Allow height of 1920.
  staging: bcm2835-codec: Correct g/s_selection API MPLANE support

James Hughes (3):
  Fixup FKMS interrupt handing for non-existent display
  Add HDMI1 facility to the driver.
  drm/vc4: Fix for margins in composite/SDTV mode (#3223)

Joerg Schambacher (1):
  adds the Hifiberry DAC+ADC PRO version

Jonathan Bell (3):
  dts: bcm2838: add missing properties for pmu and gic nodes
  hid: usb: Add device quirks for Freeway Airmouse T3 and MX3
  xhci: Use more event ring segment table entries

Jörg Schambacher (1):
  Add Hifiberry DAC+DSP soundcard driver (#3224)

Kieran Bingham (7):
  staging: bcm2835-codec: Fix non-documentation comment block
  staging: bcm2835-codec: Fix declaration of roles
  staging: bcm2835-codec: Add role to device name
  staging: bcm2835-codec: Pass driver context to create entities
  staging: bcm2835-codec: add media controller support
  media: bcm2835: unicam: Reduce scope of local function
  media: bcm2835: unicam: add media controller support

Maxime Ripard (8):
  drm/connector: Add documentation for drm_cmdline_mode
  drm/modes: Rewrite the command line parser
  drm/modes: Support modes names on the command line
  drm/modes: Allow to specify rotation and reflection on the commandline
  drm/connector: Introduce a TV margins structure
  drm/modes: Parse overscan properties
  drm/atomic: Add a function to reset connector TV properties
  drm/vc4: hdmi: Set default state margin at reset

P33M (1):
  dwc_otg: use align_buf for small IN control transfers (#3150)

Phil Elwell (20):
  overlays: audremap: Support GPIOs 18 & 19
  drm/vc4: A present but empty dmas disables audio
  overlays: Add audio parameter to vc4-kms-v3d
  overlays: Update the upstream overlay
  can: mcp251x: Allow more time after a reset
  drivers: char: Use correct name for the Raspberry Pi video decoder
  driver: char: rpivid - also support legacy name
  overlays: Add baudrate parameter to i2c3-i2c6
  net: bcmgenet: Workaround #2 for Pi4 Ethernet fail
  configs: Regenerate the defconfigs
  configs: Enable building the DS28E17 driver module
  ARM: dts: bcm2711-rpi-4-b: I2C aliases and pulls
  configs: arm64/vcm2711: Enable V3D
  overlays: sc16ic752-i2c: Fix xtal parameter
  arch/arm: Add 

[linux-yocto] : [kernel-cache master/yocto-5.2]: bcm-2xxx-rpi: add configure file for bcm-2xxx-rpi BSP in kernel-cache

[Meng.Li]

From: Limeng 

Hi Bruce,

I am working on BSP bcm-2xxx-rpi platform, and intend to merge this BSP 
supporting into yocto community.
Below patch includes scc and cfg files for Raspberrypi 4b platform.

Could you please merge this patch into yocto-kernel-cache, branch is master and 
yocto-5.2?

0001-bcm-2xxx-rpi-add-configure-file-for-bcm-2xxx-rpi-BSP.patch

 bcm-2xxx-rpi.cfg |  268 +++
 bcm-2xxx-rpi.scc |   13 ++
 bcm-2xxx-rpi4-preempt-rt.scc |8 +
 bcm-2xxx-rpi4-standard.scc   |9 +
 4 files changed, 298 insertions(+)


thanks,
Limeng
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[linux-yocto] [PATCH] bcm-2xxx-rpi: add configure file for bcm-2xxx-rpi BSP in kernel-cache

[Meng.Li]

From: Limeng 

Signed-off-by: Meng Li 
---
 bsp/bcm-2xxx-rpi/bcm-2xxx-rpi.cfg | 268 ++
 bsp/bcm-2xxx-rpi/bcm-2xxx-rpi.scc |  13 +
 bsp/bcm-2xxx-rpi/bcm-2xxx-rpi4-preempt-rt.scc |   8 +
 bsp/bcm-2xxx-rpi/bcm-2xxx-rpi4-standard.scc   |   9 +
 4 files changed, 298 insertions(+)
 create mode 100755 bsp/bcm-2xxx-rpi/bcm-2xxx-rpi.cfg
 create mode 100755 bsp/bcm-2xxx-rpi/bcm-2xxx-rpi.scc
 create mode 100755 bsp/bcm-2xxx-rpi/bcm-2xxx-rpi4-preempt-rt.scc
 create mode 100755 bsp/bcm-2xxx-rpi/bcm-2xxx-rpi4-standard.scc

diff --git a/bsp/bcm-2xxx-rpi/bcm-2xxx-rpi.cfg 
b/bsp/bcm-2xxx-rpi/bcm-2xxx-rpi.cfg
new file mode 100755
index ..6cbf3ba8
--- /dev/null
+++ b/bsp/bcm-2xxx-rpi/bcm-2xxx-rpi.cfg
@@ -0,0 +1,268 @@
+..
+.WARNING
+.
+. This file is a kernel configuration fragment, and not a full kernel
+. configuration file.  The final kernel configuration is made up of
+. an assembly of processed fragments, each of which is designed to
+. capture a specific part of the final configuration (e.g. platform
+. configuration, feature configuration, and board specific hardware
+. configuration).  For more information on kernel configuration, please
+. consult the product documentation.
+.
+..
+
+# System Type
+CONFIG_MMU=y
+CONFIG_ARM64=y
+
+# CPU Core family selection
+CONFIG_ARCH_BCM2835=y
+CONFIG_MAILBOX=y
+CONFIG_BCM2835_MBOX=y
+CONFIG_RASPBERRYPI_FIRMWARE=y
+
+# Bus support
+
+# Kernel Features
+CONFIG_SMP=y
+CONFIG_NR_CPUS=4
+
+# CPU Idle
+# CONFIG_ATAGS is not set
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_MENU=y
+CONFIG_ARM_CPUIDLE=y
+
+# MTD devices
+CONFIG_MTD=y
+CONFIG_MTD_BLOCK=m
+
+# Ethernet devices
+CONFIG_NET=y
+CONFIG_BCMGENET=y
+
+# Serial drivers
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=1
+CONFIG_SERIAL_8250_RUNTIME_UARTS=1
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_8250_BCM2835AUX=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+CONFIG_SERIAL_SC16IS7XX=m
+CONFIG_SERIAL_SC16IS7XX_SPI=y
+CONFIG_SERIAL_DEV_BUS=y
+
+# I2C device
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=m
+CONFIG_I2C_BCM2708=m
+CONFIG_I2C_BCM2835=m
+CONFIG_I2C_GPIO=m
+CONFIG_EEPROM_AT24=m
+
+# SPI device
+CONFIG_SPI=y
+CONFIG_SPI_BCM2835=m
+CONFIG_SPI_BCM2835AUX=m
+CONFIG_SPI_SPIDEV=y
+
+# Graphics support
+CONFIG_FB=y
+CONFIG_FB_BCM2708=y
+CONFIG_FB_UDL=m
+CONFIG_FB_SSD1307=m
+CONFIG_FB_RPISENSE=m
+
+CONFIG_BCM_VCIO=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_DRM=m
+CONFIG_DRM_LOAD_EDID_FIRMWARE=y
+CONFIG_DRM_UDL=m
+CONFIG_DRM_VC4=m
+
+#PCIe Bus support
+CONFIG_PCI=y
+CONFIG_PCIE_BRCMSTB=y
+
+# USB support
+CONFIG_USB=y
+CONFIG_USB_USBNET=y
+CONFIG_USB_NET_SMSC95XX=y
+CONFIG_USB_ALI_M5632=y
+CONFIG_USB_AN2720=y
+CONFIG_USB_EPSON2888=y
+CONFIG_USB_KC2190=y
+CONFIG_INPUT_MISC=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_LAN78XX=y
+CONFIG_USB_DWCOTG=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_PCI=y
+
+#Media support
+CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
+CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
+CONFIG_MEDIA_RADIO_SUPPORT=y
+CONFIG_MEDIA_CONTROLLER=y
+CONFIG_MEDIA_SUPPORT=m
+CONFIG_MEDIA_USB_SUPPORT=y
+CCONFIG_USB_VIDEO_CLASS=m
+CONFIG_VIDEO_V4L2=m
+CONFIG_VIDEO_EM28XX=m
+CONFIG_VIDEO_EM28XX_V4L2=m
+CONFIG_VIDEO_EM28XX_ALSA=m
+CONFIG_VIDEO_EM28XX_DVB=m
+CONFIG_VIDEO_BCM2835=m
+CONFIG_V4L_PLATFORM_DRIVERS=y
+
+# Thermal configuration
+CONFIG_THERMAL=y
+CONFIG_BCM2835_THERMAL=y
+
+# MMC/SD/SDIO Card Drivers
+CONFIG_MMC=y
+CONFIG_MMC_BLOCK_MINORS=32
+CONFIG_MMC_BCM2835_MMC=y
+CONFIG_MMC_BCM2835_DMA=y
+CONFIG_MMC_BCM2835_SDHOST=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SPI=m
+CONFIG_MMC_SDHCI_IPROC=y
+
+# DMA Devices
+CONFIG_DMA_SHARED_BUFFER=y
+CONFIG_CMA=y
+CONFIG_DMADEVICES=y
+CONFIG_DMA_BCM2835=y
+CONFIG_DMA_BCM2708=y
+CONFIG_DMA_CMA=y
+
+# PWM support
+CONFIG_PWM=y
+CONFIG_PWM_BCM2835=m
+CONFIG_PWM_PCA9685=m
+
+# Watchdog timer support
+CONFIG_WATCHDOG=y
+CONFIG_BCM2835_WDT=y
+
+# Sound card support
+CONFIG_SOUND=y
+CONFIG_SND=m
+CONFIG_SND_SOC=m
+CONFIG_SND_BCM2835_SOC_I2S=m
+CONFIG_SND_MPU401=m
+CONFIG_SND_SEQUENCER=m
+CONFIG_SND_HRTIMER=m
+CONFIG_SND_DUMMY=m
+CONFIG_SND_ALOOP=m
+CONFIG_SND_VIRMIDI=m
+CONFIG_SND_MTPAV=m
+CONFIG_SND_SEQ_DUMMY=m
+CONFIG_SND_HWDEP=m
+CONFIG_SND_USB_AUDIO=m
+CONFIG_SND_USB_UA101=m
+CONFIG_SND_USB_CAIAQ=m
+CONFIG_SND_USB_CAIAQ_INPUT=y
+CONFIG_SND_USB_6FIRE=m
+CONFIG_SND_BCM2708_SOC_GOOGLEVOICEHAT_SOUNDCARD=m
+CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC=m
+CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS=m

[linux-yocto] [PATCH 3/4] driver: net: can: disable clock when it is in enable status

[Meng.Li]

From: Limeng 

If disable a clock when it is already in disable status, there
will be a warning trace generated. So, it is need to confirm
whether what status the clock is in before disable it.

Signed-off-by: Meng Li 
---
 drivers/net/can/rcar/rcar_can.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/net/can/rcar/rcar_can.c b/drivers/net/can/rcar/rcar_can.c
index 13e66297b65f..f788b826e4aa 100644
--- a/drivers/net/can/rcar/rcar_can.c
+++ b/drivers/net/can/rcar/rcar_can.c
@@ -15,6 +15,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 
@@ -864,7 +865,9 @@ static int __maybe_unused rcar_can_suspend(struct device 
*dev)
writew(ctlr, >regs->ctlr);
priv->can.state = CAN_STATE_SLEEPING;
 
-   clk_disable(priv->clk);
+   if(__clk_is_enabled(priv->clk))
+   clk_disable(priv->clk);
+
return 0;
 }
 
-- 
2.18.1

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[linux-yocto] [PATCH 4/4] pci: pcie-rcar: add regulators support

[Meng.Li]

From: Andrey Gusakov 

Add PCIe regulators for KingFisher board.

Signed-off-by: Meng Li 
---
 arch/arm64/boot/dts/renesas/ulcb-kf.dtsi | 47 +
 drivers/pci/controller/pcie-rcar.c   | 64 
 2 files changed, 111 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi 
b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
index a1e70b52727b..e8d431028fc7 100644
--- a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
+++ b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
@@ -50,6 +50,25 @@
startup-delay-us = <7>;
enable-active-high;
};
+
+   mpcie_3v3: regulator-mpcie_3v3 {
+   compatible = "regulator-fixed";
+   regulator-name = "mPCIe 3v3";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   gpio = <_exp_77 14 GPIO_ACTIVE_HIGH>;
+   enable-active-high;
+   };
+
+   mpcie_1v8: regulator-mpcie_1v8 {
+   compatible = "regulator-fixed";
+   regulator-name = "mPCIe 1v8";
+   regulator-min-microvolt = <180>;
+   regulator-max-microvolt = <180>;
+   gpio = <_exp_77 15 GPIO_ACTIVE_HIGH>;
+   startup-delay-us = <20>;
+   enable-active-high;
+   };
 };
 
  {
@@ -233,6 +252,31 @@
interrupt-controller;
interrupt-parent = <>;
interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
+
+   mpcie_wake {
+   gpio-hog;
+   gpios = <0 GPIO_ACTIVE_HIGH>;
+   output-low;
+   line-name = "mPCIe WAKE#";
+   };
+   mpcie_wdisable {
+   gpio-hog;
+   gpios = <1 GPIO_ACTIVE_HIGH>;
+   output-high;
+   line-name = "mPCIe W_DISABLE";
+   };
+   mpcie_clreq {
+   gpio-hog;
+   gpios = <2 GPIO_ACTIVE_HIGH>;
+   input;
+   line-name = "mPCIe CLKREQ#";
+   };
+   mpcie_ovc {
+   gpio-hog;
+   gpios = <3 GPIO_ACTIVE_HIGH>;
+   input;
+   line-name = "mPCIe OVC";
+   };
};
 
i2cswitch4: i2c-switch@71 {
@@ -259,6 +303,9 @@
 
  {
status = "okay";
+
+   pcie3v3-supply = <_3v3>;
+   pcie1v8-supply = <_1v8>;
 };
 
  {
diff --git a/drivers/pci/controller/pcie-rcar.c 
b/drivers/pci/controller/pcie-rcar.c
index f6a669a9af41..8e7e714e33fd 100644
--- a/drivers/pci/controller/pcie-rcar.c
+++ b/drivers/pci/controller/pcie-rcar.c
@@ -14,6 +14,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -151,6 +152,8 @@ struct rcar_pcie {
struct list_headresources;
int root_bus_nr;
struct clk  *bus_clk;
+   struct regulator*pcie3v3; /* 3.3V power supply */
+   struct regulator*pcie1v8; /* 1.8V power supply */
struct  rcar_msi msi;
 };
 
@@ -1120,6 +1123,36 @@ static const struct of_device_id rcar_pcie_of_match[] = {
{},
 };
 
+static int rcar_pcie_set_vpcie(struct rcar_pcie *pcie)
+{
+   struct device *dev = pcie->dev;
+   int err;
+
+   if (!IS_ERR(pcie->pcie3v3)) {
+   err = regulator_enable(pcie->pcie3v3);
+   if (err) {
+   dev_err(dev, "fail to enable vpcie3v3 regulator\n");
+   goto err_out;
+   }
+   }
+
+   if (!IS_ERR(pcie->pcie1v8)) {
+   err = regulator_enable(pcie->pcie1v8);
+   if (err) {
+   dev_err(dev, "fail to enable vpcie1v8 regulator\n");
+   goto err_disable_3v3;
+   }
+   }
+
+   return 0;
+
+err_disable_3v3:
+   if (!IS_ERR(pcie->pcie3v3))
+   regulator_disable(pcie->pcie3v3);
+err_out:
+   return err;
+}
+
 static int rcar_pcie_probe(struct platform_device *pdev)
 {
struct device *dev = >dev;
@@ -1138,6 +1171,31 @@ static int rcar_pcie_probe(struct platform_device *pdev)
pcie->dev = dev;
platform_set_drvdata(pdev, pcie);
 
+   pcie->pcie3v3 = devm_regulator_get_optional(dev, "pcie3v3");
+   if (IS_ERR(pcie->pcie3v3)) {
+   if (PTR_ERR(pcie->pcie3v3) == -EPROBE_DEFER) {
+   pci_free_host_bridge(bridge);
+   return -EPROBE_DEFER;
+   }
+   dev_info(dev, "no pcie3v3 regulator found\n");
+   }
+
+   pcie->pcie1v8 = devm_regulator_get_optional(dev, "pcie1v8");
+   if (IS_ERR(pcie->pcie1v8)) {
+   if (PTR_ERR(pcie->pcie1v8) == -EPROBE_DEFER) {
+   pci_free_host_bridge(bridge);
+

[linux-yocto] [linux-yocto-v5.2]: [kernel standard/base]: renesas-rcar: add some patches to improve features on renesas-rcar platform

[Meng.Li]

From: Limeng 

Hi Bruce,

I am working on BSP renesas-rcar platform, and intend to merge this BSP 
supporting into yocto community.
Below 4 patches are used to improve gpio, CAN BUS, audio and PCIe features
This first patch is from mainline upstream, the other 3 patches merged into 
linux-yocto-dev(standard/base) some days ago.

0001-arm64-dts-renesas-ulcb-kf-Add-support-for-TI-WL1837.patch
0002-arch-arm64-dts-Set-gpio5-pin9-as-input-by-default.patch
0003-driver-net-can-disable-clock-when-it-is-in-enable-st.patch
0004-pci-pcie-rcar-add-regulators-support.patch

Could you please merge the 4 patches into linux-yocto, branch is 
v5.2/standard/base?

 arch/arm64/boot/dts/renesas/ulcb-kf.dtsi |  105 +++
 drivers/net/can/rcar/rcar_can.c  |5 +
 drivers/pci/controller/pcie-rcar.c   |   64 ++
 3 files changed, 173 insertions(+), 1 deletion(-)


thanks,
Limeng
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[linux-yocto] [PATCH 2/4] arch: arm64: dts: Set gpio5-pin9 as input by default

[Meng.Li]

From: Limeng 

The gpio5-pin9 is used as the interrupt pin of i2c external
gpio chip, so set this pin as input by default.

Signed-off-by: Meng Li 
---
 arch/arm64/boot/dts/renesas/ulcb-kf.dtsi | 9 +
 1 file changed, 9 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi 
b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
index 27851a77f538..a1e70b52727b 100644
--- a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
+++ b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
@@ -205,6 +205,15 @@
};
 };
 
+ {
+   gpio_exp_77_int {
+   gpio-hog;
+   gpios = <9 0>;
+   input;
+   line-name = "gpio-exp-77-int";
+   };
+};
+
  {
gpio_exp_76: gpio@76 {
compatible = "ti,tca9539";
-- 
2.18.1

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[linux-yocto] [PATCH 1/4] arm64: dts: renesas: ulcb-kf: Add support for TI WL1837

[Meng.Li]

From: Spyridon Papageorgiou 

commit 95ff4aab4173fce010832756b8bea3a7cba3238d from upstream

This patch adds description of TI WL1837 and links interfaces
to communicate with the IC, namely the SDIO interface to WLAN.

Signed-off-by: Spyridon Papageorgiou 
Signed-off-by: Simon Horman 
Signed-off-by: Meng Li 
---
 arch/arm64/boot/dts/renesas/ulcb-kf.dtsi | 49 
 1 file changed, 49 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi 
b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
index 7a09576b3112..27851a77f538 100644
--- a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
+++ b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
@@ -38,6 +38,18 @@
regulator-min-microvolt = <500>;
regulator-max-microvolt = <500>;
};
+
+   wlan_en: regulator-wlan_en {
+   compatible = "regulator-fixed";
+   regulator-name = "wlan-en-regulator";
+
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+
+   gpio = <_exp_74 4 GPIO_ACTIVE_HIGH>;
+   startup-delay-us = <7>;
+   enable-active-high;
+   };
 };
 
  {
@@ -88,6 +100,13 @@
line-name = "Audio_Out_OFF";
};
 
+   sd-wifi-mux {
+   gpio-hog;
+   gpios = <5 GPIO_ACTIVE_HIGH>;
+   output-low; /* Connect WL1837 */
+   line-name = "SD WiFi mux";
+   };
+
hub_pwen {
gpio-hog;
gpios = <6 GPIO_ACTIVE_HIGH>;
@@ -254,6 +273,12 @@
function = "scif1";
};
 
+   sdhi3_pins: sdhi3 {
+   groups = "sdhi3_data4", "sdhi3_ctrl";
+   function = "sdhi3";
+   power-source = <3300>;
+   };
+
usb0_pins: usb0 {
groups = "usb0";
function = "usb0";
@@ -273,6 +298,30 @@
status = "okay";
 };
 
+ {
+   pinctrl-0 = <_pins>;
+   pinctrl-names = "default";
+
+   vmmc-supply = <_en>;
+   vqmmc-supply = <_en>;
+   bus-width = <4>;
+   no-1-8-v;
+   non-removable;
+   cap-power-off-card;
+   keep-power-in-suspend;
+   max-frequency = <2600>;
+   status = "okay";
+
+   #address-cells = <1>;
+   #size-cells = <0>;
+   wlcore: wlcore@2 {
+   compatible = "ti,wl1837";
+   reg = <2>;
+   interrupt-parent = <>;
+   interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
+   };
+};
+
 _phy0 {
pinctrl-0 = <_pins>;
pinctrl-names = "default";
-- 
2.18.1

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[linux-yocto] [PATCH] renesas-rcar: add configure file for renesas BSP in kernel-cache

[Meng.Li]

From: Limeng 

Signed-off-by: Meng Li 
---
 bsp/renesas-rcar/renesas-rcar-h3-standard.scc |   7 +
 bsp/renesas-rcar/renesas-rcar-m3-standard.scc |   7 +
 bsp/renesas-rcar/renesas-rcar.cfg | 252 ++
 bsp/renesas-rcar/renesas-rcar.scc |   8 +
 4 files changed, 274 insertions(+)
 create mode 100644 bsp/renesas-rcar/renesas-rcar-h3-standard.scc
 create mode 100644 bsp/renesas-rcar/renesas-rcar-m3-standard.scc
 create mode 100644 bsp/renesas-rcar/renesas-rcar.cfg
 create mode 100644 bsp/renesas-rcar/renesas-rcar.scc

diff --git a/bsp/renesas-rcar/renesas-rcar-h3-standard.scc 
b/bsp/renesas-rcar/renesas-rcar-h3-standard.scc
new file mode 100644
index ..b01b4305
--- /dev/null
+++ b/bsp/renesas-rcar/renesas-rcar-h3-standard.scc
@@ -0,0 +1,7 @@
+define KMACHINE renesas-rcar-h3
+define KTYPE standard
+define KARCH arm64
+
+include ktypes/standard
+
+include renesas-rcar.scc
diff --git a/bsp/renesas-rcar/renesas-rcar-m3-standard.scc 
b/bsp/renesas-rcar/renesas-rcar-m3-standard.scc
new file mode 100644
index ..033c8ba6
--- /dev/null
+++ b/bsp/renesas-rcar/renesas-rcar-m3-standard.scc
@@ -0,0 +1,7 @@
+define KMACHINE renesas-rcar-m3
+define KTYPE standard
+define KARCH arm64
+
+include ktypes/standard
+
+include renesas-rcar.scc
diff --git a/bsp/renesas-rcar/renesas-rcar.cfg 
b/bsp/renesas-rcar/renesas-rcar.cfg
new file mode 100644
index ..cc896276
--- /dev/null
+++ b/bsp/renesas-rcar/renesas-rcar.cfg
@@ -0,0 +1,252 @@
+#.
+#WARNING
+#
+# This file is a kernel configuration fragment, and not a full kernel
+# configuration file.  The final kernel configuration is made up of
+# an assembly of processed fragments, each of which is designed to
+# capture a specific part of the final configuration (e.g. platform
+# configuration, feature configuration, and board specific hardware
+# configuration).  For more information on kernel configuration, please
+# consult the product documentation.
+#
+#.
+
+CONFIG_ARM64=y
+CONFIG_64BIT=y
+CONFIG_SMP=y
+
+# Platform selection
+CONFIG_ARCH_RENESAS=y
+CONFIG_ARCH_R8A7795=y
+CONFIG_ARCH_R8A7796=y
+CONFIG_ARM64_4K_PAGES=y
+CONFIG_ARM64_VA_BITS_48=y
+CONFIG_ARM64_VA_BITS=48
+CONFIG_NR_CPUS=8
+
+# CPU Idle
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_MENU=y
+CONFIG_DT_IDLE_STATES=y
+CONFIG_ARM_CPUIDLE=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPUFREQ_DT=y
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+
+# Networking options
+CONFIG_NET=y
+CONFIG_NET_INGRESS=y
+CONFIG_RAVB=y
+
+# Serial Congifuration
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_SERIAL_DEV_BUS=y
+CONFIG_SERIAL_SH_SCI=y
+CONFIG_SERIAL_SH_SCI_NR_UARTS=18
+CONFIG_SERIAL_SH_SCI_CONSOLE=y
+CONFIG_SERIAL_SH_SCI_EARLYCON=y
+CONFIG_SERIAL_SH_SCI_DMA=y
+
+# Spi configuration
+CONFIG_SPI=y
+CONFIG_SPI_SH_MSIOF=y
+CONFIG_SPI_GPIO=y
+
+# Pinctrl configuration
+CONFIG_PINMUX=y
+CONFIG_PINCONF=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_PINCTRL_SH_PFC=y
+CONFIG_PINCTRL_PFC_R8A7795=y
+CONFIG_PINCTRL_PFC_R8A7796=y
+
+# Watchdog configuration
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_RENESAS_WDT=y
+
+# Drm configuration
+CONFIG_DRM=y
+CONFIG_DRM_RCAR_DU=y
+CONFIG_DRM_RCAR_DW_HDMI=y
+CONFIG_DRM_RCAR_LVDS=y
+CONFIG_DRM_RCAR_VSP=y
+CONFIG_DRM_I2C_ADV7533=y
+CONFIG_DRM_I2C_ADV7511=y
+CONFIG_DRM_I2C_ADV7511_CEC=y
+CONFIG_DRM_DW_HDMI=y
+CONFIG_DRM_DUMB_VGA_DAC=y
+CONFIG_DRM_THINE_THC63LVD1024=y
+CONFIG_DRM_PANEL_LVDS=y
+CONFIG_DRM_DW_HDMI_I2S_AUDIO=y
+
+# LCD Backlight configuration
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+
+# Sound configuration
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_RCAR=y
+CONFIG_SND_SOC_AK4613=y
+CONFIG_SND_SOC_HDMI_CODEC=y
+CONFIG_SND_SIMPLE_CARD=y
+CONFIG_SND_AUDIO_GRAPH_CARD=y
+CONFIG_SND_SOC_PCM3168A_I2C=y
+
+# Clock configuration
+CONFIG_COMMON_CLK=y
+CONFIG_COMMON_CLK_CS2000_CP=y
+CONFIG_COMMON_CLK_VC5=y
+
+# USB configuration
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_XHCI_HCD=m
+CONFIG_USB_XHCI_RCAR=m
+CONFIG_USB_XHCI_PLATFORM=m
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+CONFIG_USB_OTG=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PCI=y
+CONFIG_USB_OHCI_HCD_PLATFORM=y
+CONFIG_USB_RENESAS_USBHS=y
+CONFIG_USB_RENESAS_USBHS_UDC=y
+CONFIG_USB_RENESAS_USB3=m
+CONFIG_USB_DWC3=y
+CONFIG_GENERIC_PHY=y
+CONFIG_PHY_RCAR_GEN3_USB2=y
+CONFIG_PHY_RCAR_GEN3_USB3=y
+
+# PWM configuration
+CONFIG_PWM=y
+CONFIG_PWM_SYSFS=y
+CONFIG_PWM_RCAR=y
+
+# PCIe configuration
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DOMAINS_GENERIC=y
+CONFIG_PCIE_RCAR=y
+CONFIG_PCI_MSI=y
+CONFIG_PCIEPORTBUS=y
+
+# Sata configuration
+CONFIG_ATA=y
+CONFIG_SATA_AHCI=y
+CONFIG_SATA_AHCI_PLATFORM=y
+CONFIG_SATA_RCAR=y
+
+# I2C configuration
+CONFIG_I2C=y
+CONFIG_I2C_RCAR=y

[linux-yocto] : [kernel-cache yocto-5.2]: renesas-rcar: add configure file for renesas BSP in kernel-cache

[Meng.Li]

From: Limeng 

Hi Bruce,

I am working on BSP renesas-rcar platform, and intend to merge this BSP 
supporting into yocto community.
Below patch includes scc and cfg files for renesas-rcar platform.

Could you please merge this patch into yocto-kernel-cache, branch is yocto-5.2?
This patch was merged into master some days ago. It also need to be merged into 
yocto-5.2 branch

0001-renesas-rcar-add-configure-file-for-renesas-BSP-in-k.patch

 renesas-rcar-h3-standard.scc |7 +
 renesas-rcar-m3-standard.scc |7 +
 renesas-rcar.cfg |  252 +++
 renesas-rcar.scc |8 +
 4 files changed, 274 insertions(+)


thanks,
Limeng
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[linux-yocto] [PATCH 3/3] pci: pcie-rcar: add regulators support

[Meng.Li]

From: Andrey Gusakov 

Add PCIe regulators for KingFisher board.

Signed-off-by: Meng Li 
---
 arch/arm64/boot/dts/renesas/ulcb-kf.dtsi | 47 +
 drivers/pci/controller/pcie-rcar.c   | 64 
 2 files changed, 111 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi 
b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
index a1e70b52727b..e8d431028fc7 100644
--- a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
+++ b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
@@ -50,6 +50,25 @@
startup-delay-us = <7>;
enable-active-high;
};
+
+   mpcie_3v3: regulator-mpcie_3v3 {
+   compatible = "regulator-fixed";
+   regulator-name = "mPCIe 3v3";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   gpio = <_exp_77 14 GPIO_ACTIVE_HIGH>;
+   enable-active-high;
+   };
+
+   mpcie_1v8: regulator-mpcie_1v8 {
+   compatible = "regulator-fixed";
+   regulator-name = "mPCIe 1v8";
+   regulator-min-microvolt = <180>;
+   regulator-max-microvolt = <180>;
+   gpio = <_exp_77 15 GPIO_ACTIVE_HIGH>;
+   startup-delay-us = <20>;
+   enable-active-high;
+   };
 };
 
  {
@@ -233,6 +252,31 @@
interrupt-controller;
interrupt-parent = <>;
interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
+
+   mpcie_wake {
+   gpio-hog;
+   gpios = <0 GPIO_ACTIVE_HIGH>;
+   output-low;
+   line-name = "mPCIe WAKE#";
+   };
+   mpcie_wdisable {
+   gpio-hog;
+   gpios = <1 GPIO_ACTIVE_HIGH>;
+   output-high;
+   line-name = "mPCIe W_DISABLE";
+   };
+   mpcie_clreq {
+   gpio-hog;
+   gpios = <2 GPIO_ACTIVE_HIGH>;
+   input;
+   line-name = "mPCIe CLKREQ#";
+   };
+   mpcie_ovc {
+   gpio-hog;
+   gpios = <3 GPIO_ACTIVE_HIGH>;
+   input;
+   line-name = "mPCIe OVC";
+   };
};
 
i2cswitch4: i2c-switch@71 {
@@ -259,6 +303,9 @@
 
  {
status = "okay";
+
+   pcie3v3-supply = <_3v3>;
+   pcie1v8-supply = <_1v8>;
 };
 
  {
diff --git a/drivers/pci/controller/pcie-rcar.c 
b/drivers/pci/controller/pcie-rcar.c
index f6a669a9af41..8e7e714e33fd 100644
--- a/drivers/pci/controller/pcie-rcar.c
+++ b/drivers/pci/controller/pcie-rcar.c
@@ -14,6 +14,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -151,6 +152,8 @@ struct rcar_pcie {
struct list_headresources;
int root_bus_nr;
struct clk  *bus_clk;
+   struct regulator*pcie3v3; /* 3.3V power supply */
+   struct regulator*pcie1v8; /* 1.8V power supply */
struct  rcar_msi msi;
 };
 
@@ -1120,6 +1123,36 @@ static const struct of_device_id rcar_pcie_of_match[] = {
{},
 };
 
+static int rcar_pcie_set_vpcie(struct rcar_pcie *pcie)
+{
+   struct device *dev = pcie->dev;
+   int err;
+
+   if (!IS_ERR(pcie->pcie3v3)) {
+   err = regulator_enable(pcie->pcie3v3);
+   if (err) {
+   dev_err(dev, "fail to enable vpcie3v3 regulator\n");
+   goto err_out;
+   }
+   }
+
+   if (!IS_ERR(pcie->pcie1v8)) {
+   err = regulator_enable(pcie->pcie1v8);
+   if (err) {
+   dev_err(dev, "fail to enable vpcie1v8 regulator\n");
+   goto err_disable_3v3;
+   }
+   }
+
+   return 0;
+
+err_disable_3v3:
+   if (!IS_ERR(pcie->pcie3v3))
+   regulator_disable(pcie->pcie3v3);
+err_out:
+   return err;
+}
+
 static int rcar_pcie_probe(struct platform_device *pdev)
 {
struct device *dev = >dev;
@@ -1138,6 +1171,31 @@ static int rcar_pcie_probe(struct platform_device *pdev)
pcie->dev = dev;
platform_set_drvdata(pdev, pcie);
 
+   pcie->pcie3v3 = devm_regulator_get_optional(dev, "pcie3v3");
+   if (IS_ERR(pcie->pcie3v3)) {
+   if (PTR_ERR(pcie->pcie3v3) == -EPROBE_DEFER) {
+   pci_free_host_bridge(bridge);
+   return -EPROBE_DEFER;
+   }
+   dev_info(dev, "no pcie3v3 regulator found\n");
+   }
+
+   pcie->pcie1v8 = devm_regulator_get_optional(dev, "pcie1v8");
+   if (IS_ERR(pcie->pcie1v8)) {
+   if (PTR_ERR(pcie->pcie1v8) == -EPROBE_DEFER) {
+   pci_free_host_bridge(bridge);
+

[linux-yocto] [PATCH 2/3] driver: net: can: disable clock when it is in enable status

[Meng.Li]

From: Limeng 

If disable a clock when it is already in disable status, there
will be a warning trace generated. So, it is need to confirm
whether what status the clock is in before disable it.

Signed-off-by: Meng Li 
---
 drivers/net/can/rcar/rcar_can.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/net/can/rcar/rcar_can.c b/drivers/net/can/rcar/rcar_can.c
index 13e66297b65f..f788b826e4aa 100644
--- a/drivers/net/can/rcar/rcar_can.c
+++ b/drivers/net/can/rcar/rcar_can.c
@@ -15,6 +15,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 
@@ -864,7 +865,9 @@ static int __maybe_unused rcar_can_suspend(struct device 
*dev)
writew(ctlr, >regs->ctlr);
priv->can.state = CAN_STATE_SLEEPING;
 
-   clk_disable(priv->clk);
+   if(__clk_is_enabled(priv->clk))
+   clk_disable(priv->clk);
+
return 0;
 }
 
-- 
2.17.1

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[linux-yocto] [linux-yocto-dev]: [kernel standard/base]: renesas-rcar: add some patches to improve features on renesas-rcar platform

[Meng.Li]

From: Limeng 

Hi Bruce,

I am working on BSP renesas-rcar platform, and intend to merge this BSP 
supporting into yocto community.
Below 3 patches are used to improve gpio, CAN BUS, audio and PCIe features

0001-arch-arm64-dts-Set-gpio5-pin9-as-input-by-default.patch
0002-driver-net-can-disable-clock-when-it-is-in-enable-st.patch
0003-pci-pcie-rcar-add-regulators-support.patch

Could you please merge the 3 patches into linux-yocto-dev, branch is 
standard/base?

 arch/arm64/boot/dts/renesas/ulcb-kf.dtsi |   56 +++
 drivers/net/can/rcar/rcar_can.c  |5 +-
 drivers/pci/controller/pcie-rcar.c   |   64 +++
 3 files changed, 124 insertions(+), 1 deletion(-)


thanks,
Limeng
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[linux-yocto] [PATCH 1/3] arch: arm64: dts: Set gpio5-pin9 as input by default

[Meng.Li]

From: Limeng 

The gpio5-pin9 is used as the interrupt pin of i2c external
gpio chip, so set this pin as input by default.

Signed-off-by: Meng Li 
---
 arch/arm64/boot/dts/renesas/ulcb-kf.dtsi | 9 +
 1 file changed, 9 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi 
b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
index 27851a77f538..a1e70b52727b 100644
--- a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
+++ b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
@@ -205,6 +205,15 @@
};
 };
 
+ {
+   gpio_exp_77_int {
+   gpio-hog;
+   gpios = <9 0>;
+   input;
+   line-name = "gpio-exp-77-int";
+   };
+};
+
  {
gpio_exp_76: gpio@76 {
compatible = "ti,tca9539";
-- 
2.17.1

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[linux-yocto] [PATCH] renesas-rcar: enable PCM3168A-I2C codec drvier

[Meng.Li]

From: Limeng 

On KingFisher board, there is PCM3168A codec chip, so enable
PCM3168A-I2C codec driver by setting configure
CONFIG_SND_SOC_PCM3168A_I2C

Signed-off-by: Meng Li 
---
 bsp/renesas-rcar/renesas-rcar.cfg | 1 +
 1 file changed, 1 insertion(+)

diff --git a/bsp/renesas-rcar/renesas-rcar.cfg 
b/bsp/renesas-rcar/renesas-rcar.cfg
index 102441ab..cc896276 100644
--- a/bsp/renesas-rcar/renesas-rcar.cfg
+++ b/bsp/renesas-rcar/renesas-rcar.cfg
@@ -96,6 +96,7 @@ CONFIG_SND_SOC_AK4613=y
 CONFIG_SND_SOC_HDMI_CODEC=y
 CONFIG_SND_SIMPLE_CARD=y
 CONFIG_SND_AUDIO_GRAPH_CARD=y
+CONFIG_SND_SOC_PCM3168A_I2C=y
 
 # Clock configuration
 CONFIG_COMMON_CLK=y
-- 
2.17.1

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[linux-yocto] [PATCH] renesas-rcar: add configure file for renesas BSP in kernel-cache

[Meng.Li]

From: Limeng 

Signed-off-by: Meng Li 
---
 bsp/renesas-rcar/renesas-rcar-h3-standard.scc |   7 +
 bsp/renesas-rcar/renesas-rcar-m3-standard.scc |   7 +
 bsp/renesas-rcar/renesas-rcar.cfg | 251 ++
 bsp/renesas-rcar/renesas-rcar.scc |   8 +
 4 files changed, 273 insertions(+)
 create mode 100644 bsp/renesas-rcar/renesas-rcar-h3-standard.scc
 create mode 100644 bsp/renesas-rcar/renesas-rcar-m3-standard.scc
 create mode 100644 bsp/renesas-rcar/renesas-rcar.cfg
 create mode 100644 bsp/renesas-rcar/renesas-rcar.scc

diff --git a/bsp/renesas-rcar/renesas-rcar-h3-standard.scc 
b/bsp/renesas-rcar/renesas-rcar-h3-standard.scc
new file mode 100644
index ..b01b4305
--- /dev/null
+++ b/bsp/renesas-rcar/renesas-rcar-h3-standard.scc
@@ -0,0 +1,7 @@
+define KMACHINE renesas-rcar-h3
+define KTYPE standard
+define KARCH arm64
+
+include ktypes/standard
+
+include renesas-rcar.scc
diff --git a/bsp/renesas-rcar/renesas-rcar-m3-standard.scc 
b/bsp/renesas-rcar/renesas-rcar-m3-standard.scc
new file mode 100644
index ..033c8ba6
--- /dev/null
+++ b/bsp/renesas-rcar/renesas-rcar-m3-standard.scc
@@ -0,0 +1,7 @@
+define KMACHINE renesas-rcar-m3
+define KTYPE standard
+define KARCH arm64
+
+include ktypes/standard
+
+include renesas-rcar.scc
diff --git a/bsp/renesas-rcar/renesas-rcar.cfg 
b/bsp/renesas-rcar/renesas-rcar.cfg
new file mode 100644
index ..102441ab
--- /dev/null
+++ b/bsp/renesas-rcar/renesas-rcar.cfg
@@ -0,0 +1,251 @@
+#.
+#WARNING
+#
+# This file is a kernel configuration fragment, and not a full kernel
+# configuration file.  The final kernel configuration is made up of
+# an assembly of processed fragments, each of which is designed to
+# capture a specific part of the final configuration (e.g. platform
+# configuration, feature configuration, and board specific hardware
+# configuration).  For more information on kernel configuration, please
+# consult the product documentation.
+#
+#.
+
+CONFIG_ARM64=y
+CONFIG_64BIT=y
+CONFIG_SMP=y
+
+# Platform selection
+CONFIG_ARCH_RENESAS=y
+CONFIG_ARCH_R8A7795=y
+CONFIG_ARCH_R8A7796=y
+CONFIG_ARM64_4K_PAGES=y
+CONFIG_ARM64_VA_BITS_48=y
+CONFIG_ARM64_VA_BITS=48
+CONFIG_NR_CPUS=8
+
+# CPU Idle
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_MENU=y
+CONFIG_DT_IDLE_STATES=y
+CONFIG_ARM_CPUIDLE=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPUFREQ_DT=y
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+
+# Networking options
+CONFIG_NET=y
+CONFIG_NET_INGRESS=y
+CONFIG_RAVB=y
+
+# Serial Congifuration
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_SERIAL_DEV_BUS=y
+CONFIG_SERIAL_SH_SCI=y
+CONFIG_SERIAL_SH_SCI_NR_UARTS=18
+CONFIG_SERIAL_SH_SCI_CONSOLE=y
+CONFIG_SERIAL_SH_SCI_EARLYCON=y
+CONFIG_SERIAL_SH_SCI_DMA=y
+
+# Spi configuration
+CONFIG_SPI=y
+CONFIG_SPI_SH_MSIOF=y
+CONFIG_SPI_GPIO=y
+
+# Pinctrl configuration
+CONFIG_PINMUX=y
+CONFIG_PINCONF=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_PINCTRL_SH_PFC=y
+CONFIG_PINCTRL_PFC_R8A7795=y
+CONFIG_PINCTRL_PFC_R8A7796=y
+
+# Watchdog configuration
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_RENESAS_WDT=y
+
+# Drm configuration
+CONFIG_DRM=y
+CONFIG_DRM_RCAR_DU=y
+CONFIG_DRM_RCAR_DW_HDMI=y
+CONFIG_DRM_RCAR_LVDS=y
+CONFIG_DRM_RCAR_VSP=y
+CONFIG_DRM_I2C_ADV7533=y
+CONFIG_DRM_I2C_ADV7511=y
+CONFIG_DRM_I2C_ADV7511_CEC=y
+CONFIG_DRM_DW_HDMI=y
+CONFIG_DRM_DUMB_VGA_DAC=y
+CONFIG_DRM_THINE_THC63LVD1024=y
+CONFIG_DRM_PANEL_LVDS=y
+CONFIG_DRM_DW_HDMI_I2S_AUDIO=y
+
+# LCD Backlight configuration
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+
+# Sound configuration
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_RCAR=y
+CONFIG_SND_SOC_AK4613=y
+CONFIG_SND_SOC_HDMI_CODEC=y
+CONFIG_SND_SIMPLE_CARD=y
+CONFIG_SND_AUDIO_GRAPH_CARD=y
+
+# Clock configuration
+CONFIG_COMMON_CLK=y
+CONFIG_COMMON_CLK_CS2000_CP=y
+CONFIG_COMMON_CLK_VC5=y
+
+# USB configuration
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_XHCI_HCD=m
+CONFIG_USB_XHCI_RCAR=m
+CONFIG_USB_XHCI_PLATFORM=m
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+CONFIG_USB_OTG=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PCI=y
+CONFIG_USB_OHCI_HCD_PLATFORM=y
+CONFIG_USB_RENESAS_USBHS=y
+CONFIG_USB_RENESAS_USBHS_UDC=y
+CONFIG_USB_RENESAS_USB3=m
+CONFIG_USB_DWC3=y
+CONFIG_GENERIC_PHY=y
+CONFIG_PHY_RCAR_GEN3_USB2=y
+CONFIG_PHY_RCAR_GEN3_USB3=y
+
+# PWM configuration
+CONFIG_PWM=y
+CONFIG_PWM_SYSFS=y
+CONFIG_PWM_RCAR=y
+
+# PCIe configuration
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DOMAINS_GENERIC=y
+CONFIG_PCIE_RCAR=y
+CONFIG_PCI_MSI=y
+CONFIG_PCIEPORTBUS=y
+
+# Sata configuration
+CONFIG_ATA=y
+CONFIG_SATA_AHCI=y
+CONFIG_SATA_AHCI_PLATFORM=y
+CONFIG_SATA_RCAR=y
+
+# I2C configuration
+CONFIG_I2C=y
+CONFIG_I2C_RCAR=y
+CONFIG_I2C_SH_MOBILE=y
+CONFIG_I2C_MUX=y

[linux-yocto] : [kernel-cache master]: renesas-rcar: add configure file for renesas BSP in kernel-cache

[Meng.Li]

From: Limeng 

Hi Bruce,

I am working on BSP renesas-rcar platform, and intend to merge this BSP 
supporting into yocto community.
Below patch includes scc and cfg files for renesas-rcar platform.

Could you please merge this patch into yocto-kernel-cache, branch is master?


0001-renesas-rcar-add-configure-file-for-renesas-BSP-in-k.patch

 renesas-rcar-h3-standard.scc |7 +
 renesas-rcar-m3-standard.scc |7 +
 renesas-rcar.cfg |  251 +++
 renesas-rcar.scc |8 +
 4 files changed, 273 insertions(+)


thanks,
Limeng
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[linux-yocto] [PATCH] arch: arm64: dts: add altr, sysmgr-syscon property for Ethernet driver

[Meng.Li]

From: Limeng 

In Stratix10 latest dwmac-socfpga.c Ethernet driver, the property
altr,sysmgr-syscon is parsed during driver probe. So, it is need to
add it to avoid drvier probe failed. This modification refer to SDK
kernel https://github.com/altera-opensource/linux-socfpga.git,
commit  070175e6c913 ("FogBugz #454145: Update stratix10_swvp.dts
file for S10 SoC VP")

Signed-off-by: Meng Li 
---
 arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi 
b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
index a5838a0..fdd7501 100644
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
@@ -154,6 +154,7 @@
 
gmac0: ethernet@ff80 {
compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", 
"snps,dwmac";
+   altr,sysmgr-syscon = < 0x44 0>;
reg = <0xff80 0x2000>;
interrupts = <0 90 4>;
interrupt-names = "macirq";
@@ -170,6 +171,7 @@
 
gmac1: ethernet@ff802000 {
compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", 
"snps,dwmac";
+   altr,sysmgr-syscon = < 0x48 0>;
reg = <0xff802000 0x2000>;
interrupts = <0 91 4>;
interrupt-names = "macirq";
@@ -186,6 +188,7 @@
 
gmac2: ethernet@ff804000 {
compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", 
"snps,dwmac";
+   altr,sysmgr-syscon = < 0x4c 0>;
reg = <0xff804000 0x2000>;
interrupts = <0 92 4>;
interrupt-names = "macirq";
@@ -368,6 +371,8 @@
sysmgr: sysmgr@ffd12000 {
compatible = "altr,sys-mgr", "syscon";
reg = <0xffd12000 0x228>;
+   interrupts = <0x0 0x10 0x4>;
+   cpu1-start-addr = <0xffd06230>;
};
 
/* Local timer */
-- 
2.7.4

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[linux-yocto] [V2] : [yocto-4.18]: intel-socfpga: arch: arm64: dts: add altr, sysmgr-syscon property for Ethernet driver

[Meng.Li]

From: Limeng 

Hi Bruce,

Could you please help to merge below one patch into linux-yocto, kernel 4.18, 
branch is v4.18/standard/intel-socfpga
 
0001-arch-arm64-dts-add-altr-sysmgr-syscon-property-for-E.patch

 socfpga_stratix10.dtsi |5 +
 1 file changed, 5 insertions(+)

v2:
There is context conflict in V1 patch. fix the conflict in v2 as below
change
reg = <0xffd12000 0x1000>;
into
reg = <0xffd12000 0x228>;

thanks,
Limeng


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[linux-yocto] : [yocto-4.18]: intel-socfpga: arch: arm64: dts: add altr, sysmgr-syscon property for Ethernet driver

[Meng.Li]

From: Limeng 

Hi Bruce,

Could you please help to merge below one patch into linux-yocto, kernel 4.18, 
branch is v4.18/standard/intel-socfpga
 
0001-arch-arm64-dts-add-altr-sysmgr-syscon-property-for-E.patch

 socfpga_stratix10.dtsi |5 +
 1 file changed, 5 insertions(+)

thanks,
Limeng


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[linux-yocto] [PATCH] arch: arm64: dts: add altr, sysmgr-syscon property for Ethernet driver

[Meng.Li]

From: Limeng 

In Stratix10 latest dwmac-socfpga.c Ethernet driver, the property
altr,sysmgr-syscon is parsed during driver probe. So, it is need to
add it to avoid drvier probe failed. This modification refer to SDK
kernel https://github.com/altera-opensource/linux-socfpga.git,
commit  070175e6c913 ("FogBugz #454145: Update stratix10_swvp.dts
file for S10 SoC VP")

Signed-off-by: Meng Li 
---
 arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi 
b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
index a5838a0..fdd7501 100644
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
@@ -154,6 +154,7 @@
 
gmac0: ethernet@ff80 {
compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", 
"snps,dwmac";
+   altr,sysmgr-syscon = < 0x44 0>;
reg = <0xff80 0x2000>;
interrupts = <0 90 4>;
interrupt-names = "macirq";
@@ -170,6 +171,7 @@
 
gmac1: ethernet@ff802000 {
compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", 
"snps,dwmac";
+   altr,sysmgr-syscon = < 0x48 0>;
reg = <0xff802000 0x2000>;
interrupts = <0 91 4>;
interrupt-names = "macirq";
@@ -186,6 +188,7 @@
 
gmac2: ethernet@ff804000 {
compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", 
"snps,dwmac";
+   altr,sysmgr-syscon = < 0x4c 0>;
reg = <0xff804000 0x2000>;
interrupts = <0 92 4>;
interrupt-names = "macirq";
@@ -368,6 +371,8 @@
sysmgr: sysmgr@ffd12000 {
compatible = "altr,sys-mgr", "syscon";
reg = <0xffd12000 0x1000>;
+   interrupts = <0x0 0x10 0x4>;
+   cpu1-start-addr = <0xffd06230>;
};
 
/* Local timer */
-- 
2.7.4

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[linux-yocto] [PATCH 5/8] arm64: dts: stratix10: Support Ethernet Jumbo frame

[Meng.Li]

From: Thor Thayer 

commit 273dce368d19982f65abe8bdced67f4218f03c06 from
https://github.com/altera-opensource/linux-socfpga.git

[backport 'commit a27460c9768e ("arm64: dts: stratix10: Support
 Ethernet Jumbo frame")']

Backported from net-next/master

Properly specify the RX and TX FIFO size which is important
for Jumbo frames.
Update the max-frame-size to support Jumbo frames.

Signed-off-by: Thor Thayer 
Signed-off-by: David S. Miller 
Signed-off-by: Meng Li 
---
 arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi  | 6 ++
 arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts | 2 +-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi 
b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
index 9a7c50b..84d2722 100644
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
@@ -162,6 +162,8 @@
reset-names = "stmmaceth", "stmmaceth-ocp";
clocks = < STRATIX10_EMAC0_CLK>;
clock-names = "stmmaceth";
+   tx-fifo-depth = <16384>;
+   rx-fifo-depth = <16384>;
status = "disabled";
};
 
@@ -175,6 +177,8 @@
reset-names = "stmmaceth", "stmmaceth-ocp";
clocks = < STRATIX10_EMAC1_CLK>;
clock-names = "stmmaceth";
+   tx-fifo-depth = <16384>;
+   rx-fifo-depth = <16384>;
status = "disabled";
};
 
@@ -188,6 +192,8 @@
reset-names = "stmmaceth", "stmmaceth-ocp";
clocks = < STRATIX10_EMAC2_CLK>;
clock-names = "stmmaceth";
+   tx-fifo-depth = <16384>;
+   rx-fifo-depth = <16384>;
status = "disabled";
};
 
diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts 
b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
index 86dc7529..02f 100644
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
@@ -92,7 +92,7 @@
phy-mode = "rgmii";
phy-handle = <>;
 
-   max-frame-size = <3800>;
+   max-frame-size = <9000>;
snps,multicast-filter-bins = <256>;
 
mdio0 {
-- 
2.7.4

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[linux-yocto] [PATCH 4/8] FogBugz #593535: stmmac: resolve smc related boot crash for ARMv7

[Meng.Li]

From: Richard Gong 

commit 5acba7e774b661317bb3f3d1b23a60687f5a25a1 from
https://github.com/altera-opensource/linux-socfpga.git

Fix previous commit e8c95776cfce ("FogBugz #577927: stmmac: Add SMC
support for EMAC System Manager register")

The #ifdefs that check for SMC are insufficient, since currently only
Stratix10 has the trusted firmware that services these specific SMC calls.
Other ARMv7 platforms will crash at the first arm_smccc_smc() call. Fix
this by adding one additional check to allow the kernel boot properly on
other ARMv7 platforms.

Signed-off-by: Richard Gong 
Signed-off-by: Meng Li 
---
 .../net/ethernet/stmicro/stmmac/dwmac-socfpga.c| 27 ++
 1 file changed, 23 insertions(+), 4 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c 
b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
index afdd482..e6f5735 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
@@ -15,7 +15,7 @@
  * Adopted from dwmac-sti.c
  */
 
-#ifdef CONFIG_HAVE_ARM_SMCCC
+#if defined CONFIG_HAVE_ARM_SMCCC && defined CONFIG_ARCH_STRATIX10
 #include 
 #endif
 #include 
@@ -55,7 +55,9 @@ struct socfpga_dwmac {
int interface;
u32 reg_offset;
u32 reg_shift;
+#if defined CONFIG_HAVE_ARM_SMCCC && defined CONFIG_ARCH_STRATIX10
u32 sysmgr_reg;
+#endif
struct  device *dev;
struct regmap *sys_mgr_base_addr;
struct reset_control *stmmac_rst;
@@ -65,7 +67,7 @@ struct socfpga_dwmac {
struct tse_pcs pcs;
 };
 
-#ifdef CONFIG_HAVE_ARM_SMCCC
+#if defined CONFIG_HAVE_ARM_SMCCC && defined CONFIG_ARCH_STRATIX10
 /* Functions specified by ARM SMC Calling convention:
  *
  * FAST call executes atomic operations, returns when the requested operation
@@ -224,18 +226,23 @@ static int socfpga_dwmac_parse_data(struct socfpga_dwmac 
*dwmac, struct device *
 {
struct device_node *np = dev->of_node;
struct regmap *sys_mgr_base_addr;
-   u32 reg_offset, reg_shift, sysmgr_reg = 0;
+   u32 reg_offset, reg_shift;
+#if defined CONFIG_HAVE_ARM_SMCCC && defined CONFIG_ARCH_STRATIX10
+   u32 sysmgr_reg = 0;
+#endif
int ret, index;
struct device_node *np_splitter = NULL;
struct device_node *np_sgmii_adapter = NULL;
+#if defined CONFIG_HAVE_ARM_SMCCC && defined CONFIG_ARCH_STRATIX10
struct device_node *np_sysmgr = NULL;
+#endif
struct resource res_splitter;
struct resource res_tse_pcs;
struct resource res_sgmii_adapter;
 
dwmac->interface = of_get_phy_mode(np);
 
-#ifdef CONFIG_HAVE_ARM_SMCCC
+#if defined CONFIG_HAVE_ARM_SMCCC && defined CONFIG_ARCH_STRATIX10
sys_mgr_base_addr = devm_regmap_init(dev, NULL, (void *)dwmac,
 _emac_regmap_cfg);
if (IS_ERR(sys_mgr_base_addr))
@@ -360,7 +367,9 @@ static int socfpga_dwmac_parse_data(struct socfpga_dwmac 
*dwmac, struct device *
dwmac->reg_offset = reg_offset;
dwmac->reg_shift = reg_shift;
dwmac->sys_mgr_base_addr = sys_mgr_base_addr;
+#if defined CONFIG_HAVE_ARM_SMCCC && defined CONFIG_ARCH_STRATIX10
dwmac->sysmgr_reg = sysmgr_reg;
+#endif
dwmac->dev = dev;
of_node_put(np_sgmii_adapter);
 
@@ -377,7 +386,9 @@ static int socfpga_dwmac_set_phy_mode(struct socfpga_dwmac 
*dwmac)
int phymode = dwmac->interface;
u32 reg_offset = dwmac->reg_offset;
u32 reg_shift = dwmac->reg_shift;
+#if defined CONFIG_HAVE_ARM_SMCCC && defined CONFIG_ARCH_STRATIX10
u32 sysmgr_reg = dwmac->sysmgr_reg;
+#endif
u32 ctrl, val, module;
 
switch (phymode) {
@@ -406,7 +417,11 @@ static int socfpga_dwmac_set_phy_mode(struct socfpga_dwmac 
*dwmac)
reset_control_assert(dwmac->stmmac_ocp_rst);
reset_control_assert(dwmac->stmmac_rst);
 
+#if defined CONFIG_HAVE_ARM_SMCCC && defined CONFIG_ARCH_STRATIX10
regmap_read(sys_mgr_base_addr, sysmgr_reg + reg_offset, );
+#else
+   regmap_read(sys_mgr_base_addr, reg_offset, );
+#endif
ctrl &= ~(SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << reg_shift);
ctrl |= val << reg_shift;
 
@@ -424,7 +439,11 @@ static int socfpga_dwmac_set_phy_mode(struct socfpga_dwmac 
*dwmac)
ctrl &= ~(SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK << (reg_shift / 
2));
}
 
+#if defined CONFIG_HAVE_ARM_SMCCC && defined CONFIG_ARCH_STRATIX10
regmap_write(sys_mgr_base_addr, sysmgr_reg + reg_offset, ctrl);
+#else
+   regmap_write(sys_mgr_base_addr, reg_offset, ctrl);
+#endif
 
/* Deassert reset for the phy configuration to be sampled by
 * the enet controller, and operation to start in requested mode
-- 
2.7.4

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[linux-yocto] [PATCH 7/8] arm64: dts: stratix10: fix multicast filtering

[Meng.Li]

From: Aaro Koskinen 

commit 2f43a510fc1190bec012c9c73102baf70d1be6cb from
https://github.com/altera-opensource/linux-socfpga.git

On Stratix 10, the EMAC has 256 hash buckets for multicast filtering. This
needs to be specified in DTS, otherwise the stmmac driver defaults to 64
buckets and initializes the filter incorrectly. As a result, e.g. valid
IPv6 multicast traffic ends up being dropped.

Fixes: 78cd6a9d8e15 ("arm64: dts: Add base stratix 10 dtsi")
Cc: sta...@vger.kernel.org
Signed-off-by: Aaro Koskinen 
Signed-off-by: Dinh Nguyen 
(cherry picked from commit fd5ba6ee3187617287fb9cb187e3d6b3631210a3)
Signed-off-by: Meng Li 
---
 arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi 
b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
index 84d2722..a5838a0 100644
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
@@ -164,6 +164,7 @@
clock-names = "stmmaceth";
tx-fifo-depth = <16384>;
rx-fifo-depth = <16384>;
+   snps,multicast-filter-bins = <256>;
status = "disabled";
};
 
@@ -179,6 +180,7 @@
clock-names = "stmmaceth";
tx-fifo-depth = <16384>;
rx-fifo-depth = <16384>;
+   snps,multicast-filter-bins = <256>;
status = "disabled";
};
 
@@ -194,6 +196,7 @@
clock-names = "stmmaceth";
tx-fifo-depth = <16384>;
rx-fifo-depth = <16384>;
+   snps,multicast-filter-bins = <256>;
status = "disabled";
};
 
-- 
2.7.4

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[linux-yocto] : [yocto-4.18]: intel-socfpga: get latest patches from sdk

[Meng.Li]

From: Limeng 

Hi Bruce,

Now, there are some update for intel-socfpga, Stratix10 SoC from Intel-PSG SDK 
kernel-4.18.
Detail patches as below

Please help to meger below patches into linux-yocto, kernel 4.18, branch is 
v4.18/standard/intel-socfpga
 
0001-ARM-dts-socfpga-set-timer-interrupt-to-edge-sensitiv.patch
0002-net-stmmac-build-the-dwmac-socfpga-platform-driver-f.patch
0003-FogBugz-577927-stmmac-Add-SMC-support-for-EMAC-Syste.patch
0004-FogBugz-593535-stmmac-resolve-smc-related-boot-crash.patch
0005-arm64-dts-stratix10-Support-Ethernet-Jumbo-frame.patch
0006-net-stmmac-Set-OWN-bit-for-jumbo-frames.patch
0007-arm64-dts-stratix10-fix-multicast-filtering.patch
0008-net-stmmac-Fix-RX-packet-size-8191.patch


 arch/arm/boot/dts/socfpga_arria10.dtsi |2 
 arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi  |9 
 arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts |2 
 drivers/net/ethernet/stmicro/stmmac/Kconfig|2 
 drivers/net/ethernet/stmicro/stmmac/common.h   |3 
 drivers/net/ethernet/stmicro/stmmac/descs_com.h|2 
 drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c|  173 -
 drivers/net/ethernet/stmicro/stmmac/enh_desc.c |2 
 drivers/net/ethernet/stmicro/stmmac/ring_mode.c|6 
 9 files changed, 185 insertions(+), 16 deletions(-)

thanks,
Limeng


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[linux-yocto] [PATCH 3/8] FogBugz #577927: stmmac: Add SMC support for EMAC System Manager register

[Meng.Li]

From: "Ooi, Joyce" 

commit 80f73e5d68c8acdc53d812bb6ca0d8ac9d0d12df from
https://github.com/altera-opensource/linux-socfpga.git

As there is restriction to access to EMAC System Manager registers in
the kernel, the use of SMC calls are required and added in
dwmac-socfpga driver.

Signed-off-by: Ooi, Joyce 
Signed-off-by: Meng Li 
---
 .../net/ethernet/stmicro/stmmac/dwmac-socfpga.c| 146 -
 1 file changed, 143 insertions(+), 3 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c 
b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
index 5b3b06a..afdd482 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
@@ -15,6 +15,9 @@
  * Adopted from dwmac-sti.c
  */
 
+#ifdef CONFIG_HAVE_ARM_SMCCC
+#include 
+#endif
 #include 
 #include 
 #include 
@@ -52,6 +55,7 @@ struct socfpga_dwmac {
int interface;
u32 reg_offset;
u32 reg_shift;
+   u32 sysmgr_reg;
struct  device *dev;
struct regmap *sys_mgr_base_addr;
struct reset_control *stmmac_rst;
@@ -61,6 +65,122 @@ struct socfpga_dwmac {
struct tse_pcs pcs;
 };
 
+#ifdef CONFIG_HAVE_ARM_SMCCC
+/* Functions specified by ARM SMC Calling convention:
+ *
+ * FAST call executes atomic operations, returns when the requested operation
+ * has completed.
+ * STD call starts a operation which can be preempted by a non-secure
+ * interrupt. The call can return before the requested operation has completed.
+ * a0..a7 is used as register names in the descriptions below, on arm32 that
+ * translates to r0..r7 and on arm64 to w0..w7.
+ */
+
+#define INTEL_SIP_SMC_STD_CALL_VAL(func_num) \
+   ARM_SMCCC_CALL_VAL(ARM_SMCCC_STD_CALL, ARM_SMCCC_SMC_64, \
+   ARM_SMCCC_OWNER_SIP, (func_num))
+
+#define INTEL_SIP_SMC_FAST_CALL_VAL(func_num) \
+   ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, ARM_SMCCC_SMC_64, \
+   ARM_SMCCC_OWNER_SIP, (func_num))
+
+#define INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION  0x
+#define INTEL_SIP_SMC_STATUS_OK0x0
+#define INTEL_SIP_SMC_REG_ERROR0x5
+
+/* Request INTEL_SIP_SMC_REG_READ
+ *
+ * Read a protected register using SMCCC
+ *
+ * Call register usage:
+ * a0: INTEL_SIP_SMC_REG_READ.
+ * a1: register address.
+ * a2-7: not used.
+ *
+ * Return status:
+ * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_REG_ERROR, or
+ * INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION
+ * a1: Value in the register
+ * a2-3: not used.
+ */
+#define INTEL_SIP_SMC_FUNCID_REG_READ 7
+#define INTEL_SIP_SMC_REG_READ \
+   INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_REG_READ)
+
+/* Request INTEL_SIP_SMC_REG_WRITE
+ *
+ * Write a protected register using SMCCC
+ *
+ * Call register usage:
+ * a0: INTEL_SIP_SMC_REG_WRITE.
+ * a1: register address
+ * a2: value to program into register.
+ * a3-7: not used.
+ *
+ * Return status:
+ * a0: INTEL_SIP_SMC_STATUS_OK, INTEL_SIP_SMC_REG_ERROR, or
+ * INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION
+ * a1-3: not used.
+ */
+#define INTEL_SIP_SMC_FUNCID_REG_WRITE 8
+#define INTEL_SIP_SMC_REG_WRITE \
+   INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_REG_WRITE)
+
+/ Stratix 10 EMAC Memory Controller Functions /
+
+/* s10_protected_reg_write
+ * Write to a protected SMC register.
+ * @context: Not used
+ * @reg: Address of register
+ * @value: Value to write
+ * Return: INTEL_SIP_SMC_STATUS_OK (0) on success
+ * INTEL_SIP_SMC_REG_ERROR on error
+ * INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION if not supported
+ */
+static int s10_protected_reg_write(void *context, unsigned int reg,
+  unsigned int val)
+{
+   struct arm_smccc_res result;
+
+   arm_smccc_smc(INTEL_SIP_SMC_REG_WRITE, reg, val, 0, 0,
+ 0, 0, 0, );
+
+   return (int)result.a0;
+}
+
+/* s10_protected_reg_read
+ * Read the status of a protected SMC register
+ * @context: Not used
+ * @reg: Address of register
+ * @value: Value read.
+ * Return: INTEL_SIP_SMC_STATUS_OK (0) on success
+ * INTEL_SIP_SMC_REG_ERROR on error
+ * INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION if not supported
+ */
+static int s10_protected_reg_read(void *context, unsigned int reg,
+ unsigned int *val)
+{
+   struct arm_smccc_res result;
+
+   arm_smccc_smc(INTEL_SIP_SMC_REG_READ, reg, 0, 0, 0,
+ 0, 0, 0, );
+
+   *val = (unsigned int)result.a1;
+
+   return (int)result.a0;
+}
+
+static const struct regmap_config s10_emac_regmap_cfg = {
+   .name = "s10_emac",
+   .reg_bits = 32,
+   .val_bits = 32,
+   .max_register = 0x,
+   .reg_read = s10_protected_reg_read,
+   .reg_write = s10_protected_reg_write,
+   .use_single_rw = true,
+};
+#endif
+
 static void socfpga_dwmac_fix_mac_speed(void *priv, unsigned int speed)
 {

[linux-yocto] [PATCH 1/8] ARM: dts: socfpga: set timer interrupt to edge sensitive

[Meng.Li]

From: Silvan Murer 

commit cf0cf72063d6bf0448129db4f0930ad895b90f0e from
https://github.com/altera-opensource/linux-socfpga.git

Change timer interrupt to edge sensitive.

Signed-off-by: Silvan Murer 
Reviewed-by: Thor Thayer 
Signed-off-by: Dinh Nguyen 
Signed-off-by: Meng Li 
---
 arch/arm/boot/dts/socfpga_arria10.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi 
b/arch/arm/boot/dts/socfpga_arria10.dtsi
index caa3735..6d95c03 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -749,7 +749,7 @@
timer@c600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0xc600 0x100>;
-   interrupts = <1 13 0xf04>;
+   interrupts = <1 13 0xf01>;
clocks = <_periph_clk>;
};
 
-- 
2.7.4

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[linux-yocto] [PATCH 2/8] net: stmmac: build the dwmac-socfpga platform driver for Stratix10

[Meng.Li]

From: Dinh Nguyen 

commit 57124cfbec9909ccdb5f805e5eeb5095ed85767c from
https://github.com/altera-opensource/linux-socfpga.git

The Stratix10 SoC is an AARCH64 based platform that shares the same ethernet
controller that is on other SoCFPGA platforms. Build the platform driver.

Signed-off-by: Dinh Nguyen 
Signed-off-by: David S. Miller 
Signed-off-by: Meng Li 
---
 drivers/net/ethernet/stmicro/stmmac/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig 
b/drivers/net/ethernet/stmicro/stmmac/Kconfig
index edf2036..a14085b 100644
--- a/drivers/net/ethernet/stmicro/stmmac/Kconfig
+++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig
@@ -110,7 +110,7 @@ config DWMAC_ROCKCHIP
 
 config DWMAC_SOCFPGA
tristate "SOCFPGA dwmac support"
-   default ARCH_SOCFPGA
+   default (ARCH_SOCFPGA || ARCH_STRATIX10)
depends on OF && (ARCH_SOCFPGA || ARCH_STRATIX10 || COMPILE_TEST)
select MFD_SYSCON
help
-- 
2.7.4

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[linux-yocto] [PATCH] arch: arm64: dts: add property snps, multicast-filter-bins for stratix10 platform

[Meng.Li]

From: Limeng 

The property value of snps,multicast-filter-bins is used to calculate
hash table size of stratix10 platform via log2 algorithm.
Because there are 8 hash table registers, the property value is 256

Signed-off-by: Meng Li 
---
 arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts 
b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
index 236667a..86dc7529 100644
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
@@ -93,6 +93,7 @@
phy-handle = <>;
 
max-frame-size = <3800>;
+   snps,multicast-filter-bins = <256>;
 
mdio0 {
#address-cells = <1>;
-- 
2.7.4

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[linux-yocto] : [yocto-4.18]: arch: arm64: dts: add property snps, multicast-filter-bins for stratix10 platform

[Meng.Li]

From: Limeng 


Hi Bruce,

Could you please help to merge this patch into linux-yocto kernel, branch is 
v4.18/standard/intel-socfpga


 socfpga_stratix10_socdk.dts |1 +
 1 file changed, 1 insertion(+)


Thanks,
Limeng

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[linux-yocto] : [yocto-4.18]: intel-socfpga: kernel patches

[Meng.Li]

From: Limeng 


Hi Bruce,

I am working on BSP intel-socfpga.

Could you please help to create branch "v4.18/standard/intel-socfpga" in 
linux-yocto kernel?
And then merge these kernel patches into this branch.

I verify these patches on Intel-PSG stratix10 development board.
Boot up log as below:

Starting kernel ...

Booting Linux on physical CPU 0x00 [0x410fd034]
Linux version 4.18.9-yoctodev-standard (oe-user@oe-host) (gcc version 8.2.0 
(GCC)) #1 SMP PREEMPT Sat Sep 29 10:47:46 UTC 2018
Machine model: SoCFPGA Stratix 10 SoCDK
earlycon: uart0 at MMIO32 0xffc02000 (options '115200n8')
bootconsole [uart0] enabled
efi: Getting EFI parameters from FDT:
efi: UEFI not found.
Reserved memory: created DMA memory pool at 0x, size 16 MiB
OF: reserved mem: initialized node svcbuffer@0, compatible id shared-dma-pool
cma: Reserved 16 MiB at 0x7e80
psci: probing for conduit method from DT.
psci: PSCIv65535.65535 detected in firmware.
psci: Using standard PSCI v0.2 function IDs
psci: MIGRATE_INFO_TYPE not supported.
psci: SMC Calling Convention v1.0
random: get_random_bytes called from start_kernel+0x9c/0x458 with crng_init=0
percpu: Embedded 23 pages/cpu @(ptrval) s53784 r8192 d32232 u94208
Detected VIPT I-cache on CPU0
CPU features: enabling workaround for ARM erratum 845719
CPU features: detected: Kernel page table isolation (KPTI)
Built 1 zonelists, mobility grouping on.  Total pages: 512064
Kernel command line: console=ttyS0,115200n8 earlycon root=/dev/nfs rw 
no_console_suspend rootwait 
nfsroot=128.224.162.206:/home/wrsadmin/Project/Native/nfsroot/intel-stratix10-1018,v3,p
Dentry cache hash table entries: 262144 (order: 9, 2097152 bytes)
Inode-cache hash table entries: 131072 (order: 8, 1048576 bytes)
Memory: 2011824K/2080768K available (9276K kernel code, 1060K rwdata, 4192K 
rodata, 960K init, 649K bss, 52560K reserved, 16384K cma-reserved)
SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
ftrace: allocating 31531 entries in 124 pages
Preemptible hierarchical RCU implementation.
Tasks RCU enabled.
NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
GIC: Using split EOI/Deactivate mode
arch_timer: cp15 timer(s) running at 400.00MHz (phys).
clocksource: arch_sys_counter: mask: 0xff max_cycles: 0x5c4093a7d1, 
max_idle_ns: 440795210635 ns
sched_clock: 56 bits at 400MHz, resolution 2ns, wraps every 4398046511103ns
Console: colour dummy device 80x25
Calibrating delay loop (skipped), value calculated using timer frequency.. 
800.00 BogoMIPS (lpj=160)
pid_max: default: 32768 minimum: 301
Security Framework initialized
Mount-cache hash table entries: 4096 (order: 3, 32768 bytes)
Mountpoint-cache hash table entries: 4096 (order: 3, 32768 bytes)
ASID allocator initialised with 32768 entries
Hierarchical SRCU implementation.
EFI services will not be available.
smp: Bringing up secondary CPUs ...
Detected VIPT I-cache on CPU1
CPU1: Booted secondary processor 0x01 [0x410fd034]
Detected VIPT I-cache on CPU2
CPU2: Booted secondary processor 0x02 [0x410fd034]
Detected VIPT I-cache on CPU3
CPU3: Booted secondary processor 0x03 [0x410fd034]
smp: Brought up 1 node, 4 CPUs
SMP: Total of 4 processors activated.
CPU features: detected: 32-bit EL0 Support
CPU: All CPU(s) started at EL2
alternatives: patching kernel code
devtmpfs: initialized
clocksource: jiffies: mask: 0x max_cycles: 0x, max_idle_ns: 
764504178510 ns
futex hash table entries: 1024 (order: 4, 65536 bytes)
xor: measuring software checksum speed
   8regs :  1967.000 MB/sec
   8regs_prefetch:  1701.000 MB/sec
   32regs:  2255.000 MB/sec
   32regs_prefetch:  1912.000 MB/sec
xor: using function: 32regs (2255.000 MB/sec)
DMI not present or invalid.
NET: Registered protocol family 16
cpuidle: using governor ladder
vdso: 2 pages (1 code @ (ptrval), 1 data @ (ptrval))
hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
DMA: preallocated 256 KiB pool for atomic allocations
raid6: int64x1  gen()   381 MB/s
raid6: int64x1  xor()   380 MB/s
raid6: int64x2  gen()   583 MB/s
raid6: int64x2  xor()   504 MB/s
raid6: int64x4  gen()   833 MB/s
raid6: int64x4  xor()   618 MB/s
raid6: int64x8  gen()   980 MB/s
raid6: int64x8  xor()   635 MB/s
raid6: neonx1   gen()   625 MB/s
raid6: neonx1   xor()   732 MB/s
raid6: neonx2   gen()   959 MB/s
raid6: neonx2   xor()   975 MB/s
raid6: neonx4   gen()  1263 MB/s
raid6: neonx4   xor()  1180 MB/s
raid6: neonx8   gen()  1291 MB/s
raid6: neonx8   xor()  1205 MB/s
raid6: using algorithm neonx8 gen() 1291 MB/s
raid6:  xor() 1205 MB/s, rmw enabled
raid6: using neon recovery algorithm
vgaarb: loaded
Intel Service Layer Driver Initialized
SCSI subsystem initialized
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
usb_phy_generic soc:usbphy@0: soc:usbphy@0 supply vcc not found, using dummy 
regulator
pps_core: 

[linux-yocto] [PATCH 3/3] EDAC, altera: Fix ARM64 build warning

[Meng.Li]

From: Thor Thayer 

commit 9ef20753e044f7468c4113e5aecd785419b0b3cc from
https://github.com/altera-opensource/linux-socfpga.git

The kbuild test robot reported the following warning:

  drivers/edac/altera_edac.c: In function 'ocram_free_mem':
  drivers/edac/altera_edac.c:1410:42: warning: cast from pointer to integer
of different size [-Wpointer-to-int-cast]
gen_pool_free((struct gen_pool *)other, (u32)p, size);
 ^

After adding support for ARM64 architectures, the unsigned long
parameter is 64 bits and causes a build warning on 64-bit configs. Fix
by casting to the correct size (unsigned long) instead of u32.

Reported-by: kbuild test robot 
Signed-off-by: Thor Thayer 
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-edac 
Fixes: c3eea1942a16 ("EDAC, altera: Add Altera L2 cache and OCRAM support")
Link: 
http://lkml.kernel.org/r/1526317441-4996-1-git-send-email-thor.tha...@linux.intel.com
Signed-off-by: Borislav Petkov 
Signed-off-by: Meng Li 
---
 drivers/edac/altera_edac.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c
index 68ea613..308dcfc 100644
--- a/drivers/edac/altera_edac.c
+++ b/drivers/edac/altera_edac.c
@@ -1423,7 +1423,7 @@ static void *ocram_alloc_mem(size_t size, void **other)
 
 static void ocram_free_mem(void *p, size_t size, void *other)
 {
-   gen_pool_free((struct gen_pool *)other, (u32)p, size);
+   gen_pool_free((struct gen_pool *)other, (unsigned long)p, size);
 }
 
 static const struct edac_device_prv_data ocramecc_data = {
-- 
2.7.4

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[linux-yocto] : [yocto-4.12]: intel-socfpga: intel-socfpga: drivers: edac: get patches for double bits ecc error detection

[Meng.Li]

From: Limeng 


Hi Bruce,

Get below patches for double bits ecc error detection feature

0001-Documentation-dt-edac-Move-Altera-SOCFPGA-EDAC-file.patch
0002-EDAC-altera-Handle-SDRAM-Uncorrectable-Errors-on-Str.patch
0003-EDAC-altera-Fix-ARM64-build-warning.patch

Please help to meger this patch into linux-yocto, kernel 4.12, branch is 
standard/base


 Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt |  275 
--
 b/Documentation/devicetree/bindings/edac/socfpga-eccmgr.txt |  275 
++
 b/drivers/edac/altera_edac.c|   69 ++
 b/drivers/edac/altera_edac.h|8 
 4 files changed, 340 insertions(+), 287 deletions(-)


thanks,
Limeng
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[linux-yocto] [PATCH 2/3] EDAC, altera: Handle SDRAM Uncorrectable Errors on Stratix10

[Meng.Li]

From: Thor Thayer 

commit f8eb0edeb8c19aba667a087b80706bf4f61f8256 from
https://github.com/altera-opensource/linux-socfpga.git

On Stratix10, uncorrectable errors are routed to the SError exception
instead of the IRQ exceptions. In Stratix10, uncorrectable SErrors
must be treated as fatal and will cause a panic. Older Altera/Intel
parts printed out a message for UE so do that here using the notifier
framework.

Record the UE in sticky registers that retain the state through a reset.
Check these registers on probe and printout the error on startup.

Signed-off-by: Thor Thayer 
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-edac 
Cc: mark.rutl...@arm.com
Cc: mche...@kernel.org
Cc: will.dea...@arm.com
Link: 
http://lkml.kernel.org/r/1526079610-5527-1-git-send-email-thor.tha...@linux.intel.com
[ Remove unused var in s10_edac_dberr_handler(), reorder args. ]
Signed-off-by: Borislav Petkov 
Signed-off-by: Meng Li 
---
 drivers/edac/altera_edac.c | 67 +++---
 drivers/edac/altera_edac.h |  8 +-
 2 files changed, 64 insertions(+), 11 deletions(-)

diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c
index fcd0c95..68ea613 100644
--- a/drivers/edac/altera_edac.c
+++ b/drivers/edac/altera_edac.c
@@ -14,6 +14,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -735,6 +736,13 @@ static int altr_s10_sdram_probe(struct platform_device 
*pdev)
goto err2;
}
 
+   if (regmap_write(regmap, S10_SYSMGR_ECC_INTMASK_CLR_OFST,
+S10_DDR0_IRQ_MASK)) {
+   edac_printk(KERN_ERR, EDAC_MC,
+   "Error clearing SDRAM ECC count\n");
+   return -ENODEV;
+   }
+
if (regmap_update_bits(drvdata->mc_vbase, priv->ecc_irq_en_offset,
   priv->ecc_irq_en_mask, priv->ecc_irq_en_mask)) {
edac_mc_printk(mci, KERN_ERR,
@@ -2236,23 +2244,50 @@ module_platform_driver(altr_edac_a10_driver);
 
 /** Stratix 10 EDAC Device Controller Functions> /
 
+#define to_s10edac(p, m) container_of(p, struct altr_stratix10_edac, m)
+
+/*
+ * The double bit error is handled through SError which is fatal. This is
+ * called as a panic notifier to printout ECC error info as part of the panic.
+ */
+static int s10_edac_dberr_handler(struct notifier_block *this,
+ unsigned long event, void *ptr)
+{
+   struct altr_stratix10_edac *edac = to_s10edac(this, panic_notifier);
+   int err_addr, dberror;
+
+   s10_protected_reg_read(edac, S10_SYSMGR_ECC_INTSTAT_DERR_OFST,
+  );
+   /* Remember the UE Errors for a reboot */
+   s10_protected_reg_write(edac, S10_SYSMGR_UE_VAL_OFST, dberror);
+   if (dberror & S10_DDR0_IRQ_MASK) {
+   s10_protected_reg_read(edac, S10_DERRADDR_OFST, _addr);
+   /* Remember the UE Error address */
+   s10_protected_reg_write(edac, S10_SYSMGR_UE_ADDR_OFST,
+   err_addr);
+   edac_printk(KERN_ERR, EDAC_MC,
+   "EDAC: [Uncorrectable errors @ 0x%08X]\n\n",
+   err_addr);
+   }
+
+   return NOTIFY_DONE;
+}
+
 static void altr_edac_s10_irq_handler(struct irq_desc *desc)
 {
-   int dberr, bit, sm_offset, irq_status;
struct altr_stratix10_edac *edac = irq_desc_get_handler_data(desc);
struct irq_chip *chip = irq_desc_get_chip(desc);
int irq = irq_desc_get_irq(desc);
+   int bit, sm_offset, irq_status;
 
-   dberr = (irq == edac->db_irq) ? 1 : 0;
-   sm_offset = dberr ? S10_SYSMGR_ECC_INTSTAT_DERR_OFST :
-   S10_SYSMGR_ECC_INTSTAT_SERR_OFST;
+   sm_offset = S10_SYSMGR_ECC_INTSTAT_SERR_OFST;
 
chained_irq_enter(chip, desc);
 
s10_protected_reg_read(NULL, sm_offset, _status);
 
for_each_set_bit(bit, (unsigned long *)_status, 32) {
-   irq = irq_linear_revmap(edac->domain, dberr * 32 + bit);
+   irq = irq_linear_revmap(edac->domain, bit);
if (irq)
generic_handle_irq(irq);
}
@@ -2297,6 +2332,7 @@ static int altr_edac_s10_probe(struct platform_device 
*pdev)
 {
struct altr_stratix10_edac *edac;
struct device_node *child;
+   int dberror, err_addr;
 
edac = devm_kzalloc(>dev, sizeof(*edac), GFP_KERNEL);
if (!edac)
@@ -2326,11 +2362,22 @@ static int altr_edac_s10_probe(struct platform_device 
*pdev)
 altr_edac_s10_irq_handler,
 edac);
 
-   edac->db_irq = platform_get_irq(pdev, 1);
-   if (edac->db_irq >= 0)
-   irq_set_chained_handler_and_data(edac->db_irq,
-altr_edac_s10_irq_handler,
-

[linux-yocto] [PATCH 1/3] Documentation: dt: edac: Move Altera SOCFPGA EDAC file

[Meng.Li]

From: Limeng 

commit  f8eb0edeb8c19aba667a087b80706bf4f61f8256 from
https://github.com/altera-opensource/linux-socfpga.git

Move the Altera SOCFPGA EDAC file from bindings/arm/altera to
bindings/edac.

Signed-off-by: Thor Thayer 
Requested-by: Rob Herring 
Acked-by: Rob Herring 
Cc: Mark Rutland 
Cc: devicet...@vger.kernel.org
Cc: linux-edac 
Link: 
http://lkml.kernel.org/r/1525203036-21774-1-git-send-email-thor.tha...@linux.intel.com
Signed-off-by: Borislav Petkov 
Signed-off-by: Meng Li 
---
 .../bindings/arm/altera/socfpga-eccmgr.txt | 275 -
 .../devicetree/bindings/edac/socfpga-eccmgr.txt| 275 +
 2 files changed, 275 insertions(+), 275 deletions(-)
 delete mode 100644 
Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
 create mode 100644 Documentation/devicetree/bindings/edac/socfpga-eccmgr.txt

diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt 
b/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
deleted file mode 100644
index fe582f6..000
--- a/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
+++ /dev/null
@@ -1,275 +0,0 @@
-Altera SoCFPGA ECC Manager
-This driver uses the EDAC framework to implement the SOCFPGA ECC Manager.
-The ECC Manager counts and corrects single bit errors and counts/handles
-double bit errors which are uncorrectable.
-
-Cyclone5 and Arria5 ECC Manager
-Required Properties:
-- compatible : Should be "altr,socfpga-ecc-manager"
-- #address-cells: must be 1
-- #size-cells: must be 1
-- ranges : standard definition, should translate from local addresses
-
-Subcomponents:
-
-L2 Cache ECC
-Required Properties:
-- compatible : Should be "altr,socfpga-l2-ecc"
-- reg : Address and size for ECC error interrupt clear registers.
-- interrupts : Should be single bit error interrupt, then double bit error
-   interrupt. Note the rising edge type.
-
-On Chip RAM ECC
-Required Properties:
-- compatible : Should be "altr,socfpga-ocram-ecc"
-- reg : Address and size for ECC error interrupt clear registers.
-- iram : phandle to On-Chip RAM definition.
-- interrupts : Should be single bit error interrupt, then double bit error
-   interrupt. Note the rising edge type.
-
-Example:
-
-   eccmgr: eccmgr@ffd08140 {
-   compatible = "altr,socfpga-ecc-manager";
-   #address-cells = <1>;
-   #size-cells = <1>;
-   ranges;
-
-   l2-ecc@ffd08140 {
-   compatible = "altr,socfpga-l2-ecc";
-   reg = <0xffd08140 0x4>;
-   interrupts = <0 36 1>, <0 37 1>;
-   };
-
-   ocram-ecc@ffd08144 {
-   compatible = "altr,socfpga-ocram-ecc";
-   reg = <0xffd08144 0x4>;
-   iram = <>;
-   interrupts = <0 178 1>, <0 179 1>;
-   };
-   };
-
-Arria10 SoCFPGA ECC Manager
-The Arria10 SoC ECC Manager handles the IRQs for each peripheral
-in a shared register instead of individual IRQs like the Cyclone5
-and Arria5. Therefore the device tree is different as well.
-
-Required Properties:
-- compatible : Should be "altr,socfpga-a10-ecc-manager"
-- altr,sysgr-syscon : phandle to Arria10 System Manager Block
-   containing the ECC manager registers.
-- #address-cells: must be 1
-- #size-cells: must be 1
-- interrupts : Should be single bit error interrupt, then double bit error
-   interrupt.
-- interrupt-controller : boolean indicator that ECC Manager is an interrupt 
controller
-- #interrupt-cells : must be set to 2.
-- ranges : standard definition, should translate from local addresses
-
-Subcomponents:
-
-L2 Cache ECC
-Required Properties:
-- compatible : Should be "altr,socfpga-a10-l2-ecc"
-- reg : Address and size for ECC error interrupt clear registers.
-- interrupts : Should be single bit error interrupt, then double bit error
-   interrupt, in this order.
-
-On-Chip RAM ECC
-Required Properties:
-- compatible : Should be "altr,socfpga-a10-ocram-ecc"
-- reg: Address and size for ECC block registers.
-- interrupts : Should be single bit error interrupt, then double bit error
-   interrupt, in this order.
-
-Ethernet FIFO ECC
-Required Properties:
-- compatible  : Should be "altr,socfpga-eth-mac-ecc"
-- reg : Address and size for ECC block registers.
-- altr,ecc-parent : phandle to parent Ethernet node.
-- interrupts  : Should be single bit error interrupt, then double bit error
-   interrupt, in this order.
-
-NAND FIFO ECC
-Required Properties:
-- compatible  : Should be "altr,socfpga-nand-ecc"
-- reg : Address and size for ECC block registers.
-- altr,ecc-parent : phandle to parent NAND node.
-- interrupts  : Should be single bit error interrupt, then double bit error
-   interrupt, in this order.
-
-DMA FIFO ECC
-Required Properties:
-- compatible  : Should be 

[linux-yocto] [PATCH] arm64: dts: stratix10: move dts node gpio_fpga into board specific dts file.

[Meng.Li]

From: Limeng 

The FPGA IO peripheral is only in specific FPGA design on Intel-PSG Stratix10
development board, and not all FPGA designs include FPGA IO. In addtional, this
part of resource <0xf9001080 0x4> is able to be used for any peripheral.

Therefore, move the dts node gpio_fpga from header file socfpga_stratix10.dtsi
into board specific dts file

Signed-off-by: Meng Li 
---
 arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi  | 16 
 arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts | 16 
 2 files changed, 16 insertions(+), 16 deletions(-)

diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi 
b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
index 1cdd800..dd266d5 100644
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
@@ -662,22 +662,6 @@
};
};
 
-   gpio_fpga: gpio@f9001080 {
-   #address-cells = <1>;
-   #size-cells = <0>;
-   compatible = "snps,dw-apb-gpio";
-   reg = <0xf9001080 0x4>;
-   status = "disabled";
-
-   portfpga: gpio-controller@0 {
-   compatible = "snps,dw-apb-gpio-port";
-   gpio-controller;
-   #gpio-cells = <2>;
-   snps,nr-gpios = <8>;
-   reg = <0>;
-   };
-   };
-
i2c0: i2c@ffc02800 {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts 
b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
index f6da74a..745e78c 100644
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
@@ -67,6 +67,22 @@
};
};
};
+
+   gpio_fpga: gpio@f9001080 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   compatible = "snps,dw-apb-gpio";
+   reg = <0xf9001080 0x4>;
+   status = "disabled";
+
+   portfpga: gpio-controller@0 {
+   compatible = "snps,dw-apb-gpio-port";
+   gpio-controller;
+   #gpio-cells = <2>;
+   snps,nr-gpios = <8>;
+   reg = <0>;
+   };
+   };
};
 };
 
-- 
2.7.4

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[linux-yocto] : [yocto-4.12]: intel-socfpga: arm64: dts: stratix10: move dts node gpio_fpga into board specific dts file.

[Meng.Li]

From: Limeng 


Hi Bruce,

The FPGA IO peripheral is only in specific FPGA design on Intel-PSG Stratix10
development board, and not all FPGA designs include FPGA IO. In addtional, this
part of resource <0xf9001080 0x4> is able to be used for any peripheral.

Therefore, move the dts node gpio_fpga from header file socfpga_stratix10.dtsi
into board specific dts file

patches as below:
0001-arm64-dts-stratix10-move-dts-node-gpio_fpga-into-boa.patch

Please help to meger this patch into linux-yocto, kernel 4.12, branch is 
standard/base

 socfpga_stratix10.dtsi  |   16 
 socfpga_stratix10_socdk.dts |   16 
 2 files changed, 16 insertions(+), 16 deletions(-)


thanks,
Limeng
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[linux-yocto] [PATCH 2/2] spi-nor: add support for mx25u51245g

[Meng.Li]

From: Marian Florea 

Signed-off-by: Marian Florea 
Signed-off-by: Meng Li 
---
 drivers/mtd/spi-nor/spi-nor.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 8ea66cc..6eac6f1 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -1025,6 +1025,7 @@ static const struct flash_info spi_nor_ids[] = {
{ "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, 0) },
{ "mx25u25635f", INFO(0xc22539, 0, 64 * 1024, 512, SECT_4K | 
SPI_NOR_4B_OPCODES) },
{ "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
+   { "mx25u51245g", INFO(0xc2253a, 0, 64 * 1024, 1024, SECT_4K | 
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_QUAD_READ) 
},
{ "mx66l1g55g",  INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) 
},
 { "mx66u2g45g",  INFO(0xc2253c, 0, 64 * 1024, 4096, SECT_4K | 
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
-- 
2.7.4

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[linux-yocto] : [yocto-4.12]: intel-socfpga: driver: spi-nor: add new spi-norflash support

[Meng.Li]

From: Limeng 


Hi Bruce,

Add 2 spi-norflash support  Stratix10 SoC platform.
Macronix 512Mb MX25U51245GXDI00
Macronix 2Gb MX66U2G45G 

patches as below:
0001-spi-nor-add-support-for-mx66u2g45g.patch
0002-spi-nor-add-support-for-mx25u51245g.patch

Please help to meger the 2 patches into linux-yocto, kernel 4.12, branch is 
standard/base

spi-nor.c |2 ++
1 file changed, 2 insertions(+)


thanks,
Limeng
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[linux-yocto] [PATCH 1/2] spi-nor: add support for mx66u2g45g

[Meng.Li]

From: Marian Florea 

Add support for Macronix 2GB flash device.

Upstream-Status: Pending

Signed-off-by: Marian Florea 
Signed-off-by: Meng Li 
---
 drivers/mtd/spi-nor/spi-nor.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 6a6d0c3..8ea66cc 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -1027,6 +1027,7 @@ static const struct flash_info spi_nor_ids[] = {
{ "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
{ "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_QUAD_READ) 
},
{ "mx66l1g55g",  INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) 
},
+{ "mx66u2g45g",  INFO(0xc2253c, 0, 64 * 1024, 4096, SECT_4K | 
SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 
/* Micron */
{ "n25q016a",INFO(0x20bb15, 0, 64 * 1024,   32, SECT_4K | 
SPI_NOR_QUAD_READ) },
-- 
2.7.4

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[linux-yocto] [PATCH 11/14] FogBugz #554835-3: Intel RSU binding documentation

[Meng.Li]

From: David Koltak 

commit 800553eb887b2477bed3693e931c6aadf484eefb from
https://github.com/altera-opensource/linux-socfpga.git

Documentation showing the proper device tree node
and binding for the Intel Remote System Update (RSU)
driver for Stratix 10 SoC FPGAs.

Signed-off-by: David Koltak 
Signed-off-by: Meng Li 
---
 .../bindings/firmware/intel,stratix10-rsu.txt  | 28 ++
 1 file changed, 28 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/firmware/intel,stratix10-rsu.txt

diff --git a/Documentation/devicetree/bindings/firmware/intel,stratix10-rsu.txt 
b/Documentation/devicetree/bindings/firmware/intel,stratix10-rsu.txt
new file mode 100644
index 000..9df6f89
--- /dev/null
+++ b/Documentation/devicetree/bindings/firmware/intel,stratix10-rsu.txt
@@ -0,0 +1,28 @@
+Intel Remote System Update (RSU) for Stratix10 SoC FPGAs
+
+The Intel Remote System Update (RSU) driver exposes interfaces
+accessed through the Intel Service Layer to user space via SysFS
+device attribute nodes. The RSU interfaces report/control some of
+the optional RSU features of the Stratix 10 SoC FPGA.
+
+The RSU feature provides a way for customers to update the boot
+configuration of a Stratix 10 SoC device with significantly reduced
+risk of corrupting the bitstream storage and bricking the system.
+
+Required properties:
+---
+The intel-rsu node has the following mandatory properties and must be located
+under the firmware/svc node.
+
+- compatible: "intel,stratix10-rsu"
+
+Example:
+---
+
+   firmware {
+   svc {
+   rsu {
+   compatible = "intel,stratix10-rsu";
+   };
+   };
+   };
-- 
2.7.4

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[linux-yocto] [PATCH 14/14] intel-socfpga: dts: improve qspi node for rsu feature

[Meng.Li]

From: Limeng 

There are 2 modification in qspi node for rsu feature as below:
- The QSPI read delay must be changed from the default of 3 to 1
   in order to make sure it works on Stratix10 platform.
- The MTD partition used by LIBRSU must start at the beginning
   of SPT0(sub-partition table 0) in flash

Signed-off-by: Meng Li 
---
 arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts 
b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
index 533b4cb..f6da74a 100644
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
@@ -155,7 +155,7 @@
m25p,fast-read;
cdns,page-size = <256>;
cdns,block-size = <16>;
-   cdns,read-delay = <3>;
+   cdns,read-delay = <1>;
cdns,tshsl-ns = <50>;
cdns,tsd2d-ns = <50>;
cdns,tchsh-ns = <4>;
@@ -164,7 +164,7 @@
partition@qspi-boot {
label = "Boot and fpga data";
/* 64MB for boot and FPGA data */
-   reg = <0x0 0x400>;
+   reg = <0x0091 0x036F>;
};
 
partition@qspi-rootfs {
-- 
2.7.4

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[linux-yocto] [PATCH 13/14] intel-socfpga: dts: add rsu node to enable rsu driver

[Meng.Li]

From: Limeng 

Add a corresponding dts node in socfpga_stratix10.dtsi to enable
rsu drvier.

Signed-off-by: Meng Li 
---
 arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi 
b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
index 375d68a..1cdd800 100644
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
@@ -968,6 +968,9 @@
compatible = "intel,stratix10-svc";
method = "smc";
memory-region = <_reserved>;
+   rsu {
+   compatible = "intel,stratix10-rsu";
+   };
};
};
};
-- 
2.7.4

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[linux-yocto] [PATCH 12/14] FogBugz #514234: arm64: dts: stratix10: Add PL330 DMA to Stratix10 dts

[Meng.Li]

From: Graham Moore 

commit 8927da5c28eeb5c36f969860b3945c0adb7cdb14 from
https://github.com/altera-opensource/linux-socfpga.git

This patch is part of the bringup of the Stratix10 SoC.  It depends upon
Uboot to take the PL330 out of reset in non-secure mode.

Signed-off-by: Graham Moore 
Signed-off-by: Meng Li 
---
 arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 19 +++
 1 file changed, 19 insertions(+)

diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi 
b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
index 83f4f35..375d68a 100644
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
@@ -752,6 +752,25 @@
reg = <0xffe0 0x10>;
};
 
+   pdma: pdma@ffda {
+   compatible = "arm,pl330", "arm,primecell";
+   reg = <0xffda 0x1000>;
+   interrupts = <0 81 4>,
+<0 82 4>,
+<0 83 4>,
+<0 84 4>,
+<0 85 4>,
+<0 86 4>,
+<0 87 4>,
+<0 88 4>,
+<0 89 4>;
+   #dma-cells = <1>;
+   #dma-channels = <8>;
+   #dma-requests = <32>;
+   clocks = <_main_clk>;
+   clock-names = "apb_pclk";
+   };
+
rst: rstmgr@ffd11000 {
#reset-cells = <1>;
compatible = "altr,rst-mgr";
-- 
2.7.4

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[linux-yocto] [PATCH 08/14] FogBugz #549288-3: edac: Add support for Stratix10 SDRAM EDAC

[Meng.Li]

From: Thor Thayer 

commit a2884ad40e8120fe44c268f48b162e4fcff68feb from
https://github.com/altera-opensource/linux-socfpga.git

edac: altera: Add support for Stratix10 SDRAM EDAC

Support for Stratix10 SDRAM ECC requires the use of SMC
calls to a higher priority exception level.

Signed-off-by: Thor Thayer 
Signed-off-by: Meng Li 
---
 drivers/edac/Kconfig   |   2 +-
 drivers/edac/altera_edac.c | 455 +++--
 drivers/edac/altera_edac.h | 126 +++--
 3 files changed, 555 insertions(+), 28 deletions(-)

diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index 96afb2a..8ed7bc2 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -379,7 +379,7 @@ config EDAC_THUNDERX
 
 config EDAC_ALTERA
bool "Altera SOCFPGA ECC"
-   depends on EDAC=y && ARCH_SOCFPGA
+   depends on EDAC=y && (ARCH_SOCFPGA || ARCH_STRATIX10)
help
  Support for error detection and correction on the
  Altera SOCs. This must be selected for SDRAM ECC.
diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c
index 7717b094..fcd0c95 100644
--- a/drivers/edac/altera_edac.c
+++ b/drivers/edac/altera_edac.c
@@ -1,20 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
+ *  Copyright (C) 2017-2018, Intel Corporation. All rights reserved
  *  Copyright Altera Corporation (C) 2014-2016. All rights reserved.
  *  Copyright 2011-2012 Calxeda, Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program.  If not, see .
- *
- * Adapted from the highbank_mc_edac driver.
  */
 
 #include 
@@ -81,6 +69,25 @@ static const struct altr_sdram_prv_data a10_data = {
.ue_set_mask= A10_DIAGINT_TDERRA_MASK,
 };
 
+static const struct altr_sdram_prv_data s10_data = {
+   .ecc_ctrl_offset= S10_ECCCTRL1_OFST,
+   .ecc_ctl_en_mask= A10_ECCCTRL1_ECC_EN,
+   .ecc_stat_offset= S10_INTSTAT_OFST,
+   .ecc_stat_ce_mask   = A10_INTSTAT_SBEERR,
+   .ecc_stat_ue_mask   = A10_INTSTAT_DBEERR,
+   .ecc_saddr_offset   = S10_SERRADDR_OFST,
+   .ecc_daddr_offset   = S10_DERRADDR_OFST,
+   .ecc_irq_en_offset  = S10_ERRINTEN_OFST,
+   .ecc_irq_en_mask= A10_ECC_IRQ_EN_MASK,
+   .ecc_irq_clr_offset = S10_INTSTAT_OFST,
+   .ecc_irq_clr_mask   = (A10_INTSTAT_SBEERR | A10_INTSTAT_DBEERR),
+   .ecc_cnt_rst_offset = S10_ECCCTRL1_OFST,
+   .ecc_cnt_rst_mask   = A10_ECC_CNT_RESET_MASK,
+   .ce_ue_trgr_offset  = S10_DIAGINTTEST_OFST,
+   .ce_set_mask= A10_DIAGINT_TSERRA_MASK,
+   .ue_set_mask= A10_DIAGINT_TDERRA_MASK,
+};
+
 /*** EDAC Memory Controller Functions /
 
 /* The SDRAM controller uses the EDAC Memory Controller framework.   */
@@ -240,6 +247,7 @@ static unsigned long get_total_mem(void)
 static const struct of_device_id altr_sdram_ctrl_of_match[] = {
{ .compatible = "altr,sdram-edac", .data = _data},
{ .compatible = "altr,sdram-edac-a10", .data = _data},
+   { .compatible = "altr,sdram-edac-s10", .data = _data},
{},
 };
 MODULE_DEVICE_TABLE(of, altr_sdram_ctrl_of_match);
@@ -487,6 +495,285 @@ static int altr_sdram_remove(struct platform_device *pdev)
return 0;
 }
 
+/ Stratix 10 EDAC Memory Controller Functions /
+
+/**
+ * s10_protected_reg_write
+ * Write to a protected SMC register.
+ * @context: Not used.
+ * @reg: Address of register
+ * @value: Value to write
+ * Return: INTEL_SIP_SMC_STATUS_OK (0) on success
+ *INTEL_SIP_SMC_REG_ERROR on error
+ *INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION if not supported
+ */
+static int s10_protected_reg_write(void *context, unsigned int reg,
+  unsigned int val)
+{
+   struct arm_smccc_res result;
+
+   arm_smccc_smc(INTEL_SIP_SMC_REG_WRITE, reg, val, 0, 0,
+ 0, 0, 0, );
+
+   return (int)result.a0;
+}
+
+/**
+ * s10_protected_reg_read
+ * Read the status of a protected SMC register
+ * @context: Not used.
+ * @reg: Address of register
+ * @value: Value read.
+ * Return: INTEL_SIP_SMC_STATUS_OK (0) on success
+ *INTEL_SIP_SMC_REG_ERROR on error
+ *INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION if not supported
+ */
+static int s10_protected_reg_read(void *context, unsigned int reg,
+ unsigned int *val)

[linux-yocto] [PATCH 10/14] FogBugz #554835-1: Add Stratix 10 SoC RSU Driver

[Meng.Li]

From: David Koltak 

commit 000af215119d8a7ccb469d49535a59a5dbb12ad7 from
https://github.com/altera-opensource/linux-socfpga.git

Add a kernel driver to expose interfaces required to
support the Remote System Update (RSU) feature of Stratix
10 SoC FPGAs.  The driver uses SysFS device attribute nodes.
The accesses are performed through the intel-service layer.

Signed-off-by: David Koltak 
Signed-off-by: Meng Li 
---
 drivers/misc/Kconfig |  17 ++
 drivers/misc/Makefile|   1 +
 drivers/misc/intel-rsu.c | 377 +++
 drivers/misc/intel-service.c |  51 -
 drivers/misc/intel-smc.h |  41 
 include/linux/intel-service-client.h |  15 +-
 6 files changed, 498 insertions(+), 4 deletions(-)
 create mode 100644 drivers/misc/intel-rsu.c

diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 5a48b8a..02f3359 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -151,6 +151,23 @@ config INTEL_SERVICE
 
  Say Y here if you want Intel service layer support.
 
+config INTEL_RSU
+   tristate "Intel Remote System Update"
+   depends on INTEL_SERVICE
+   help
+ The Intel Remote System Update (RSU) driver exposes interfaces
+ accessed through the Intel Service Layer to user space via SysFS
+ device attribute nodes. The RSU interfaces report/control some of
+ the optional RSU features of the Stratix 10 SoC FPGA.
+
+ The RSU feature provides a way for customers to update the boot
+ configuration of a Stratix 10 SoC device with significantly reduced
+ risk of corrupting the bitstream storage and bricking the system.
+
+ Enable RSU support if you are using an Intel SoC FPGA with the RSU
+ feature enabled and you want Linux user space control.
+
+ Say Y here if you want Intel RSU support.
 
 config SGI_IOC4
tristate "SGI IOC4 Base IO support"
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 0cbc82f..837d9f0 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_AD525X_DPOT_I2C)   += ad525x_dpot-i2c.o
 obj-$(CONFIG_AD525X_DPOT_SPI)  += ad525x_dpot-spi.o
 obj-$(CONFIG_INTEL_MID_PTI)+= pti.o
 obj-$(CONFIG_INTEL_SERVICE) += intel-service.o
+obj-$(CONFIG_INTEL_RSU)+= intel-rsu.o
 obj-$(CONFIG_ATMEL_SSC)+= atmel-ssc.o
 obj-$(CONFIG_ATMEL_TCLIB)  += atmel_tclib.o
 obj-$(CONFIG_DUMMY_IRQ)+= dummy-irq.o
diff --git a/drivers/misc/intel-rsu.c b/drivers/misc/intel-rsu.c
new file mode 100644
index 000..4dc834b
--- /dev/null
+++ b/drivers/misc/intel-rsu.c
@@ -0,0 +1,377 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 Intel Corporation
+ */
+
+/*
+ * This driver exposes some optional features of the Intel Stratix 10 SoC FPGA.
+ * The SysFS interfaces exposed here are FPGA Remote System Update (RSU)
+ * related.  They allow user space software to query the configuration system
+ * status and to request optional reboot behavior specific to Intel FPGAs.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define MAX_U64_STR_LEN 22
+
+/*
+ * Private data structure
+ */
+struct intel_rsu_priv {
+   struct intel_svc_chan *chan;
+   struct intel_svc_client client;
+   struct completion svc_completion;
+   struct {
+   unsigned long current_image;
+   unsigned long fail_image;
+   unsigned int version;
+   unsigned int state;
+   unsigned int error_details;
+   unsigned int error_location;
+   } status;
+};
+
+/*
+ * status_svc_callback() - Callback from intel-service layer that returns SMC
+ * response with RSU status data. Parses up data and
+ * update driver private data structure.
+ * client - returned context from intel-service layer
+ * data - SMC response data
+ */
+static void status_svc_callback(struct intel_svc_client *client,
+   struct intel_svc_c_data *data)
+{
+   struct intel_rsu_priv *priv = client->priv;
+   struct arm_smccc_res *res = (struct arm_smccc_res *)data->kaddr1;
+
+   if (data->status == BIT(SVC_STATUS_RSU_OK)) {
+   priv->status.version =
+   (unsigned int)(res->a2 >> 32) & 0x;
+   priv->status.state = (unsigned int)res->a2 & 0x;
+   priv->status.fail_image = res->a1;
+   priv->status.current_image = res->a0;
+   priv->status.error_location =
+   (unsigned int)res->a3 & 0x;
+   priv->status.error_details =
+   (unsigned int)(res->a3 >> 32) & 0x;
+   } else {
+   dev_err(client->dev, 

[linux-yocto] [PATCH 09/14] FogBugz #549288-4: dts: add Stratix10 sdram ecc

[Meng.Li]

From: Thor Thayer 

commit aa9b366a54171468663f221ae46baa6e34c35288 from
https://github.com/altera-opensource/linux-socfpga.git

arm64: dts: stratix10: add sdram ecc

Add the Stratix10 ECC Manager and SDRAM EDAC nodes to the
device tree.

Signed-off-by: Thor Thayer 
Signed-off-by: Meng Li 
---
 arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 15 +++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi 
b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
index dc0a4a6..83f4f35 100644
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
@@ -913,6 +913,21 @@
status = "disabled";
};
 
+   eccmgr: eccmgr {
+   compatible = "altr,socfpga-s10-ecc-manager";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   interrupts = <0 15 4>, <0 95 4>;
+   interrupt-controller;
+   #interrupt-cells = <2>;
+   ranges;
+
+   sdramedac {
+   compatible = "altr,sdram-edac-s10";
+   interrupts = <16 4>, <48 4>;
+   };
+   };
+
qspi: spi@ff8d2000 {
compatible = "cdns,qspi-nor";
#address-cells = <1>;
-- 
2.7.4

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[linux-yocto] [PATCH 05/14] mtd: spi-nor: cadence-quadspi: Fix page fault kernel panic

[Meng.Li]

From: Thor Thayer 

commit c1de85b2b1dd9dcad21a2514fca327d74d03b571 from
https://github.com/altera-opensource/linux-socfpga.git

[backport 'commit 47016b341fc3 ("mtd: spi-nor: cadence-quadspi:
 Fix page fault kernel panic")']

Backported from spi-nor-next/master

The current Cadence QSPI driver caused a kernel panic when loading
a Root Filesystem from QSPI. The problem was caused by reading more
bytes than needed because the QSPI operated on 4 bytes at a time.

[7.947754] spi_nor_read[1048]:from 0x037cad74, len 1 [bfe07fff]
[7.956247] cqspi_read[910]:offset 0x58502516, buffer=bfe07fff
[7.956247]
[7.966046] Unable to handle kernel paging request at virtual
address bfe08002
[7.973239] pgd = eebfc000
[7.975931] [bfe08002] *pgd=2fffb811, *pte=, *ppte=

Notice above how only 1 byte needed to be read but by reading 4 bytes
into the end of a mapped page, an unrecoverable page fault occurred.

This patch uses a temporary buffer to hold the 4 bytes read and then
copies only the bytes required into the buffer. A min() function is
used to limit the length to prevent buffer overflows.

Request testing of this patch on other platforms. This was tested
on the Intel Arria10 SoCFPGA DevKit.

Fixes: 0cf1725676a97fc8 ("mtd: spi-nor: cqspi: Fix build on arches missing 
readsl/writesl")
Signed-off-by: Thor Thayer 
Cc: 
Reviewed-by: Marek Vasut 
Signed-off-by: Boris Brezillon 
Signed-off-by: Meng Li 
---
 drivers/mtd/spi-nor/cadence-quadspi.c | 19 +--
 1 file changed, 17 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c 
b/drivers/mtd/spi-nor/cadence-quadspi.c
index 9f8102d..0404898 100644
--- a/drivers/mtd/spi-nor/cadence-quadspi.c
+++ b/drivers/mtd/spi-nor/cadence-quadspi.c
@@ -495,7 +495,9 @@ static int cqspi_indirect_read_execute(struct spi_nor *nor,
void __iomem *reg_base = cqspi->iobase;
void __iomem *ahb_base = cqspi->ahb_base;
unsigned int remaining = n_rx;
+   unsigned int mod_bytes = n_rx % 4;
unsigned int bytes_to_read = 0;
+   u8 *rxbuf_end = rxbuf + n_rx;
int ret = 0;
 
writel(remaining, reg_base + CQSPI_REG_INDIRECTRDBYTES);
@@ -523,11 +525,24 @@ static int cqspi_indirect_read_execute(struct spi_nor 
*nor,
}
 
while (bytes_to_read != 0) {
+   unsigned int word_remain = round_down(remaining, 4);
+
bytes_to_read *= cqspi->fifo_width;
bytes_to_read = bytes_to_read > remaining ?
remaining : bytes_to_read;
-   ioread32_rep(ahb_base, rxbuf,
-DIV_ROUND_UP(bytes_to_read, 4));
+   bytes_to_read = round_down(bytes_to_read, 4);
+   /* Read 4 byte word chunks then single bytes */
+   if (bytes_to_read) {
+   ioread32_rep(ahb_base, rxbuf,
+(bytes_to_read / 4));
+   } else if (!word_remain && mod_bytes) {
+   unsigned int temp = ioread32(ahb_base);
+
+   bytes_to_read = mod_bytes;
+   memcpy(rxbuf, , min((unsigned int)
+(rxbuf_end - rxbuf),
+bytes_to_read));
+   }
rxbuf += bytes_to_read;
remaining -= bytes_to_read;
bytes_to_read = cqspi_get_rd_sram_level(cqspi);
-- 
2.7.4

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[linux-yocto] [PATCH 06/14] FogBugz #549288-1: misc: Stratix10 Protected register access defines

[Meng.Li]

From: Thor Thayer 

commit da941c6dc017d0eebf0d7c72d9a84231c5447c61 from
https://github.com/altera-opensource/linux-socfpga.git

Add the defines for the Stratix10 Protected register
accesses. This syncs with the U-Boot version of this
file.

Signed-off-by: Thor Thayer 
Signed-off-by: Meng Li 
---
 drivers/misc/intel-smc.h | 64 
 1 file changed, 64 insertions(+)

diff --git a/drivers/misc/intel-smc.h b/drivers/misc/intel-smc.h
index 0b92560..d92dcd7 100644
--- a/drivers/misc/intel-smc.h
+++ b/drivers/misc/intel-smc.h
@@ -66,12 +66,17 @@
  *
  * INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR:
  * There is error during the FPGA configuration process.
+ *
+ * INTEL_SIP_SMC_REG_ERROR:
+ * There is error during a read or write operation of the protected
+ * registers.
  */
 #define INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION  0x
 #define INTEL_SIP_SMC_STATUS_OK0x0
 #define INTEL_SIP_SMC_FPGA_CONFIG_STATUS_BUSY  0x1
 #define INTEL_SIP_SMC_FPGA_CONFIG_STATUS_REJECTED   0x2
 #define INTEL_SIP_SMC_FPGA_CONFIG_STATUS_ERROR 0x4
+#define INTEL_SIP_SMC_REG_ERROR0x5
 
 /*
  * Request INTEL_SIP_SMC_FPGA_CONFIG_START
@@ -202,4 +207,63 @@ 
INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_COMPLETED_WRITE)
 #define INTEL_SIP_SMC_FPGA_CONFIG_LOOPBACK \
INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_FPGA_CONFIG_LOOPBACK)
 
+/*
+ * Request INTEL_SIP_SMC_REG_READ
+ *
+ * Read a protected register using SMCCC
+ *
+ * Call register usage:
+ * a0: INTEL_SIP_SMC_REG_READ.
+ * a1: register address.
+ * a2-7: not used.
+ *
+ * Return status:
+ * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_REG_ERROR.
+ * a1: Value in the register
+ * a2-3: not used.
+ */
+#define INTEL_SIP_SMC_FUNCID_REG_READ 7
+#define INTEL_SIP_SMC_REG_READ \
+   INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_REG_READ)
+
+/*
+ * Request INTEL_SIP_SMC_REG_WRITE
+ *
+ * Write a protected register using SMCCC
+ *
+ * Call register usage:
+ * a0: INTEL_SIP_SMC_REG_WRITE.
+ * a1: register address
+ * a2: value to program into register.
+ * a3-7: not used.
+ *
+ * Return status:
+ * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_REG_ERROR.
+ * a1-3: not used.
+ */
+#define INTEL_SIP_SMC_FUNCID_REG_WRITE 8
+#define INTEL_SIP_SMC_REG_WRITE \
+   INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_REG_WRITE)
+
+/*
+ * Request INTEL_SIP_SMC_FUNCID_REG_UPDATE
+ *
+ * Update one or more bits in a protected register using a
+ * read-modify-write operation.
+ *
+ * Call register usage:
+ * a0: INTEL_SIP_SMC_REG_UPDATE.
+ * a1: register address
+ * a2: Write Mask.
+ * a3: Value to write.
+ * a4-7: not used.
+ *
+ * Return status:
+ * a0: INTEL_SIP_SMC_STATUS_OK or INTEL_SIP_SMC_REG_ERROR.
+ * a1-3: Not used.
+ */
+#define INTEL_SIP_SMC_FUNCID_REG_UPDATE 9
+#define INTEL_SIP_SMC_REG_UPDATE \
+   INTEL_SIP_SMC_FAST_CALL_VAL(INTEL_SIP_SMC_FUNCID_REG_UPDATE)
+
 #endif
-- 
2.7.4

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[linux-yocto] [PATCH 07/14] FogBugz #549288-2: Add Stratix10 ECC Manager binding

[Meng.Li]

From: Thor Thayer 

commit 97a3b7365253bc7757b2c885a23e4bd57be9d25b from
https://github.com/altera-opensource/linux-socfpga.git

Documentation: dt: socfpga: Add Stratix10 ECC Manager binding

Add the device tree bindings needed to support the Stratix10
ECC Manager and SDRAM ECC.

Signed-off-by: Thor Thayer 
Signed-off-by: Meng Li 
---
 .../bindings/arm/altera/socfpga-eccmgr.txt | 42 ++
 1 file changed, 42 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt 
b/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
index 4a1714f..fe582f6 100644
--- a/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
+++ b/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
@@ -231,3 +231,45 @@ Example:
 <48 IRQ_TYPE_LEVEL_HIGH>;
};
};
+
+Stratix10 SoCFPGA ECC Manager
+The Stratix10 SoC ECC Manager handles the IRQs for each peripheral
+in a shared register similar to the Arria10. However, ECC requires
+access to registers that can only be read from Secure Monitor with
+SMC calls.
+Therefore the device tree is slightly different.
+
+Required Properties:
+- compatible : Should be "altr,socfpga-s10-ecc-manager"
+- #address-cells: must be 1
+- #size-cells: must be 1
+- interrupts : Should be single bit error interrupt, then double bit error
+   interrupt.
+- interrupt-controller : boolean indicator that ECC Manager is an interrupt 
controller
+- #interrupt-cells : must be set to 2.
+- ranges : standard definition, should translate from local addresses
+
+Subcomponents:
+
+SDRAM ECC
+Required Properties:
+- compatible : Should be "altr,sdram-edac-s10"
+- interrupts : Should be single bit error interrupt, then double bit error
+   interrupt, in this order.
+
+Example:
+
+   eccmgr: eccmgr {
+   compatible = "altr,socfpga-s10-ecc-manager";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   interrupts = <0 15 4>, <0 95 4>;
+   interrupt-controller;
+   #interrupt-cells = <2>;
+   ranges;
+
+   sdramedac {
+   compatible = "altr,sdram-edac-s10";
+   interrupts = <16 4>, <48 4>;
+   };
+   };
-- 
2.7.4

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[linux-yocto] [PATCH 02/14] FogBugz #251539-2: dts: Add Altera Quad SPI Driver Device Tree Binding

[Meng.Li]

From: VIET NGA DAO 

commit 990acaf14261901a67c96f2effab389556d87c60 from
https://github.com/altera-opensource/linux-socfpga.git

This patch adds Device Tree Binding for Altera Quad SPI Driver.

Signed-off-by: Viet Nga Dao 
Signed-off-by: Ooi, Joyce 
Signed-off-by: Meng Li 
---
 .../devicetree/bindings/mtd/altera_quadspi.txt | 42 ++
 1 file changed, 42 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mtd/altera_quadspi.txt

diff --git a/Documentation/devicetree/bindings/mtd/altera_quadspi.txt 
b/Documentation/devicetree/bindings/mtd/altera_quadspi.txt
new file mode 100644
index 000..626b602
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/altera_quadspi.txt
@@ -0,0 +1,42 @@
+* MTD Altera QUADSPI driver
+
+Required properties:
+- compatible: Should be "altr,quadspi-1.0"
+- reg: Address and length of the register set  for the device. It contains
+  the information of registers in the same order as described by reg-names
+- reg-names: Should contain the reg names
+  "avl_csr": Should contain the register configuration base address
+  "avl_mem": Should contain the data base address
+- #address-cells: Must be <1>.
+- #size-cells: Must be <0>.
+- flash device tree subnode, there must be a node with the following fields:
+   - compatible: Should contain the flash name
+   - #address-cells: please refer to /mtd/partition.txt
+   - #size-cells: please refer to /mtd/partition.txt
+   For partitions inside each flash, please refer to /mtd/partition.txt
+
+Example:
+
+   quadspi_controller_0: quadspi@0x180014a0 {
+   compatible = "altr,quadspi-1.0";
+   reg = <0x180014a0 0x0020>,
+ <0x1400 0x0400>;
+   reg-names = "avl_csr", "avl_mem";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   flash0: epcq256@0 {
+   compatible = "epcq256-nonjedec";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   partition@0 {
+   /* 16 MB for raw data. */
+   label = "EPCQ Flash 0 raw data";
+   reg = <0x0 0x100>;
+   };
+   partition@100 {
+   /* 16 MB for jffs2 data. */
+   label = "EPCQ Flash 0 JFFS 2";
+   reg = <0x100 0x100>;
+   };
+   };
+   }; //end quadspi@0x180014a0 (quadspi_controller_0)
-- 
2.7.4

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[linux-yocto] [PATCH 03/14] arm64: dts: stratix10: Change pad skew values for EMAC0 PHY driver

[Meng.Li]

From: "Ooi, Joyce" 

commit bf0c54db1dff12fbef7aedf7538a741e78328fc7 from
https://github.com/altera-opensource/linux-socfpga.git

The HPS EMAC0 drive strength is changed to 4mA because the initial 8mA
drive strength has caused CE test to fail. This requires changes on the
pad skew for EMAC0 PHY driver. Based on several measurements done, Tx
clock does not require the extra 0.96ns delay.

Signed-off-by: Ooi, Joyce 
Signed-off-by: Dinh Nguyen 
Signed-off-by: Meng Li 
---
 arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts 
b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
index ec18609..533b4cb 100644
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
@@ -92,7 +92,7 @@
rxd2-skew-ps = <420>; /* 0ps */
rxd3-skew-ps = <420>; /* 0ps */
txen-skew-ps = <0>; /* -420ps */
-   txc-skew-ps = <1860>; /* 960ps */
+   txc-skew-ps = <900>; /* 0ps */
rxdv-skew-ps = <420>; /* 0ps */
rxc-skew-ps = <1680>; /* 780ps */
max-frame-size = <3800>;
-- 
2.7.4

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[linux-yocto] [PATCH 01/14] FogBugz #251539-1: Add Altera Quad SPI Driver

[Meng.Li]

From: VIET NGA DAO 

commit 09dc2f10a87141935cfef75a8adbbe4a3928465f from
https://github.com/altera-opensource/linux-socfpga.git

This patch adds linux driver for Altera Quad SPI controller.
Quad SPI controller is a soft IP designed to access EPCS, EPCQ
and Micron flash chips.

Signed-off-by: Viet Nga Dao 
Signed-off-by: Ooi, Joyce 
Signed-off-by: Meng Li 
---
 drivers/mtd/devices/Kconfig  |   7 +
 drivers/mtd/devices/Makefile |   2 +-
 drivers/mtd/devices/altera_quadspi.c | 667 +++
 3 files changed, 675 insertions(+), 1 deletion(-)
 create mode 100644 drivers/mtd/devices/altera_quadspi.c

diff --git a/drivers/mtd/devices/Kconfig b/drivers/mtd/devices/Kconfig
index 58329d2..a0c0968 100644
--- a/drivers/mtd/devices/Kconfig
+++ b/drivers/mtd/devices/Kconfig
@@ -221,4 +221,11 @@ config BCH_CONST_T
default 4
 endif
 
+config MTD_ALTERA_QUADSPI
+   tristate "Altera Quad SPI Flash Driver"
+   help
+ This enables access to Altera EPCQ/EPCS/Micron flash chips,
+ used for data storage. See the driver source for the current list,
+ or to add other chips.
+
 endmenu
diff --git a/drivers/mtd/devices/Makefile b/drivers/mtd/devices/Makefile
index 7912d3a..b09511d 100644
--- a/drivers/mtd/devices/Makefile
+++ b/drivers/mtd/devices/Makefile
@@ -17,6 +17,6 @@ obj-$(CONFIG_MTD_SST25L)  += sst25l.o
 obj-$(CONFIG_MTD_BCM47XXSFLASH)+= bcm47xxsflash.o
 obj-$(CONFIG_MTD_ST_SPI_FSM)+= st_spi_fsm.o
 obj-$(CONFIG_MTD_POWERNV_FLASH)+= powernv_flash.o
-
+obj-$(CONFIG_MTD_ALTERA_QUADSPI) += altera_quadspi.o
 
 CFLAGS_docg3.o += -I$(src)
diff --git a/drivers/mtd/devices/altera_quadspi.c 
b/drivers/mtd/devices/altera_quadspi.c
new file mode 100644
index 000..3990b7d
--- /dev/null
+++ b/drivers/mtd/devices/altera_quadspi.c
@@ -0,0 +1,667 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define ALTERA_QUADSPI_RESOURCE_NAME   "altera_quadspi"
+
+/* max possible slots for serial flash chip in the QUADSPI controller */
+#define MAX_NUM_FLASH_CHIP 3
+#define EPCS   1
+#define NON_EPCS   2
+
+#define WRITE_CHECK1
+#define ERASE_CHECK0
+
+#define NOR_OP_RDID0x9F
+#define NOR_OP_RDSR0x05
+
+/* Define max times to check status register before we give up. */
+#define QUADSPI_MAX_TIME_OUT_USEC  4
+
+/* defines for status register */
+#define QUADSPI_SR_REG 0x0
+#define QUADSPI_SR_WIP_MASK0x0001
+#define QUADSPI_SR_WIP 0x1
+#define QUADSPI_SR_WEL 0x2
+#define QUADSPI_SR_BP0 0x4
+#define QUADSPI_SR_BP1 0x8
+#define QUADSPI_SR_BP2 0x10
+#define QUADSPI_SR_BP3 0x40
+#define QUADSPI_SR_TB  0x20
+#define QUADSPI_SR_MASK0x000F
+
+/* defines for device id register */
+#define QUADSPI_SID_REG0x4
+#define QUADSPI_RDID_REG   0x8
+#define QUADSPI_ID_MASK0x00FF
+
+/*
+ * QUADSPI_MEM_OP register offset
+ *
+ * The QUADSPI_MEM_OP register is used to do memory protect and erase 
operations
+ *
+ */
+#define QUADSPI_MEM_OP_REG 0xC
+
+#define QUADSPI_MEM_OP_CMD_MASK0x0003
+#define QUADSPI_MEM_OP_BULK_ERASE_CMD  0x0001
+#define QUADSPI_MEM_OP_SECTOR_ERASE_CMD0x0002
+#define QUADSPI_MEM_OP_SECTOR_PROTECT_CMD  0x0003
+#define QUADSPI_MEM_OP_SECTOR_VALUE_MASK   0x0003FF00
+#define QUADSPI_MEM_OP_SECTOR_PROTECT_VALUE_MASK   0x1F00
+#define QUADSPI_MEM_OP_SECTOR_PROTECT_SHIFT8
+/*
+ * QUADSPI_ISR register offset
+ *
+ * The QUADSPI_ISR register is used to determine whether an invalid write or
+ * erase operation trigerred an interrupt
+ *
+ */
+#define QUADSPI_ISR_REG0x10
+
+#define QUADSPI_ISR_ILLEGAL_ERASE_MASK 0x0001
+#define QUADSPI_ISR_ILLEGAL_WRITE_MASK 0x0002
+
+/*
+ * QUADSPI_IMR register offset
+ *
+ * The QUADSPI_IMR register is used to mask the invalid erase or the invalid
+ * write interrupts.
+ *
+ */
+#define QUADSPI_IMR_REG

[linux-yocto] [PATCH 04/14] FogBugz #554812: fpga: stratix10: unitialized data

[Meng.Li]

From: Alan Tull 

commit e85199e8db5bc5c8880f95b5e8fec05d52ddd5d0 from
https://github.com/altera-opensource/linux-socfpga.git

Address the following issue caught by static code analysis:

drivers/fpga/stratix10-soc.c:206 --  -- UNINIT.STACK.MUST
(1:Critical) Analyze 'payload.flags' is used uninitialized
in this function.

Signed-off-by: Alan Tull 
Signed-off-by: Meng Li 
---
 drivers/fpga/stratix10-soc.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/fpga/stratix10-soc.c b/drivers/fpga/stratix10-soc.c
index 9648387..2974c8e 100644
--- a/drivers/fpga/stratix10-soc.c
+++ b/drivers/fpga/stratix10-soc.c
@@ -201,6 +201,7 @@ static int s10_ops_write_init(struct fpga_manager *mgr,
uint i;
int ret;
 
+   payload.flags = 0;
if (info->flags & FPGA_MGR_PARTIAL_RECONFIG) {
dev_info(dev, "Requesting partial reconfiguration.\n");
payload.flags |= BIT(COMMAND_RECONFIG_FLAG_PARTIAL);
-- 
2.7.4

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[linux-yocto] : [yocto-4.12]: intel-socfpga: get latest patches from sdk for remote system feature

[Meng.Li]

From: Limeng 


Hi Bruce,

Now, there are some update for intel-socfpga, Stratix10 SoC from SDK.
These patches are used to implement remote system update feature.

Please help to meger below patches into linux-yocto, kernel 4.12, branch is 
standard/base
 
0001-FogBugz-251539-1-Add-Altera-Quad-SPI-Driver.patch
0002-FogBugz-251539-2-dts-Add-Altera-Quad-SPI-Driver-Devi.patch
0003-arm64-dts-stratix10-Change-pad-skew-values-for-EMAC0.patch
0004-FogBugz-554812-fpga-stratix10-unitialized-data.patch
0005-mtd-spi-nor-cadence-quadspi-Fix-page-fault-kernel-pa.patch
0006-FogBugz-549288-1-misc-Stratix10-Protected-register-a.patch
0007-FogBugz-549288-2-Add-Stratix10-ECC-Manager-binding.patch
0008-FogBugz-549288-3-edac-Add-support-for-Stratix10-SDRA.patch
0009-FogBugz-549288-4-dts-add-Stratix10-sdram-ecc.patch
0010-FogBugz-554835-1-Add-Stratix-10-SoC-RSU-Driver.patch
0011-FogBugz-554835-3-Intel-RSU-binding-documentation.patch
0012-FogBugz-514234-arm64-dts-stratix10-Add-PL330-DMA-to-.patch
0013-intel-socfpga-dts-add-rsu-node-to-enable-rsu-driver.patch
0014-intel-socfpga-dts-improve-qspi-node-for-rsu-feature.patch

Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt|   42 
Documentation/devicetree/bindings/firmware/intel,stratix10-rsu.txt |   28 
Documentation/devicetree/bindings/mtd/altera_quadspi.txt   |   42 
arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi  |   37 
arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts |6 
drivers/edac/Kconfig   |2 
drivers/edac/altera_edac.c |  455 ++
drivers/edac/altera_edac.h |  126 +
drivers/fpga/stratix10-soc.c   |1 
drivers/misc/Kconfig   |   17 
drivers/misc/Makefile  |1 
drivers/misc/intel-rsu.c   |  377 +
drivers/misc/intel-service.c   |   51 
drivers/misc/intel-smc.h   |  105 +
drivers/mtd/devices/Kconfig|7 
drivers/mtd/devices/Makefile   |2 
drivers/mtd/devices/altera_quadspi.c   |  667 
++
drivers/mtd/spi-nor/cadence-quadspi.c  |   19 
include/linux/intel-service-client.h   |   15 
19 files changed, 1962 insertions(+), 38 deletions(-)


thanks,
Limeng


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[linux-yocto] [PATCH 1/2] driver: of: configfs: fix a building warning

[Meng.Li]

From: Limeng 

Build kernel for arm64 platform, there is a warning as below:
drivers/of/configfs.c:153:34: note: format string is defined here
  pr_debug("%s: buf=%p max_count=%u\n", __func__,
 ~^
 %lu
This building warning is introduced by commit 784a7fe5585c
("OF: DT-Overlay configfs interface (v7)")

Because on arm64 platform, size_t is long unsigned int.
Therefore, change %u into %zu to compatible with arm
and arm64 platform.

Signed-off-by: Meng Li 
---
 drivers/of/configfs.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/of/configfs.c b/drivers/of/configfs.c
index c7e999c..8490d9c 100644
--- a/drivers/of/configfs.c
+++ b/drivers/of/configfs.c
@@ -150,7 +150,7 @@ ssize_t cfs_overlay_item_dtbo_read(struct config_item 
*item, void *buf,
 {
struct cfs_overlay_item *overlay = to_cfs_overlay_item(item);
 
-   pr_debug("%s: buf=%p max_count=%u\n", __func__,
+   pr_debug("%s: buf=%p max_count=%zu\n", __func__,
buf, max_count);
 
if (overlay->dtbo == NULL)
-- 
2.9.3

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[linux-yocto] [v2]: : [yocto-4.12]: intel-socfpga: update patches for Stratix10 platform

[Meng.Li]

From: Limeng 


Hi Bruce,

Now, there are 2 below patches to update intel-socfpga, Stratix10 SoC platform.
0001-driver-of-configfs-fix-a-building-warning.patch
0002-driver-misc-intel-service-schedule-thread-out-when-t.patch

Please help to meger the 2 patches into linux-yocto, kernel 4.12, branch is 
standard/base

misc/intel-service.c |5 -
of/configfs.c|2 +-
2 files changed, 5 insertions(+), 2 deletions(-)

thanks,
Limeng


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[linux-yocto] [PATCH 1/2] driver: of: configfs: fix a building warning

[Meng.Li]

From: Limeng 

Build kernel for arm64 platform, there is a waring as below:
drivers/of/configfs.c:153:34: note: format string is defined here
  pr_debug("%s: buf=%p max_count=%u\n", __func__,
 ~^
 %lu
Because on arm64 platform, size_t is long unsigned int.
Therefore, change %u into %zu to compatible with arm
and arm64 platform.

Signed-off-by: Meng Li 
---
 drivers/of/configfs.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/of/configfs.c b/drivers/of/configfs.c
index c7e999c..8490d9c 100644
--- a/drivers/of/configfs.c
+++ b/drivers/of/configfs.c
@@ -150,7 +150,7 @@ ssize_t cfs_overlay_item_dtbo_read(struct config_item 
*item, void *buf,
 {
struct cfs_overlay_item *overlay = to_cfs_overlay_item(item);
 
-   pr_debug("%s: buf=%p max_count=%u\n", __func__,
+   pr_debug("%s: buf=%p max_count=%zu\n", __func__,
buf, max_count);
 
if (overlay->dtbo == NULL)
-- 
2.9.3

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[linux-yocto] [PATCH 2/2] driver: misc: intel-service: schedule thread out when there is no data reveived

[Meng.Li]

From: MengLi 

In thread svc_normal_to_secure_thread(), function kfifo_out_spinlocked()
always return, so this thread can't release cpu even if there is no data
received, and cause cpu is under heave load status. System performance
is poor.
Therefore, schedule this thread out when there is no data reveived, and
wake it up after sending data to it.

Signed-off-by: Meng Li 
---
 drivers/misc/intel-service.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/misc/intel-service.c b/drivers/misc/intel-service.c
index 4c63330..8aa2a24 100644
--- a/drivers/misc/intel-service.c
+++ b/drivers/misc/intel-service.c
@@ -278,6 +278,7 @@ int intel_svc_send(struct intel_svc_chan *chan, void *msg)
ret = kfifo_in_spinlocked(>ctrl->svc_fifo, p_data,
  sizeof(*p_data),
  >ctrl->svc_fifo_lock);
+   wake_up_process(chan->ctrl->task);
 
kfree(p_data);
 
@@ -537,8 +538,10 @@ static int svc_normal_to_secure_thread(void *data)
pdata, sizeof(*pdata),
>svc_fifo_lock);
 
-   if (!ret_fifo)
+   if (!ret_fifo) {
+   schedule_timeout_interruptible(MAX_SCHEDULE_TIMEOUT);
continue;
+   }
 
pr_debug("get from FIFO pa=0x%016x, command=%u, size=%u\n",
 (unsigned int)pdata->paddr, pdata->command,
-- 
2.9.3

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[linux-yocto] : [yocto-4.12]: intel-socfpga: update patches for Stratix10 platform

[Meng.Li]

From: Limeng 


Hi Bruce,

Now, there are 2 below patches to update intel-socfpga, Stratix10 SoC platform.
0001-driver-of-configfs-fix-a-building-warning.patch
0002-driver-misc-intel-service-schedule-thread-out-when-t.patch

Please help to meger the 2 patches into linux-yocto, kernel 4.12, branch is 
standard/base

misc/intel-service.c |5 -
of/configfs.c|2 +-
2 files changed, 5 insertions(+), 2 deletions(-)

thanks,
Limeng


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[linux-yocto] [PATCH 23/25] arm64: dts: stratix10: disable false USB overcurrent on devkit

[Meng.Li]

From: Dinh Nguyen 

commit  1752cc0adb37e96e79a8ce8189dbd8d53016a224 from
https://github.com/altera-opensource/linux-socfpga.git

Disable the USB overcurrent condition that is falsely detected on the
devkit.

Signed-off-by: Dinh Nguyen 
Signed-off-by: Meng Li 
---
 .../boot/dts/altera/socfpga_stratix10_socdk.dts|1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts 
b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
index 8f421d6..ec18609 100644
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
@@ -113,6 +113,7 @@
 
  {
status = "okay";
+   disable-over-current;
 };
 
  {
-- 
1.7.9.5

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[linux-yocto] [PATCH 20/25] FogBugz #539974: set clocks for watchdog timer on Stratix10

[Meng.Li]

From: Dinh Nguyen 

commit  b002bf552cb779951ca843a058545dc146989270 from
https://github.com/altera-opensource/linux-socfpga.git

Populate the clocks property in the watchdog timers on Stratix10.

Signed-off-by: Dinh Nguyen 
Signed-off-by: Meng Li 
---
 arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi |4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi 
b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
index c8bc964..dc0a4a6 100644
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
@@ -882,6 +882,7 @@
reg = <0xffd00200 0x100>;
interrupts = <0 117 4>;
resets = < WATCHDOG0_RESET>;
+   clocks = <_sys_free_clk>;
status = "disabled";
};
 
@@ -890,6 +891,7 @@
reg = <0xffd00300 0x100>;
interrupts = <0 118 4>;
resets = < WATCHDOG1_RESET>;
+   clocks = <_sys_free_clk>;
status = "disabled";
};
 
@@ -898,6 +900,7 @@
reg = <0xffd00400 0x100>;
interrupts = <0 125 4>;
resets = < WATCHDOG2_RESET>;
+   clocks = <_sys_free_clk>;
status = "disabled";
};
 
@@ -906,6 +909,7 @@
reg = <0xffd00500 0x100>;
interrupts = <0 126 4>;
resets = < WATCHDOG3_RESET>;
+   clocks = <_sys_free_clk>;
status = "disabled";
};
 
-- 
1.7.9.5

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[linux-yocto] [PATCH 22/25] arm64: dts: stratix10: enable watchdog timer on the S10 devkit

[Meng.Li]

From: Dinh Nguyen 

commit  07ecc72ce169d4a4e11259067a714e31d6acd400 from
https://github.com/altera-opensource/linux-socfpga.git

Enables the watchdog0 timer on the Stratix10 devkit.

Signed-off-by: Dinh Nguyen 

Conflicts:
arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
Signed-off-by: Meng Li 
---
 .../boot/dts/altera/socfpga_stratix10_socdk.dts|4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts 
b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
index 81fc603..8f421d6 100644
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
@@ -173,3 +173,7 @@
};
};
 };
+
+ {
+   status = "okay";
+};
-- 
1.7.9.5

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[linux-yocto] [PATCH 24/25] FogBugz #545807: driver, misc: increase timeout value for claiming back buf

[Meng.Li]

From: Richard Gong 

commit  f1835b2b7aa23cc1b47c178a3eb414eaf58fde63 from
https://github.com/altera-opensource/linux-socfpga.git

Firmware from the latest Quartus releases takes more time to process
data. As a result service layer needs increase timeout value so it can
claim back the submitted data buffer(s) from the secure world to program
FPGA properly.

Also add pr_err() to provide the error return value for the case
which service layer fails to make a SMC call to secure world for the
shared memory block reserved by secure monitor software.

Signed-off-by: Richard Gong 
Signed-off-by: Meng Li 
---
 drivers/misc/intel-service.c |4 +++-
 include/linux/intel-service-client.h |2 +-
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/misc/intel-service.c b/drivers/misc/intel-service.c
index c87d9aa..4c63330 100644
--- a/drivers/misc/intel-service.c
+++ b/drivers/misc/intel-service.c
@@ -55,7 +55,7 @@
  * from the secure world for FPGA manager to reuse, or to free the buffer(s)
  * when all bit-stream data had be send.
  */
-#define FPGA_CONFIG_DATA_CLAIM_TIMEOUT_MS  20
+#define FPGA_CONFIG_DATA_CLAIM_TIMEOUT_MS  200
 /*
  * FPGA_CONFIG_STATUS_TIMEOUT_SEC - poll the FPGA configuration status,
  * service layer will return error to FPGA manager when timeout occurs,
@@ -642,6 +642,8 @@ static int svc_normal_to_secure_shm_thread(void *data)
sh_mem->addr = res.a1;
sh_mem->size = res.a2;
} else {
+   pr_err("%s: after SMC call -- res.a0=0x%016x",  __func__,
+  (unsigned int)res.a0);
sh_mem->addr = 0;
sh_mem->size = 0;
}
diff --git a/include/linux/intel-service-client.h 
b/include/linux/intel-service-client.h
index aac16ab..8cef141 100644
--- a/include/linux/intel-service-client.h
+++ b/include/linux/intel-service-client.h
@@ -49,7 +49,7 @@
 
 /* Timeout settings for FPGA manager driver */
 #define SVC_RECONFIG_REQUEST_TIMEOUT_MS 100
-#define SVC_RECONFIG_BUFFER_TIMEOUT_MS  100
+#define SVC_RECONFIG_BUFFER_TIMEOUT_MS  240
 
 struct intel_svc_chan;
 
-- 
1.7.9.5

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[linux-yocto] [PATCH] arm64: dts: add dts for updating FPGA configure

[Meng.Li]

From: Limeng 

Add a overlay to implement updating FPGA congifure in Linux
enviroment in real time via Stratix 10 FPGA manager.

Signed-off-by: Meng Li 
---
 arch/arm64/boot/dts/altera/Makefile|2 +-
 .../dts/altera/socfpga_stratix10_fpga_update.dts   |   17 +
 2 files changed, 18 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm64/boot/dts/altera/socfpga_stratix10_fpga_update.dts

diff --git a/arch/arm64/boot/dts/altera/Makefile 
b/arch/arm64/boot/dts/altera/Makefile
index 5b08e85..ecc0560 100644
--- a/arch/arm64/boot/dts/altera/Makefile
+++ b/arch/arm64/boot/dts/altera/Makefile
@@ -1,4 +1,4 @@
-dtb-$(CONFIG_ARCH_STRATIX10) += socfpga_stratix10_socdk.dtb
+dtb-$(CONFIG_ARCH_STRATIX10) += socfpga_stratix10_socdk.dtb 
socfpga_stratix10_fpga_update.dtb
 dtb-$(CONFIG_ARCH_STRATIX10SWVP) += stratix10_swvp.dtb
 
 always := $(dtb-y)
diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_fpga_update.dts 
b/arch/arm64/boot/dts/altera/socfpga_stratix10_fpga_update.dts
new file mode 100644
index 000..c7811cc
--- /dev/null
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_fpga_update.dts
@@ -0,0 +1,17 @@
+/dts-v1/;
+/plugin/;
+/ {
+   fragment@0 {
+   target-path = "/soc/base_fpga_region";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   __overlay__ {
+   #address-cells = <1>;
+   #size-cells = <1>;
+
+   firmware-name = "soc_s10_fpga_config.rbf";
+   config-complete-timeout-us = <200>;
+   };
+   };
+};
+
-- 
1.7.9.5

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[linux-yocto] [PATCH 19/25] Revert "ARM: DT: Enable symbols when CONFIG_OF_OVERLAY is used"

[Meng.Li]

From: Alan Tull 

commit  62b87db13758408968d1979be70e673873346415 from
https://github.com/altera-opensource/linux-socfpga.git

This reverts commit fe94677b6e60189ee0e4dbace1ce81c66c2053c5.
Signed-off-by: Meng Li 
---
 arch/arm/boot/Makefile |4 
 arch/arm/boot/dts/Makefile |4 
 2 files changed, 8 deletions(-)

diff --git a/arch/arm/boot/Makefile b/arch/arm/boot/Makefile
index 056cc97..1af29e0 100644
--- a/arch/arm/boot/Makefile
+++ b/arch/arm/boot/Makefile
@@ -29,10 +29,6 @@ export ZRELADDR INITRD_PHYS PARAMS_PHYS
 
 targets := Image zImage xipImage bootpImage uImage
 
-ifeq ($(CONFIG_OF_OVERLAY),y)
-DTC_FLAGS += -@
-endif
-
 ifeq ($(CONFIG_XIP_KERNEL),y)
 
 $(obj)/xipImage: vmlinux FORCE
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 0633c38..64aecde 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1,9 +1,5 @@
 ifeq ($(CONFIG_OF),y)
 
-ifeq ($(CONFIG_OF_OVERLAY),y)
-DTC_FLAGS += -@
-endif
-
 dtb-$(CONFIG_ARCH_ALPINE) += \
alpine-db.dtb
 dtb-$(CONFIG_MACH_ARTPEC6) += \
-- 
1.7.9.5

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[linux-yocto] [PATCH 18/25] kbuild: Enable DT symbols when CONFIG_OF_OVERLAY is used

[Meng.Li]

From: Geert Uytterhoeven 

commit  ed1eb10b8dd43ea1447e5adc47bcd52ddc3b5c25 from
https://github.com/altera-opensource/linux-socfpga.git

Signed-off-by: Geert Uytterhoeven 
Signed-off-by: Meng Li 
---
 scripts/Makefile.lib |4 
 1 file changed, 4 insertions(+)

diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
index 58c05e5..c35bbaa 100644
--- a/scripts/Makefile.lib
+++ b/scripts/Makefile.lib
@@ -313,6 +313,10 @@ cmd_dt_S_dtb=  
\
 $(obj)/%.dtb.S: $(obj)/%.dtb
$(call cmd,dt_S_dtb)
 
+ifeq ($(CONFIG_OF_OVERLAY),y)
+DTC_FLAGS += -@
+endif
+
 quiet_cmd_dtc = DTC $@
 cmd_dtc = mkdir -p $(dir ${dtc-tmp}) ; \
$(CPP) $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) $< ; \
-- 
1.7.9.5

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