Steven Rostedt wrote:
I'm going through old email, and I found this. Do you still see this
error. I don't recall seeing it myself.
I can still recreate this with 31-rc9. When i enable tracing
with function_graph i notice the following oops. This happens
only once. Later if i try to enable/dis
This patch separates the parts of hugetlbpage.c which are inherently
specific to the hash MMU into a new hugelbpage-hash64.c file.
Signed-off-by: David Gibson
---
arch/powerpc/include/asm/hugetlb.h |3
arch/powerpc/mm/Makefile |5 -
arch/powerpc/mm/hugetlbpage-hash64.c |
Currently each available hugepage size uses a slightly different
pagetable layout: that is, the bottem level table of pointers to
hugepages is a different size, and may branch off from the normal page
tables at a different level. Every hugepage aware path that needs to
walk the pagetables must the
This patch simplifies the logic used to initialize hugepages on
powerpc. The somewhat oddly named set_huge_psize() is renamed to
add_huge_page_size() and now does all necessary verification of
whether it's given a valid hugepage sizes (instead of just some) and
instantiates the generic hstate stru
Currently we have a fair bit of rather fiddly code to manage the
various kmem_caches used to store page tables of various levels. We
generally have two caches holding some combination of PGD, PUD and PMD
tables, plus several more for the special hugepage pagetables.
This patch cleans this all up
Currently, hpte_need_flush() only correctly flushes the given address
for normal pages. Callers for hugepages are required to mask the
address themselves.
But hpte_need_flush() already looks up the page sizes for its own
reasons, so this is a rather silly imposition on the callers. This
patch al
Currently, ordinary pages use one pagetable layout, and each different
hugepage size uses a slightly different variant layout. A number of
places which need to walk the pagetable must first check the slice map
to see what the pagetable layout then handle the various different
forms. New hardware,
The following commit introduced a compile error since it removed
the implementation of smp_85xx_basic_setup:
commit 77c0a700c1c292edafa11c1e52821ce4636f81b0
Author: Benjamin Herrenschmidt
Date: Fri Aug 28 14:25:04 2009 +1000
powerpc: Properly start decrementer on BookE secondary CPUs
Make
On Sep 8, 2009, at 4:31 PM, Benjamin Herrenschmidt wrote:
On Tue, 2009-09-08 at 14:21 -0500, Kumar Gala wrote:
struct smp_ops_t smp_85xx_ops = {
+ .message_pass = NULL,
+ .probe = NULL,
.kick_cpu = smp_85xx_kick_cpu,
+ .setup_cpu = NULL,
};
Why explicitely setting
One I2C driver has been included in 0603 bsp, you can refer to it.
It has no specific driver for GPIO, but you can find some initializing
code for GPIO in arch/powerpc/platforms/512x/mpc5125_ads.c. and
mpc512x_pm_test.c.
From:
linuxppc-dev-bounces+hong
On 07/29/2009 12:03 PM, ashish kalra wrote:
From: Ashish Kalra
Date: Wed, 29 Jul 2009 21:15:49 +0530
Fix for non-ncq & ncq commands causing timeouts when both are issued
simultaneously to the same device.
Signed-off-by: Ashish Kalra
---
drivers/ata/sata_fsl.c | 1 +
1 files changed, 1 insertio
On Tue, 2009-09-08 at 16:00 -0400, Adam Zilkie wrote:
> We are using pci_alloc_consistent()
Then your flush should have no effect since pci_alloc_consistent will
return I=1 mapped memory, unless you don't have
CONFIG_NOT_COHERENT_CACHE for some reason.
Cheers,
Ben.
> Adam
>
> On Tue, 2009-09-08
On Mon, 2009-08-03 at 16:10 +0530, Sachin Sant wrote:
> Steven Rostedt wrote:
> > Thanks,
> >
> > I've seen issues with my PPC box and function graph, but the bugs were
> > also caused by other changes. I'll boot up my PPC64 box and see if
> > I see the same issues you have.
> >
> Hi Steven,
>
From: Pravin Bathija
Powerpc 44x uses 36 bit real address while the real address defined
in MPT Fusion driver is of type 32 bit. This causes ioremap to fail and driver
fails to initialize. This fix changes the data types representing the real
address from unsigned long 32-bit types to "phys_addr_
Also remove a duplicate setting of it in the context switch path
on BookE.
Signed-off-by: Benjamin Herrenschmidt
---
arch/powerpc/kernel/process.c | 14 +++---
1 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
i
On Mon, Sep 07, 2009 at 10:44:07AM +0530, M. Mohan Kumar wrote:
> Write to HVC terminal from purgatory code
>
> Current x86/x86-64 kexec-tools print the message "I'm in purgatory" to
> serial console/VGA while executing the purgatory code. Implement this
> feature for POWERPC pseries platform by
On Tue, 2009-09-08 at 15:30 -0400, Adam Zilkie wrote:
> All,
>
> We have found that using flush_dcache_range() after each DMA solves the
> problem. Ideally, we'd like to be able to allocate the virtual page in
> cache inhibited memory to avoid the performance loss from all the flush
> calls. To do
On Tue, 2009-09-08 at 14:21 -0500, Kumar Gala wrote:
>
> struct smp_ops_t smp_85xx_ops = {
> + .message_pass = NULL,
> + .probe = NULL,
> .kick_cpu = smp_85xx_kick_cpu,
> + .setup_cpu = NULL,
> };
Why explicitely setting those to NULL ?
Cheers,
Ben.
> -static int __init sm
On Tue, 2009-09-08 at 14:01 -0400, Adam Zilkie wrote:
> Hi Prodyut,
>
> Yes, I am using the 440EPx (same as the sequoia board).
> Our ideDriver is DMA'ing blocks of 192-byte data over the PCI bus (using
> the Sil0680A PCI-IDE bridge). Most of the DMA's (depending on timing)
> end up being partial
We are using pci_alloc_consistent()
Adam
On Tue, 2009-09-08 at 12:56 -0700, Prodyut Hazarika wrote:
> > We have found that using flush_dcache_range() after each DMA solves
> the
> > problem. Ideally, we'd like to be able to allocate the virtual page in
> > cache inhibited memory to avoid the perf
> We have found that using flush_dcache_range() after each DMA solves
the
> problem. Ideally, we'd like to be able to allocate the virtual page in
> cache inhibited memory to avoid the performance loss from all the
flush
> calls. To do this, we'd have to change our TLB sizes and reserve a TLB
> in
All,
We have found that using flush_dcache_range() after each DMA solves the
problem. Ideally, we'd like to be able to allocate the virtual page in
cache inhibited memory to avoid the performance loss from all the flush
calls. To do this, we'd have to change our TLB sizes and reserve a TLB
in memo
The following commit introduced a compile error since it removed
the implementation of smp_85xx_basic_setup:
commit 77c0a700c1c292edafa11c1e52821ce4636f81b0
Author: Benjamin Herrenschmidt
Date: Fri Aug 28 14:25:04 2009 +1000
powerpc: Properly start decrementer on BookE secondary CPUs
Make
Hi Adam,
> Yes, I am using the 440EPx (same as the sequoia board).
> Our ideDriver is DMA'ing blocks of 192-byte data over the PCI bus
(using
> the Sil0680A PCI-IDE bridge). Most of the DMA's (depending on timing)
> end up being partially corrupted when we try to parse the data in the
> virtual p
Hi Prodyut,
Yes, I am using the 440EPx (same as the sequoia board).
Our ideDriver is DMA'ing blocks of 192-byte data over the PCI bus (using
the Sil0680A PCI-IDE bridge). Most of the DMA's (depending on timing)
end up being partially corrupted when we try to parse the data in the
virtual page. We
Hi all,
I am a newbie to the powerpc linux kernel, but I have worked
on some drivers in arm architecture. I am finding powerpc architecture to be
fully different than that.
I am working on Freescale MPC5121e with the BSP MPC512xADS_20090603-ltib.iso
running in it on the ADS512101
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