Re: [PATCH] powerpc/8xx: fix regression introduced by cache coherency rewrite

2009-10-04 Thread Joakim Tjernlund
Benjamin Herrenschmidt b...@kernel.crashing.org wrote on 03/10/2009 12:57:28: On Sat, 2009-10-03 at 11:24 +0200, Joakim Tjernlund wrote: So yes, there is a missing _tlbil_va() missing for 8xx somewhere but there is something more too. Maybe your new filter functions and my powerpc,

Re: [PATCH] sound: Don't assume i2c device probing always succeeds

2009-10-04 Thread Jean Delvare
Hi Takashi, On Thu, 01 Oct 2009 08:52:59 +0200, Takashi Iwai wrote: At Wed, 30 Sep 2009 18:55:05 +0200, Jean Delvare wrote: On Wed, 30 Sep 2009 17:15:49 +0200, Takashi Iwai wrote: Yes, indeed I prefer NULL check because the user can know the error at the right place. I share your

Re: [patch 1/3] powerpc: Move 64bit VDSO to improve context switch performance

2009-10-04 Thread Andreas Schwab
Benjamin Herrenschmidt b...@kernel.crashing.org writes: Maybe a better fix is to force alignment in the kernel by requesting size + 64k - 4k and aligning it. Sure you are right. Andreas. From b9441a3d2148d439e2730def3222a7b70dccc432 Mon Sep 17 00:00:00 2001 From: Andreas Schwab

Re: [PATCH] powerpc/8xx: fix regression introduced by cache coherency rewrite

2009-10-04 Thread Joakim Tjernlund
Scott Wood scottw...@freescale.com wrote on 02/10/2009 23:49:49: On Thu, Oct 01, 2009 at 08:35:59AM +1000, Benjamin Herrenschmidt wrote: From what I can see, the TLB miss code will check _PAGE_PRESENT, and when not set, it will -still- insert something into the TLB (unlike all other CPU

Re: [PATCH] powerpc/8xx: fix regression introduced by cache coherency rewrite

2009-10-04 Thread Benjamin Herrenschmidt
On Sun, 2009-10-04 at 10:35 +0200, Joakim Tjernlund wrote: Benjamin Herrenschmidt b...@kernel.crashing.org wrote on 03/10/2009 12:57:28: On Sat, 2009-10-03 at 11:24 +0200, Joakim Tjernlund wrote: So yes, there is a missing _tlbil_va() missing for 8xx somewhere but there is

Re: [PATCH] powerpc/8xx: fix regression introduced by cache coherency rewrite

2009-10-04 Thread Benjamin Herrenschmidt
I have managed to update the TLB code to make proper use of dirty and accessed states. Advantages are: - I/D TLB Miss never needs to write to the linux pte, saving a few cycles That's good, that leaves us with only 40x to fix now. Also we can remove atomic updates of PTEs for all non-hash.

Re: [PATCH] powerpc/8xx: fix regression introduced by cache coherency rewrite

2009-10-04 Thread Joakim Tjernlund
Benjamin Herrenschmidt b...@kernel.crashing.org wrote on 04/10/2009 22:26:42: On Sun, 2009-10-04 at 10:35 +0200, Joakim Tjernlund wrote: Benjamin Herrenschmidt b...@kernel.crashing.org wrote on 03/10/2009 12:57:28: On Sat, 2009-10-03 at 11:24 +0200, Joakim Tjernlund wrote: So

Re: [PATCH] powerpc/8xx: fix regression introduced by cache coherency rewrite

2009-10-04 Thread Joakim Tjernlund
Benjamin Herrenschmidt b...@kernel.crashing.org wrote on 04/10/2009 22:28:38: I have managed to update the TLB code to make proper use of dirty and accessed states. Advantages are: - I/D TLB Miss never needs to write to the linux pte, saving a few cycles That's good, that leaves us

Re: [PATCH] sound: Don't assume i2c device probing always succeeds

2009-10-04 Thread Takashi Iwai
At Sun, 4 Oct 2009 11:35:21 +0200, Jean Delvare wrote: Hi Takashi, On Thu, 01 Oct 2009 08:52:59 +0200, Takashi Iwai wrote: At Wed, 30 Sep 2009 18:55:05 +0200, Jean Delvare wrote: On Wed, 30 Sep 2009 17:15:49 +0200, Takashi Iwai wrote: Yes, indeed I prefer NULL check because