On Tue, Jun 21, 2011 at 08:13:21AM -0400, Josh Boyer wrote:
The Security function on the AMCC SoCs has multiple engines within a
single MMIO range. The crypto driver currently enables the 3DES
functionality by doing a blind write to the device control register.
This can unintentionally
On Tue, Jun 21, 2011 at 10:56:02AM -0500, Matt Mackall wrote:
On Tue, 2011-06-21 at 08:19 -0400, Josh Boyer wrote:
Various PowerPC 4xx SoCs contain a TRNG embedded in the Security function.
This adds a device driver for that TRNG.
Signed-off-by: Josh Boyer jwbo...@linux.vnet.ibm.com
On Sun, Jun 26, 2011 at 11:47:13PM +0900, Masami Hiramatsu wrote:
(2011/06/24 19:29), Steven Rostedt wrote:
On Fri, 2011-06-24 at 17:21 +0800, Yong Zhang wrote:
Hi,
When I use kprobe to do something, I found some wired thing.
When CONFIG_FUNCTION_TRACER is disabled:
(gdb)
On Tue, May 31, 2011 at 02:27:19PM -0700, Tirumala Marri wrote:
Not sure how I would know -- But with my eiger kit, I got a
cd from amcc that had a patched 2.6.30 or something kernel
in it to support the 460SX. The pci code was basically
subverted by adding a port-link=1 at the very end of
On Mon, 2011-06-27 at 05:14 -0500, Ayman El-Khashab wrote:
I took care of that in my patch. Basically it let the
system go to gen-2 speeds and negotiate down.
[marri] Great thx.
Ok, so I am back from doing whatever it is that I do. Shall
I go ahead and take a stab at making a new
On Sat, 2011-06-25 at 18:52 -0500, Ayman El-Khashab wrote:
I noticed during a recent development with the 460SX that a
simple device that once worked stopped. I did a bisect to
find the offending commit and it turns out to be this one:
0e52247a2ed1f211f0c4f682dc999610a368903f is the first
On Mon, Jun 27, 2011 at 08:19:56PM +1000, Benjamin Herrenschmidt wrote:
On Sat, 2011-06-25 at 18:52 -0500, Ayman El-Khashab wrote:
I noticed during a recent development with the 460SX that a
simple device that once worked stopped. I did a bisect to
find the offending commit and it turns
On Mon, 2011-06-27 at 06:31 -0500, Ayman El-Khashab wrote:
That was my initial thought as well, but I wasn't versed
enough in the pci magic in order to completely figure it
out.
Here is the output, it is dmesg, iomem, then ioports for the
passing and then the failing cases.
Ok, I can see
On Jun 23, 2011, at 11:16 AM, Timur Tabi wrote:
mpc8610hpcd_set_pixel_clock() calculates the correct value of the PXCLK
bits in the CLKDVDR register for a given pixel clock rate. The code which
performs this calculation is overly complicated and includes an error
estimation routine that
On Jun 14, 2011, at 6:04 PM, Timur Tabi wrote:
The Freescale hypervisor does not allow guests to write to the timebase
registers (virtualizing the timebase register was deemed too complicated),
so don't try to synchronize the timebase registers when we're running
under the hypervisor.
On Jun 22, 2011, at 6:10 PM, Scott Wood wrote:
e500mc cannot doze or nap due to an erratum (as well as having a
different mechanism than previous e500), but it has a wait instruction
that is similar to doze.
On 64-bit, due to the soft-irq-disable mechanism, the existing
book3e_idle should
On Jun 23, 2011, at 7:06 AM, Kumar Gala wrote:
Split out common (non-board specific) parts of the SoC related device
tree into a stub so multiple board dts files can include it and we can
reduce duplication and maintenance effort.
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
---
On Jun 23, 2011, at 11:16 AM, Timur Tabi wrote:
Enable framebuffer console support by default in the defconfig on the
Freescale MPC8610 HPCD reference board. This allows the boot messages to
be shown on the video display.
Signed-off-by: Timur Tabi ti...@freescale.com
---
On Jun 23, 2011, at 2:48 PM, Timur Tabi wrote:
Enable framebuffer console support by default in the defconfigs for the
Freescale 85xx-based reference board. This allows the boot messages to
be shown on the video display on the P1022DS.
Signed-off-by: Timur Tabi ti...@freescale.com
---
On Jun 23, 2011, at 2:48 PM, Timur Tabi wrote:
To ensure that the DIU pixel clock will not be set to an invalid value,
clamp the PXCLK divider to the allowed range (2-255). This also acts as
a limiter for the pixel clock.
Signed-off-by: Timur Tabi ti...@freescale.com
---
Split out common (non-board specific) parts of the SoC related device
tree into a stub so multiple board dts files can include it and we can
reduce duplication and maintenance effort.
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
---
arch/powerpc/boot/dts/p3041ds.dts | 579
Split out common (non-board specific) parts of the SoC related device
tree into a stub so multiple board dts files can include it and we can
reduce duplication and maintenance effort.
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
---
arch/powerpc/boot/dts/p5020ds.dts | 571
Hello,
On 6/17/11, Dmitry Eremin-Solenikov dbarysh...@gmail.com wrote:
Hello, colleagues,
Another respin of this patchset.
Changes since previous version:
* Fix comments in cpc925_edac.c
* Rename cpc925_cpu_getmask() to cpc925_cpu_mask_disabled()
* Don't return an error from init code if
This iotype is only used by the legacy_serial code in powerpc, so the
code should live there, rather than be compiled in for every 8250
driver.
Signed-off-by: Arnd Bergmann a...@arndb.de
Cc: Benjamin Herrenschmidt b...@kernel.crashing.org
Cc: linuxppc-dev@lists.ozlabs.org
Cc: Greg Kroah-Hartman
As is done in read_tsc() on x86, make sure that we don't return a timebase
value smaller than cycle_last, which can happen on SMP if the timebases are
not perfectly synchronized. It is less expensive than total enforcement of
monotonicity, since we don't need to add another variable and update it
On 06/27/2011 02:45 PM, Arnd Bergmann wrote:
This iotype is only used by the legacy_serial code in powerpc, so the
code should live there, rather than be compiled in for every 8250
driver.
Signed-off-by: Arnd Bergmanna...@arndb.de
Cc: Benjamin Herrenschmidtb...@kernel.crashing.org
Cc:
On Mon, 2011-06-27 at 16:56 -0500, Scott Wood wrote:
As is done in read_tsc() on x86, make sure that we don't return a timebase
value smaller than cycle_last, which can happen on SMP if the timebases are
not perfectly synchronized. It is less expensive than total enforcement of
monotonicity,
From: Liu Shuo b35...@freescale.com
The global data fsl_lbc_ctrl_dev-nand don't have to be freed in
fsl_elbc_chip_remove(). The right place to do that is in fsl_elbc_nand_remove()
if elbc_fcm_ctrl-counter is zero.
Signed-off-by: Liu Shuo b35...@freescale.com
---
drivers/mtd/nand/fsl_elbc_nand.c
From: Liu Shuo b35...@freescale.com
Freescale FCM controller has a 2K size limitation of buffer RAM. In order
to support the Nand flash chip whose page size is larger than 2K bytes,
we divide a page into multi-2K pages for MTD layer driver. In that case,
we force to set the page size to 2K bytes.
Remove duplicate assignment of SCSI_BNX2_ISCSI in pseries_defconfig
introduced by:
37e0c21e powerpc/pseries: Enable iSCSI support for a number of cards
causes warning:
arch/powerpc/configs/pseries_defconfig:151:warning: override: reassigning to
symbol SCSI_BNX2_ISCSI
Signed-off-by: Michael
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