My main concern is that currently the PCI code has some assumptions
about ordering of things that will get violated.
For example, the pci final fixups are an fs_initcall iirc, or something
like that. There's other similar oddities that might become problematic.
In addition, there might be
Do hardware timebase sync. Firstly, stop all timebases, and transfer
the timebase value of the boot core to the other core. Finally,
start all timebases.
Only apply to dual-core chips, such as MPC8572, P2020, etc.
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
Signed-off-by: Li Yang
From: Li Yang le...@freescale.com
Add support to disable and re-enable individual cores at runtime
on MPC85xx/QorIQ SMP machines. Currently support e500v1/e500v2 core.
MPC85xx machines use ePAPR spin-table in boot page for CPU kick-off.
This patch uses the boot page from bootloader to boot core
Add APIs for setting wakeup source and lossless Ethernet in low power modes.
These APIs can be used by wake-on-packet feature.
Signed-off-by: Dave Liu dave...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Jin Qing b24...@freescale.com
Signed-off-by: Zhao Chenhui
Some 85xx silicons like MPC8536 and P1022 have a JOG feature, which provides
a dynamic mechanism to lower or raise the CPU core clock at runtime.
This patch adds the support to change CPU frequency using the standard
cpufreq interface. The ratio CORE to CCB can be 1:1(except MPC8536), 3:2,
2:1,
From: Li Yang le...@freescale.com
In sleep PM mode, the clocks of e500 core and unused IP blocks is
turned off. IP blocks which are allowed to wake up the processor
are still running.
Some Freescale chips like MPC8536 and P1022 has deep sleep PM mode
in addtion to the sleep PM mode.
While in
We want to access the MMCRA_SIHV and MMCRA_SIPR bits elsewhere so
create mmcra_sihv and mmcra_sipr which hide the differences between
the old and new layout of the bits.
Signed-off-by: Anton Blanchard an...@samba.org
---
Index: linux-build/arch/powerpc/perf/core-book3s.c
The logic to choose whether to use the SIAR or get the information
out of pt_regs is going to get more complicated, so do it once in
perf_read_regs.
We overload regs-result which is gross but we are already doing it
with regs-dsisr.
Signed-off-by: Anton Blanchard an...@samba.org
---
Other
At the moment we always use the SIAR if the PMU supports continuous
sampling. Unfortunately the SIAR and the PMU exception are not
synchronised for non marked events so we can end up with callchains
that dont make sense.
The following patch checks the HV and PR bits for samples coming from
We use SIAR or regs-nip for the instruction pointer depending on
the PMU configuration, but we always use regs-nip in the callchain.
Use perf_instruction_pointer so the backtrace is consistent.
Signed-off-by: Anton Blanchard an...@samba.org
---
Index: linux-build/arch/powerpc/perf/callchain.c
On Jun 26, 2012, at 5:25 AM, Zhao Chenhui wrote:
Do hardware timebase sync. Firstly, stop all timebases, and transfer
the timebase value of the boot core to the other core. Finally,
start all timebases.
Only apply to dual-core chips, such as MPC8572, P2020, etc.
Signed-off-by: Zhao
usb_get_phy will return -ENODEV if it's not able to find the phy. Hence
fixed all the callers of usb_get_phy to check for this error condition
instead of relying on a non-zero value as success condition.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
Developed on
This patch series adds support to set basic usb gadget properties via
devicetree.
I takes into account the sugestions from Rob Herring and Mitch Bradley.
This was only tested on ARM LPC32XX SOC. I'm including patches to other soc's as
an reference.
Alexandre Pereira da Silva (5):
usb: gadget:
Fill dev.of_node of gadget drivers, so they can use devicetree
Signed-off-by: Alexandre Pereira da Silva aletes@gmail.com
---
drivers/usb/gadget/lpc32xx_udc.c |1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/usb/gadget/lpc32xx_udc.c b/drivers/usb/gadget/lpc32xx_udc.c
index
Fill dev.of_node of gadget drivers, so they can use devicetree
Signed-off-by: Alexandre Pereira da Silva aletes@gmail.com
---
drivers/usb/gadget/s3c-hsotg.c |1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/usb/gadget/s3c-hsotg.c b/drivers/usb/gadget/s3c-hsotg.c
index
Fill dev.of_node of gadget drivers, so they can use devicetree
Signed-off-by: Alexandre Pereira da Silva aletes@gmail.com
---
drivers/usb/gadget/fsl_udc_core.c |1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/usb/gadget/fsl_udc_core.c
b/drivers/usb/gadget/fsl_udc_core.c
index
Fill dev.of_node of gadget drivers, so they can use devicetree
Signed-off-by: Alexandre Pereira da Silva aletes@gmail.com
---
drivers/usb/gadget/at91_udc.c |1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/usb/gadget/at91_udc.c b/drivers/usb/gadget/at91_udc.c
index
Grab the devicetree node properties to override VendorId, ProductId,
bcdDevice, Manucacturer, Product and SerialNumber
Signed-off-by: Alexandre Pereira da Silva aletes@gmail.com
---
Documentation/devicetree/bindings/usb/gadget.txt | 20 +++
drivers/usb/gadget/composite.c
I'm hoping someone here can help me. Several levels of Freescale
management have assured me that I am authorized to discuss their Linux
code on public lists--and even explicitly suggested the ozlabs
linuxppc-dev list.
I'm using the P4080 processor and the Freescale SDK on a custom board.
We've
On Mon, Jun 25, 2012 at 5:30 PM, Gavin Shan sha...@linux.vnet.ibm.com wrote:
Yeah, I think your patch meets the requirement: access struct
pci_host_bridge,
and when will you merge your patch into mainline?
not sure.
but i extract that patch as attached.
and with that could make your first
On 06/26/2012 09:27 AM, Alexandre Pereira da Silva wrote:
Grab the devicetree node properties to override VendorId, ProductId,
bcdDevice, Manucacturer, Product and SerialNumber
I'm still confused about what is the order of priority for the 2
possible sources of these values. The way it is
On 06/26/2012 09:27 AM, Alexandre Pereira da Silva wrote:
Grab the devicetree node properties to override VendorId, ProductId,
bcdDevice, Manucacturer, Product and SerialNumber
Like before, the code looks good to me:
Acked-by: Michal Nazarewicz min...@mina86.com
Not commenting on the other
The support for this reference platform really no longer needs
to be carried in tree anymore, since the hardware has been EOL'd
for a while, and the age and configuration of the hardware doesn't
really make it desireable to use vs. say using the newer Wind River
sbc8548 board, which has had recent
This reference board dates back to 2004, and is largely a legacy
EOL product. The MPC8560 is a pre e500v2 CPU. The SBC8548 is
a more modern, better e500v2 target for people to use as a
reference board with today's kernels, should they require one.
Removing support for it will also allow us to
The SBC8260 support was dropped back when we moved from ppc to
powerpc. We are now also dropping the support for the EOL SBC8560,
so we can also delete this mapping support, as they were the only
users of it.
Cc: David Woodhouse david.woodho...@intel.com
Cc: linux-...@lists.infradead.org
We've are dropping the support for the EOL SBC8560, so we can
also delete this variant of the Alpha quirk support.
Cc: Alan Cox a...@linux.intel.com
Cc: Greg Kroah-Hartman gre...@linuxfoundation.org
Cc: linux-ser...@vger.kernel.org
Signed-off-by: Paul Gortmaker paul.gortma...@windriver.com
---
On Tue, Jun 26, 2012 at 9:59 PM, Geert Uytterhoeven
ge...@linux-m68k.org wrote:
JFYI, when comparing v3.5-rc4 to v3.5-rc3[3], the summaries are:
- build errors: +11/-219
11 regressions:
+ arch/sh/include/asm/fixmap.h: error: implicit declaration of
function 'BUG_ON'
On 06/26/2012 09:03 AM, Kumar Gala wrote:
On Jun 26, 2012, at 5:25 AM, Zhao Chenhui wrote:
Do hardware timebase sync. Firstly, stop all timebases, and transfer
the timebase value of the boot core to the other core. Finally,
start all timebases.
Only apply to dual-core chips, such as
On Tue, 2012-06-26 at 16:45 -0500, Scott Wood wrote:
Some parts are due to corenet versus non-corenet, such as the actual
register you write to to disable/enable the timebase.
There's also a two-core assumption in the synchronization code which
I've complained about multiple times --
On Tue, 2012-06-26 at 18:25 +0800, Zhao Chenhui wrote:
Do hardware timebase sync. Firstly, stop all timebases, and transfer
the timebase value of the boot core to the other core. Finally,
start all timebases.
Only apply to dual-core chips, such as MPC8572, P2020, etc.
Signed-off-by: Zhao
On Mon, 2012-06-25 at 15:26 +0300, Mihai Caraman wrote:
Refactor exception prolog to allow save/restore register parameters. Add
addition none definition for exception prolog usage.
This is needed for exceptions like Guest Doorbell that use GSRRx regsiters
which do not map on exception type.
On Mon, 2012-06-25 at 15:26 +0300, Mihai Caraman wrote:
Machine check exception handler was using a wrong prolog. Hypervisors, like
KVM, which are called early from the exception handler rely on the interrupt
source.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
Ack.
Please
On Mon, 2012-06-25 at 15:26 +0300, Mihai Caraman wrote:
Embedded.Hypervisor category defines GSPRG0..3 physical registers for guests.
Avoid SPRG4-7 usage as scratch in host exception handlers, otherwise guest
SPRG4-7 registers will be clobbered.
For bolted TLB miss exception handlers, which is
On 06/25/2012 07:26 AM, Mihai Caraman wrote:
Embedded.Hypervisor category defines GSPRG0..3 physical registers for guests.
Avoid SPRG4-7 usage as scratch in host exception handlers, otherwise guest
SPRG4-7 registers will be clobbered.
For bolted TLB miss exception handlers, which is the
On 06/25/2012 07:26 AM, Mihai Caraman wrote:
Add KVM_SREGS_E_64 feature and EPCR spr support in get/set sregs
for 64-bit hosts.
Signed-off-by: Mihai Caraman mihai.cara...@freescale.com
---
arch/powerpc/kvm/booke.c | 14 ++
1 files changed, 14 insertions(+), 0 deletions(-)
On 06/26/2012 06:04 AM, Anton Blanchard wrote:
We use SIAR or regs-nip for the instruction pointer depending on
the PMU configuration, but we always use regs-nip in the callchain.
Use perf_instruction_pointer so the backtrace is consistent.
Signed-off-by: Anton Blanchard an...@samba.org
On Sat, 23 Jun 2012 23:58:22 +0900
Akinobu Mita akinobu.m...@gmail.com wrote:
This adds two testing scripts with notifier error injection
Can we move these into tools/testing/selftests/, so that a make
run_tests runs these tests?
Also, I don't think it's appropriate that fault-injection be in
On Tue, Jun 26, 2012 at 04:31:47PM -0700, Andrew Morton wrote:
My overall take on the fault-injection code is that there has been a
disappointing amount of uptake: I don't see many developers using them
for whitebox testing their stuff. I guess this patchset addresses
that, in a way.
I
Hi Scott,
Won't this break core-fsl-emb, which doesn't define
perf_instruction_pointer()?
It links ok for me. You should get the default version:
#ifndef perf_misc_flags
# define perf_misc_flags(regs) \
(user_mode(regs) ? PERF_RECORD_MISC_USER :
PERF_RECORD_MISC_KERNEL)
#
Signed-off-by: Michael Neuling mi...@neuling.org
diff --git a/arch/powerpc/platforms/pseries/eeh_pseries.c
b/arch/powerpc/platforms/pseries/eeh_pseries.c
index 8752f79..c33360ec 100644
--- a/arch/powerpc/platforms/pseries/eeh_pseries.c
+++ b/arch/powerpc/platforms/pseries/eeh_pseries.c
@@ -81,7
From: Bharat Bhushan bharat.bhus...@freescale.com
The caam job rings (input/output job ring) are allocated using
dma_map_single(). These job rings can be visualized as the ring
buffers in which the jobs are en-queued/de-queued. The s/w enqueues
the jobs in input job ring which h/w dequeues and
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