On Thu, Feb 02, 2017 at 11:12:46AM +0530, Bhupesh Sharma wrote:
> This RFC patchset tries to make the powerpc ASLR elf randomness
> implementation similar to other ARCHs (like x86).
>
> The 1st patch introduces the support of ARCH_MMAP_RND_BITS in powerpc
> mmap implementation to allow a sane bala
This adds AUX vectors for the L1I,D, L2 and L3 cache levels
providing for each cache level the size of the cache in bytes
and the geometry (line size and number of ways).
We chose to not use the existing alpha/sh definition which
packs all the information in a single entry per cache level as
it is
Acked-by: Ian Munsie
Nathan Fontenot writes:
> The ibm,dynamic-reconfiguration-memory/ibm,dynamic-memory property
> of the device-tree can be fairly big on systems with a large amount
> of memory. A system with 1 TB of memory (256 MB LMBs) the property
> size is 94k, this equates to roughly a 30MB property size for a
Hi Kees,
On Thu, Jan 26, 2017 at 7:08 AM, Kees Cook wrote:
> On Sun, Jan 22, 2017 at 9:34 PM, Bhupesh Sharma wrote:
>> I was recently looking at ways to extend the randomization range for a
>> ASLR elf on a PPC64LE system.
>>
>> I basically have been using 28-bits of randomization on x86_64 for
Currently the powerpc arch uses a ELF_ET_DYN_BASE value of 0x2000
which ends up pushing an elf to a load address which is 32-bit.
On 64-bit platforms, this might be too less especially when one is
trying to increase the randomness of the load address of the ASLR elfs
on such platforms.
This p
powerpc: arch_mmap_rnd() uses hard-coded values, (23-PAGE_SHIFT) for
32-bit and (30-PAGE_SHIFT) for 64-bit, to generate the random offset
for the mmap base address.
This value represents a compromise between increased
ASLR effectiveness and avoiding address-space fragmentation.
Replace it with a K
This RFC patchset tries to make the powerpc ASLR elf randomness
implementation similar to other ARCHs (like x86).
The 1st patch introduces the support of ARCH_MMAP_RND_BITS in powerpc
mmap implementation to allow a sane balance between increased randomness
in the mmap address of ASLR elfs and incr
> NOTE: This is an internal posting at the moment for review
> and criticism.
>
Clearly left over bits, please ignore
Balbir
After updating ppc-dis.c, ppc-opc.c and ppc.h
the following changes were made to enable compilation
and working of xmon
1. Remove all disasmebler_info
2. Use xmon's printf/print_address to output data and
addresses respectively
3. All bfd_* types and casts have been removed
4. Optimizations rel
Upgrade ppc-opc.c, ppc-dis.c and ppc.h to the
versions belonging to the following commit
65b650b4c7463f4508bed523c24ab0031a5ae5cd
* ppc-dis.c (print_insn_powerpc): Don't skip all operands
after setting skip_optional.
This version will not compile, but make it easier to
apply newer reclicensed c
This series updates xmon to allow disassembly of
upto POWER9 instructions.
With a lot of help from Peter Bergner and help
from Paul Mckenney I was able to get help in relicensing
the new binutils ppc-opc.c/ppc-dis.c and ppc.h to
GPLv2. The details of the commits are in patch 2 in the
series. The
> On Jan 26, 2017, at 5:58 PM, Ashley Lai wrote:
>
> Adding Vicky from IBM.
>
>
> On 01/26/2017 04:05 PM, Jason Gunthorpe wrote:
>> On Thu, Jan 26, 2017 at 09:22:48PM +0100, Michal Such??nek wrote:
>>
>>> This is repeated a few times in the driver so I added memset to quiet
>>> gcc and make b
On Jan 26, 2017, at 5:58 PM, Ashley Lai wrote:Adding Vicky from IBM.On 01/26/2017 04:05 PM, Jason Gunthorpe wrote:On Thu, Jan 26, 2017 at 09:22:48PM +0100, Michal Such??nek wrote:This is repeated a few times in the driver so I added memset to quietgcc and make behavior deterministic in case the un
On Wed, 2017-02-01 at 20:40 -0800, Eric Dumazet wrote:
> A typical benchmark would be to use 200 concurrent netperf -t TCP_RR,
> through a single qdisc (protected by a spinlock)
>
> Non ticket/queued spinlocks behave quite bad in this scenario.
>
> I can try this next week if you want.
That woul
On 02/02/17 04:30, Christophe Lombard wrote:
The two fields pid and tid of the structure cxl_irq_info are only used
in the guest environment. To avoid confusion, it's not necessary
to fill the fields in the bare-metal environment.
The PSL Process and Thread Identification Register is only used wh
On 02/02/17 04:30, Christophe Lombard wrote:
This bit is used to cause a flash image load for programmable
CAIA-compliant implementation. If this bit is set to ‘0’, a power
cycle of the adapter is required to load a programmable CAIA-com-
pliant implementation from flash.
This field will be use
Benjamin Herrenschmidt writes:
> On Wed, 2017-02-01 at 09:05 -0800, Eric Dumazet wrote:
>> Hi all
>>
>> Is anybody working on adding QUEUED spinlocks to powerpc 64bit ?
>>
>> I've seen past attempts with ticket spinlocks
>> ( https://patchwork.ozlabs.org/patch/449381/ and other related links
>>
On 02/02/17 12:28, Borislav Petkov wrote:
> On Thu, Feb 02, 2017 at 12:16:24PM +1300, Chris Packham wrote:
>> The l2-cache controller on the T2080 SoC has similar capabilities to the
>> others already supported by the mpc85xx_edac driver. Add it to the list
>> of compatible devices.
>>
>> Signed-of
On Thu, Feb 02, 2017 at 12:16:24PM +1300, Chris Packham wrote:
> The l2-cache controller on the T2080 SoC has similar capabilities to the
> others already supported by the mpc85xx_edac driver. Add it to the list
> of compatible devices.
>
> Signed-off-by: Chris Packham
> Acked-by: Johannes Thumsh
The l2-cache controller on the T2080 SoC has similar capabilities to the
others already supported by the mpc85xx_edac driver. Add it to the list
of compatible devices.
Signed-off-by: Chris Packham
Acked-by: Johannes Thumshirn
---
This is a resend of a patch that got an ack[1] but didn't seem to
The generic implementation of of_node_to_nid is EXPORT_SYMBOL.
The powerpc implementation added by following commit is EXPORT_SYMBOL_GPL.
commit 953039c8df7b ("[PATCH] powerpc: Allow devices to register with numa
topology")
This creates an inconsistency for of_node_to_nid callers across
architect
On Wed, 1 Feb 2017, Josh Poimboeuf wrote:
> If there are no more comments, it would be great to get these patches in
> for the 4.11 merge window. Any objections to that?
That'd mean that the exposure in -next would be really short, which I'd
like to avoid. I'd love to tentatively target 4.12 t
On Wed, 1 Feb 2017, Josh Poimboeuf wrote:
> On Thu, Jan 19, 2017 at 09:46:08AM -0600, Josh Poimboeuf wrote:
> > Here's v4, based on linux-next/master. Mostly minor changes this time,
> > primarily due to Petr's v3 comments.
>
> So far, the only review comments have been related to the first patc
On Wed, 2017-02-01 at 09:05 -0800, Eric Dumazet wrote:
> Hi all
>
> Is anybody working on adding QUEUED spinlocks to powerpc 64bit ?
>
> I've seen past attempts with ticket spinlocks
> ( https://patchwork.ozlabs.org/patch/449381/ and other related links
> )
>
> But it looks ticket spinlocks are
On Thu, Jan 19, 2017 at 09:46:08AM -0600, Josh Poimboeuf wrote:
> Here's v4, based on linux-next/master. Mostly minor changes this time,
> primarily due to Petr's v3 comments.
So far, the only review comments have been related to the first patch,
of which I just posted an updated version.
If the
For live patching and possibly other use cases, a stack trace is only
useful if it can be assured that it's completely reliable. Add a new
save_stack_trace_tsk_reliable() function to achieve that.
Note that if the target task isn't the current task, and the target task
is allowed to run, then it
Thiago Jung Bauermann [bauer...@linux.vnet.ibm.com] wrote:
> Instead of this method of trying a small RMA size and rebooting to try a
> bigger size, could the "min RMA percentage of total RAM" field of the
> ibm_architecture_vec be used?
We tried that and concluded that even 1% could end up rese
Hello,
Am Mittwoch, 1. Februar 2017, 16:37:58 BRST schrieb Michael Ellerman:
> Sukadev Bhattiprolu writes:
> > Paul Clarke [p...@us.ibm.com] wrote:
> > ---
> >
> > From f9e9e8460206bc3fa7eaa741b9a2bde22870b9e0 Mon Sep 17 00:00:00 2001
>
> I know it's been a while but I think it would still be g
The cpufeatures binding describes architected CPU features along with
some compatibility, privilege, and enablement properties that allow
flexibility with discovering and enabling capabilities.
For example, FSCR or similar simple prescription based enablement can be
done by an OS that does not und
The new Coherent Accelerator Interface Architecture, level 2, for the
IBM POWER9 brings new content and features:
- POWER9 Service Layer
- Registers
- Radix mode
- Process element entry
- Dedicated-Shared Process Programming Model
- Translation Fault Handling
- CAPP
- Memory Context ID
If a val
Point out the specific Coherent Accelerator Interface Architecture,
level 1, registers.
Code and functions specific to PSL8 (CAIA1) must be framed.
Signed-off-by: Christophe Lombard
---
drivers/misc/cxl/context.c | 28 +++-
drivers/misc/cxl/cxl.h | 35 +++-
Rename a few functions, changing the '_psl' suffix to '_psl8', to make
clear that the implementation is psl8 specific.
Those functions will have an equivalent implementation for the psl9 in
a later patch.
Signed-off-by: Christophe Lombard
---
drivers/misc/cxl/cxl.h | 23 +++--
The service layer API (in cxl.h) lists some low-level functions whose
implementation is different on PSL8, PSL9 and XSL. Each
environment implements its own functions, and the common code uses
them through function pointers, defined in cxl_service_layer_ops.
Signed-off-by: Christophe Lombard
---
The mm_struct corresponding to the current task is acquired each time
an interrupt is raised. So to simplify the code, we only get the
mm_struct when attaching an AFU context to the process.
The mm_count reference is increased to ensure that the mm_struct can't
be freed. The mm_struct will be relea
The two fields pid and tid of the structure cxl_irq_info are only used
in the guest environment. To avoid confusion, it's not necessary
to fill the fields in the bare-metal environment.
The PSL Process and Thread Identification Register is only used when
attaching a dedicated process for PSL8 only.
This bit is used to cause a flash image load for programmable
CAIA-compliant implementation. If this bit is set to ‘0’, a power
cycle of the adapter is required to load a programmable CAIA-com-
pliant implementation from flash.
This field will be used by the following patches.
Signed-off-by: Chris
This series adds support for a cxl card which supports the Coherent
Accelerator Interface Architecture 2.0.
It requires IBM Power9 system and the Power Service Layer, version 9.
The PSL provides the address translation and system memory cache for
CAIA compliant Accelerators.
the PSL attaches to th
Hi all
Is anybody working on adding QUEUED spinlocks to powerpc 64bit ?
I've seen past attempts with ticket spinlocks
( https://patchwork.ozlabs.org/patch/449381/ and other related links )
But it looks ticket spinlocks are a thing of the past.
Thanks.
On Wed, 1 Feb 2017 14:26:16 +1100
Alexey Kardashevskiy wrote:
> d9c728949ddc: "vfio/spapr: Postpone default window creation" added
> an additional exit to the VFIO_IOMMU_SPAPR_TCE_CREATE case and made it
> possible to return from tce_iommu_ioctl() without unlocking
> container->lock; this fixes
hotplug_init: Simplify the code needed for runtime memory hotplug and
maintenance with a conversion routine that transforms the compressed
property "ibm,dynamic-memory-v2" to the form of "ibm,dynamic-memory"
within the "ibm,dynamic-reconfiguration-memory" property. Thus only
a single set of routin
On Wednesday 01 February 2017 04:30 PM, Anton Blanchard wrote:
Hi Maddy,
+EVENT(PM_INST_DISP,0x200f0)
+EVENT(PM_INST_DISP_ALT,0x300f0)
Are you sure these are the right events? 0x200f2, 0x300f2 should be
instruction dispatch I think.
Hi Maddy,
> +EVENT(PM_INST_DISP, 0x200f0)
> +EVENT(PM_INST_DISP_ALT, 0x300f0)
Are you sure these are the right events? 0x200f2, 0x300f2 should be
instruction dispatch I think.
Anton
Anju T Sudhakar writes:
> Detour buffer contains instructions to create an in memory pt_regs.
> After the execution of the pre-handler, a call is made for instruction
> emulation.
> The NIP is determined in advanced through dummy instruction emulation and a
> branch
> instruction is created to
On Wed, Jan 25, 2017 at 10:46 AM, Thomas De Schampheleire
wrote:
> Hi,
>
> We are experiencing kernel panics of the type "Unable to handle kernel paging
> request for instruction fetch" but are stuck in our analysis. We would
> appreciate any help you can give.
>
> The problem occurs from time to
On Tue, 31 Jan 2017, Josh Poimboeuf wrote:
> On Tue, Jan 31, 2017 at 03:31:39PM +0100, Miroslav Benes wrote:
> > On Thu, 19 Jan 2017, Josh Poimboeuf wrote:
> >
> > > Expose the per-task patch state value so users can determine which tasks
> > > are holding up completion of a patching operation.
>
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