[Patch v4] powerpc/powernv: add hdat attribute to sysfs

The HDAT data area is consumed by skiboot and turned into a device-tree. In some cases we would like to look directly at the HDAT, so this patch adds a sysfs node to allow it to be viewed. This is not possible through /dev/mem as it is reserved memory which is stopped by the /dev/mem filter.

Re: [PATCH 3/7] cxl: Keep track of mm struct associated with a context

On 02/02/17 04:30, Christophe Lombard wrote: The mm_struct corresponding to the current task is acquired each time an interrupt is raised. So to simplify the code, we only get the mm_struct when attaching an AFU context to the process. The mm_count reference is increased to ensure that the

[RFC 3/3] cxl: Reset freeze counters before adapter PERST for flashing new image

The patch resets the freeze counter on eeh_pe struct for PHB associated with the cxl pci adapter. This would enable re-flashing of the cxl-adapter beyond the default limit of 5. Signed-off-by: Vaibhav Jain --- drivers/misc/cxl/pci.c | 15 +++ 1 file

Re: [PATCH 3/3] powerpc/64s: POWER9 machine check handler

On 02/28/2017 07:30 AM, Nicholas Piggin wrote: > Add POWER9 machine check handler. There are several new types of errors > added, so logging messages for those are also added. > > This doesn't attempt to reuse any of the P7/8 defines or functions, > because that becomes too complex. The better

[RFC 2/3] powerpc/eeh: Introduce function eeh_pe_reset_freeze_counter

This patch introduces function eeh_pe_reset_freeze_counter which can be used to reset the PE's freeze count variable outside eeh code. This is useful for devices that can acquire a different personality after a PERST event (e.g FPGA Adapters). Presently an existing freeze count for an adapter with

[RFC 1/3] powerpc/eeh: Refactor eeh_pe_update_time_stamp to update freeze_count

This patch introduces a new function named eeh_pe_update_freeze_counter replacing existing function eeh_pe_update_time_stamp. The new function also manages the value of freeze_count along with tstamp to track the number of times the PE froze in last one hour and if the freeze_count >

[RFC 0/3] cxl: Reset freeze counter for the adapter before PERST

Presently to flash a cxl adapter with a new FPGA image a warm pcie reset is requested on the adapter, once the bitstream is loaded to card flash memory. This issues a pci-fundamental reset to the card slot signaling the card controller to reconfigure the fpga with the new bitstream. However

[PATCH V3 2/2] powerpc: Update to new option-vector-5 format for CAS

On POWER9 the ibm,client-architecture-support (CAS) negotiation process has been updated to change how the host to guest negotiation is done for the new hash/radix mmu as well as the nest mmu, process tables and guest translation shootdown (GTSE). The host tells the guest which options it

[PATCH V3 1/2] powerpc: Parse the command line before calling CAS

On POWER9 the hypervisor requires the guest to decide whether it would like to use a hash or radix mmu model at the time it calls ibm,client-architecture-support (CAS) based on what the hypervisor has said it's allowed to do. It is possible to disable radix by passing "disable_radix" on the

Re: [PATCH 1/3] powerpc/64s: fix handling of non-synchronous machine checks

On 02/28/2017 07:30 AM, Nicholas Piggin wrote: > A synchronous machine check is an exception raised by the attempt to > execute the current instruction. If the error can't be corrected, it > can make sense to SIGBUS the currently running process. > > In other cases, the error condition is not

Re: [PATCH] KVM: Prevent double-free on HPT resize commit path

On Tue, Feb 28, 2017 at 11:56:55AM +1100, David Gibson wrote: > On Wed, Feb 15, 2017 at 02:40:04PM +1100, David Gibson wrote: > > resize_hpt_release(), called once the HPT resize of a KVM guest is > > completed (successfully or unsuccessfully) free()s the state structure for > > the resize. It is

Re: [PATCH] jump_label: align jump_entry table to at least 4-bytes

972 Comm: modprobe Not tainted 4.10.0-next-20170227 #4 [ 11.731930] task: c0077b284a00 task.stack: c0077b8b8000 [ 11.731933] NIP: c17bf84c LR: c17bfcbc CTR: [ 11.731937] REGS: c0077b8bb800 TRAP: 0700 Not tainted (4.10.0-next-20170227)

Re: [PATCH v3 1/2] powerpc: split ftrace bits into a separate file

Steven Rostedt writes: > On Wed, 22 Feb 2017 00:31:01 +0530 > "Naveen N. Rao" wrote: > >> entry_*.S now includes a lot more than just kernel entry/exit code. As a >> first step at cleaning this up, let's split out the ftrace bits into >>

Re: [PATCH v3 2/2] powerpc: ftrace_64: split further based on -mprofile-kernel

Steven Rostedt writes: > On Wed, 22 Feb 2017 00:31:02 +0530 > "Naveen N. Rao" wrote: > >> Split ftrace_64.S further retaining the core ftrace 64-bit aspects >> in ftrace_64.S and moving ftrace_caller() and ftrace_graph_caller() into >>

Re: PowerPC build fail

"Tobin C. Harding" writes: > On Mon, Feb 27, 2017 at 09:38:13PM +1100, Michael Ellerman wrote: >> Hi Tobin, >> >> "Tobin C. Harding" writes: >> > The current (2bfe01e) torvalds git tree fails to build on powerpc64. Build >> > machine >> > is virtualized. >> > >>

Re: [PATCH v3] powerpc/powernv: add hdat attribute to sysfs

Oliver O'Halloran writes: > On Mon, Feb 27, 2017 at 9:56 PM, Michael Ellerman wrote: >> Matt Brown writes: >>> diff --git a/arch/powerpc/platforms/powernv/opal-hdat.c >>> b/arch/powerpc/platforms/powernv/opal-hdat.c >>> new

[PATCH 3/3] powerpc/64s: POWER9 machine check handler

Add POWER9 machine check handler. There are several new types of errors added, so logging messages for those are also added. This doesn't attempt to reuse any of the P7/8 defines or functions, because that becomes too complex. The better option in future is to use a table driven approach.

[PATCH 2/3] powerpc/64s: allow machine check handler to set severity and initiator

Currently severity and initiator are always set to MCE_SEV_ERROR_SYNC and MCE_INITIATOR_CPU in the core mce code. Allow them to be set by the machine specific mce handlers. No functional change for existing handlers. Signed-off-by: Nicholas Piggin ---

[PATCH 1/3] powerpc/64s: fix handling of non-synchronous machine checks

A synchronous machine check is an exception raised by the attempt to execute the current instruction. If the error can't be corrected, it can make sense to SIGBUS the currently running process. In other cases, the error condition is not related to the current instruction, so killing the current

[PATCH 0/3 v2] MCE handler for POWER9

Hi, This is a minimal implementation of the POWER9 MCE handler that should be suitable for backport if necessary. Moving this to firmware may be the right long term solution, but we need a P9 Linux handler for existing kernels and firmwares. Thanks, Nick Nicholas Piggin (3): powerpc/64s: fix

Re: [PATCH] KVM: Prevent double-free on HPT resize commit path

On Wed, Feb 15, 2017 at 02:40:04PM +1100, David Gibson wrote: > resize_hpt_release(), called once the HPT resize of a KVM guest is > completed (successfully or unsuccessfully) free()s the state structure for > the resize. It is currently not safe to call with a NULL pointer. > > However, one of

Re: [PATCH kernel v5 10/10] KVM: PPC: VFIO: Add in-kernel acceleration for VFIO

On Mon, Feb 27, 2017 at 02:20:13PM +1100, Alexey Kardashevskiy wrote: > On 27/02/17 12:53, David Gibson wrote: > > On Fri, Feb 24, 2017 at 02:43:05PM +1100, Alexey Kardashevskiy wrote: > >> On 24/02/17 14:36, David Gibson wrote: > >>> On Fri, Feb 24, 2017 at 02:29:14PM +1100, Alexey Kardashevskiy

Re: [PATCH kernel] powerpc/powernv/ioda2: Gracefully fail if too many TCE levels requested

On 27/02/17 22:00, Michael Ellerman wrote: > Alexey Kardashevskiy writes: > >> The IODA2 specification says that a 64 DMA address cannot use top 4 bits >> (3 are reserved and one is a "TVE select"); bottom page_shift bits >> cannot be used for multilevel table addressing either.

Re: [PATCH v2 3.5/5] trace/kprobes: Add back warning about offset in return probes

On Mon, 27 Feb 2017 11:52:04 -0500 "Steven Rostedt (VMware)" wrote: > Let's not remove the warning about offsets and return probes when the > offset is invalid. Agreed, This looks good to me. Acked-by: Masami Hiramatsu Thanks! > > Signed-off-by:

Re: [PATCH] jump_label: align jump_entry table to at least 4-bytes

On 02/27/2017 02:50 PM, Jason Baron wrote: On 02/27/2017 05:45 PM, David Daney wrote: On 02/27/2017 02:36 PM, Steven Rostedt wrote: On Mon, 27 Feb 2017 14:21:21 -0800 David Daney wrote: See attached for mips. It seems to do the right thing. I leave it as an

Re: [PATCH] jump_label: align jump_entry table to at least 4-bytes

On 02/27/2017 05:45 PM, David Daney wrote: On 02/27/2017 02:36 PM, Steven Rostedt wrote: On Mon, 27 Feb 2017 14:21:21 -0800 David Daney wrote: See attached for mips. It seems to do the right thing. I leave it as an exercise to the reader to fix the other

Re: [PATCH] jump_label: align jump_entry table to at least 4-bytes

On Mon, 27 Feb 2017 14:45:37 -0800 David Daney wrote: > On 02/27/2017 02:36 PM, Steven Rostedt wrote: > > On Mon, 27 Feb 2017 14:21:21 -0800 > > David Daney wrote: > > > >> See attached for mips. It seems to do the right thing. > >> > >>

Re: [PATCH] jump_label: align jump_entry table to at least 4-bytes

On 02/27/2017 02:36 PM, Steven Rostedt wrote: On Mon, 27 Feb 2017 14:21:21 -0800 David Daney wrote: See attached for mips. It seems to do the right thing. I leave it as an exercise to the reader to fix the other architectures. Consult your own binutils experts

Re: [PATCH] jump_label: align jump_entry table to at least 4-bytes

On Mon, 27 Feb 2017 14:21:21 -0800 David Daney wrote: > See attached for mips. It seems to do the right thing. > > I leave it as an exercise to the reader to fix the other architectures. > > Consult your own binutils experts to verify that what I say is true. It

Re: [PATCH] jump_label: align jump_entry table to at least 4-bytes

On 02/27/2017 02:09 PM, Steven Rostedt wrote: On Mon, 27 Feb 2017 13:41:13 -0800 David Daney wrote: On 02/27/2017 01:06 PM, Steven Rostedt wrote: On Mon, 27 Feb 2017 11:59:50 -0800 David Daney wrote: For me the size is not the

Re: [PATCH] jump_label: align jump_entry table to at least 4-bytes

On Mon, 27 Feb 2017 13:41:13 -0800 David Daney wrote: > On 02/27/2017 01:06 PM, Steven Rostedt wrote: > > On Mon, 27 Feb 2017 11:59:50 -0800 > > David Daney wrote: > > > >> For me the size is not the important issue, it is the alignment of

Re: [PATCH] jump_label: align jump_entry table to at least 4-bytes

On 02/27/2017 01:06 PM, Steven Rostedt wrote: On Mon, 27 Feb 2017 11:59:50 -0800 David Daney wrote: For me the size is not the important issue, it is the alignment of the struct jump_entry entries in the table. I don't understand how your patch helps, and I cannot

Re: [PATCH] jump_label: align jump_entry table to at least 4-bytes

On Mon, 27 Feb 2017 11:59:50 -0800 David Daney wrote: > For me the size is not the important issue, it is the alignment of the > struct jump_entry entries in the table. I don't understand how your > patch helps, and I cannot Acked-by unless I understand what is

[PATCH] staging: fsl-mc: fix warning in DT ranges parser

The fsl-mc-bus driver in staging contains a copy of the standard 'ranges' property parsing algorithm with a hack to treat a missing property the same way as an empty one. This code produces false-positive warnings for me in an allmodconfig build: drivers/staging/fsl-mc/bus/fsl-mc-bus.c: In

Re: PowerPC build fail

On Mon, Feb 27, 2017 at 09:38:13PM +1100, Michael Ellerman wrote: > Hi Tobin, > > "Tobin C. Harding" writes: > > The current (2bfe01e) torvalds git tree fails to build on powerpc64. Build > > machine > > is virtualized. > > > > - Build error > > arch/powerpc/kernel/time.c: In

Re: [PATCH] jump_label: align jump_entry table to at least 4-bytes

On 02/27/2017 11:18 AM, Jason Baron wrote: On 02/27/2017 01:57 PM, David Daney wrote: On 02/27/2017 10:49 AM, Jason Baron wrote: The core jump_label code makes use of the 2 lower bits of the static_key::[type|entries|next] field. Thus, ensure that the jump_entry table is at least 4-byte

Re: [PATCH] jump_label: align jump_entry table to at least 4-bytes

On 02/27/2017 01:57 PM, David Daney wrote: On 02/27/2017 10:49 AM, Jason Baron wrote: The core jump_label code makes use of the 2 lower bits of the static_key::[type|entries|next] field. Thus, ensure that the jump_entry table is at least 4-byte aligned. [...] diff --git

[PATCH] jump_label: align jump_entry table to at least 4-bytes

The core jump_label code makes use of the 2 lower bits of the static_key::[type|entries|next] field. Thus, ensure that the jump_entry table is at least 4-byte aligned. Reported-and-tested-by: Sachin Sant Cc: Steven Rostedt Cc: Ingo Molnar

Re: [PATCH] jump_label: align jump_entry table to at least 4-bytes

On 02/27/2017 10:49 AM, Jason Baron wrote: The core jump_label code makes use of the 2 lower bits of the static_key::[type|entries|next] field. Thus, ensure that the jump_entry table is at least 4-byte aligned. [...] diff --git a/arch/mips/include/asm/jump_label.h

Re: [PATCH] ASoC: fsl: Remove unneeded init of static variable

On Sat, Feb 25, 2017 at 12:47:26PM +0200, Alin Grigorean wrote: > This was reported by checkpatch.pl > > Signed-off-by: Alin Grigorean Acked-by: Nicolin Chen > --- > sound/soc/fsl/imx-pcm-fiq.c | 2 +- > 1 file changed, 1 insertion(+), 1

[PATCH v2 3.5/5] trace/kprobes: Add back warning about offset in return probes

Let's not remove the warning about offsets and return probes when the offset is invalid. Signed-off-by: Steven Rostedt (VMware) --- diff --git a/kernel/trace/trace_kprobe.c b/kernel/trace/trace_kprobe.c index 3f4f788..f626235 100644 --- a/kernel/trace/trace_kprobe.c +++

Re: [PATCH v2 3/5] trace/kprobes: allow return probes with offsets and absolute addresses

On Wed, 22 Feb 2017 19:23:39 +0530 "Naveen N. Rao" wrote: > Since the kernel includes many non-global functions with same names, we > will need to use offsets from other symbols (typically _text/_stext) or > absolute addresses to place return probes on specific

Re: [PATCH v3 2/2] powerpc: ftrace_64: split further based on -mprofile-kernel

On Wed, 22 Feb 2017 00:31:02 +0530 "Naveen N. Rao" wrote: > Split ftrace_64.S further retaining the core ftrace 64-bit aspects > in ftrace_64.S and moving ftrace_caller() and ftrace_graph_caller() into > separate files based on -mprofile-kernel. The livepatch

Re: [PATCH v3 1/2] powerpc: split ftrace bits into a separate file

On Wed, 22 Feb 2017 00:31:01 +0530 "Naveen N. Rao" wrote: > entry_*.S now includes a lot more than just kernel entry/exit code. As a > first step at cleaning this up, let's split out the ftrace bits into > separate files. Also move all related tracing code into a

Re: next-20170217 boot on POWER8 LPAR : WARNING @kernel/jump_label.c:287

On Tue, 21 Feb 2017 11:37:21 -0500 Jason Baron wrote: > Thanks for testing. We probably need something like the following to > make sure we don't hit this on other arches. Steve - I will send 4 > separate patches for this to get arch maintainers' acks for this? > I just

Re: [PATCH] kbuild: avoid unrecognized option error for external DTC

On Mon, 2017-02-27 at 14:40 +0900, Masahiro Yamada wrote: > Since commit 6b22b3d1614a ("kbuild: Allow using host dtc instead of > kernel's copy"), it is possible to use an external dtc.  In this > case, we do not know which options are supported on it. > > Commit bc553986a2f7 ("dtc: turn off dtc

[PATCH 1/1] Add ASCII dump to d1,d2,d4,d8 commands.

The reason debuggers add an ASCII dump to other types of memory dumps is to give the user visual reference points in the case that ASCII strings are adjacent to other structures or element. For example, when examining the task_struct structure one can look for the comm[] string and use it to

[PATCH 2/2] power/mm: update pte_write and pte_wrprotect to handle savedwrite

We use pte_write() to check whethwer the pte entry is writable. This is mostly used to later mark the pte read only if it is writable. The other use of pte_write() is to check whether the pte_entry is writable so that hardware page table entry can be marked accordingly. This is used in kvm where

[PATCH 1/2] powerpc/mm: Handle protnone ptes on fork

We need mark pages of parent process read only on fork. Numa fault pte needs a protnone ptes variant with saved write flag set. On fork we need to make sure we remove the saved write bit. Instead of adding the protnone check in the caller update ptep_set_wrprotect variants to clear savedwrite bit.

Re: [PATCH v2 2/5] powerpc: kretprobes: override default function entry offset

Arnaldo Carvalho de Melo writes: > Em Wed, Feb 22, 2017 at 07:23:38PM +0530, Naveen N. Rao escreveu: >> With ABIv2, we offset 8 bytes into a function to get at the local entry >> point. > > So, I think I can carry the first one via Ingo, etc, what about this > one? > > Is it ok

Re: [PATCH] powerpc/xics: Fix migrate_irqs_away - set CPPR to lowest priority

Balbir Singh writes: > With XICS emulation, setting the CPPR to DEFAULT_PRIORITY ^ (Current Processor Priority Register) > masks all interrupts including

Re: [PATCH v3] powerpc/powernv: add hdat attribute to sysfs

On Mon, Feb 27, 2017 at 9:56 PM, Michael Ellerman wrote: > Matt Brown writes: >> diff --git a/arch/powerpc/platforms/powernv/opal-hdat.c >> b/arch/powerpc/platforms/powernv/opal-hdat.c >> new file mode 100644 >> index 000..3315dd3 >> ---

Re: [PATCH kernel] powerpc/powernv/ioda2: Gracefully fail if too many TCE levels requested

Alexey Kardashevskiy writes: > The IODA2 specification says that a 64 DMA address cannot use top 4 bits > (3 are reserved and one is a "TVE select"); bottom page_shift bits > cannot be used for multilevel table addressing either. > > The existing IODA2 table allocation code

Re: [PATCH v3] powerpc/powernv: add hdat attribute to sysfs

Matt Brown writes: > diff --git a/arch/powerpc/platforms/powernv/opal-hdat.c > b/arch/powerpc/platforms/powernv/opal-hdat.c > new file mode 100644 > index 000..3315dd3 > --- /dev/null > +++ b/arch/powerpc/platforms/powernv/opal-hdat.c > @@ -0,0 +1,65 @@ ... > + >

Re: [PATCH v3] powerpc/powernv: add hdat attribute to sysfs

Andrew Donnellan writes: > On 24/02/17 17:20, Matt Brown wrote: >> The HDAT data area is consumed by skiboot and turned into a device-tree. >> In some cases we would like to look directly at the HDAT, so this patch >> adds a sysfs node to allow it to be viewed.

Re: PowerPC build fail

Hi Tobin, "Tobin C. Harding" writes: > The current (2bfe01e) torvalds git tree fails to build on powerpc64. Build > machine > is virtualized. > > - Build error > arch/powerpc/kernel/time.c: In function ‘running_clock’: > arch/powerpc/kernel/time.c:712:25: error: implicit

Re: powerpc/mm/hash: Always clear UPRT and Host Radix bits when setting up CPU

On Wed, 2017-02-22 at 05:12:02 UTC, "Aneesh Kumar K.V" wrote: > We will set LPCR with correct value for radix during int. This make sure we > start with a sanitized value of LPCR. In case of kexec, cpus can have LPCR > value based on the previous translation mode we were running. > > Fixes:

Re: powerpc: Remove leftover cputime_to_nsecs call causing build error

On Tue, 2017-02-21 at 15:18:41 UTC, =?utf-8?b?RnLDqWTDqXJpYyBXZWlzYmVja2Vy?= wrote: > This type conversion is a leftover that got ignored during the kcpustat > conversion to nanosecs, resulting in build breakage with config having > CONFIG_NO_HZ_FULL=y. > > arch/powerpc/kernel/time.c: In

Re: powerpc: optprobes: fix TOC handling in optprobes trampoline

On Tue, 2017-02-21 at 15:00:47 UTC, "Naveen N. Rao" wrote: > Optprobes on powerpc is limited to kernel text area. We decided to also > optimize kretprobe_trampoline since that is also in kernel text area. > However,we failed to take into consideration the fact that the same > trampoline is also

Re: powerpc/pseries: advertise Hot Plug Event support to firmware

On Tue, 2017-02-21 at 01:12:18 UTC, Michael Roth wrote: > With the inclusion of: > > powerpc/pseries: Implement indexed-count hotplug memory remove > powerpc/pseries: Implement indexed-count hotplug memory add > > we now have complete handling of the RTAS hotplug event format > as described

Re: powerpc/powernv: Make PCI non-optional

On Fri, 2017-02-17 at 06:34:13 UTC, Michael Ellerman wrote: > Bare metal systems without PCI don't exist, so there's no real point in > making PCI optional, it just breaks the build from time to time. In fact > the build is broken now if you turn off PCI_MSI but enable KVM. > > Using select for

Re: [v7,2/4] powerpc/pseries: Revert 'Auto-online hotplugged memory'

On Wed, 2017-02-15 at 18:45:30 UTC, Nathan Fontenot wrote: > Revert the patch patch to auto-online hotplugged memory, commit > id ec999072442a. Using the auto-online acpability does online added > memory but does not update the associated device struct to > indicate that the memory is online. The

Re: [1/1] powerpc/xmon: Dump memory in native endian format.

On Tue, 2017-02-07 at 13:40:44 UTC, Douglas Miller wrote: > Extend dump command to allow display of 2, 4, and 8 byte words in native > endian format. Also adds dump command for "1 byte words" for the sake > of symmetry. New commands are: > > Signed-off-by: Douglas Miller

Re: cxl: fix nested locking hang during EEH hotplug

On Mon, 2017-02-06 at 01:07:17 UTC, Andrew Donnellan wrote: > Commit 14a3ae34bfd0 ("cxl: Prevent read/write to AFU config space while AFU > not configured") introduced a rwsem to fix an invalid memory access that > occurred when someone attempts to access the config space of an AFU on a > vPHB

Re: [PATCH] powerpc/mm: Add translation mode information in /proc/cpuinfo

"Aneesh Kumar K.V" writes: > On Wednesday 22 February 2017 11:15 AM, Michael Ellerman wrote: >> "Aneesh Kumar K.V" writes: >>> diff --git a/arch/powerpc/platforms/powernv/setup.c >>> b/arch/powerpc/platforms/powernv/setup.c >>>

[next 20170227] CPU remove DLPAR operation WARN @ lib/refcount.c:128

With Feb 27 next tree I am seeing inconsistent results on a CPU remove DLPAR operation on a POWER8 LPAR. After the cpu remove operation the SMT capability of the LPAR is disabled. # uname -r 4.10.0-next-20170227 # ppc64_cpu --smt SMT=8 # lscpu Architecture: ppc64le Byte Order

[next 20170227] Memory hot plug results in kernel BUG at mm/memory_hotplug.c:2180!

4.10.0-next-20170227 #1 [ 115.196260] Workqueue: pseries hotplug workque pseries_hp_work_fn [ 115.196263] task: c003b903c200 task.stack: c003b90fc000 [ 115.196266] NIP: c18789d0 LR: c1878958 CTR: c1cefb50 [ 115.196269] REGS: c003b90ff7a0 TRAP: 0700