[PATCH 08/13] ocxl: Add a kernel API for other opencapi drivers

to calling a in-kernel library. It is still a bit theoretical, for lack of real hardware, and will likely need adjustements down the road. But we used the cxlflash driver as a guinea pig. Signed-off-by: Frederic Barrat <fbar...@linux.vnet.ibm.com> --- drivers/misc/ocxl/config.c| 13 ++- d

[PATCH 06/13] ocxl: Driver code for 'generic' opencapi devices

to the opencapi device. Signed-off-by: Frederic Barrat <fbar...@linux.vnet.ibm.com> Signed-off-by: Andrew Donnellan <andrew.donnel...@au1.ibm.com> Signed-off-by: Alastair D'Silva <alast...@d-silva.org> --- drivers/misc/ocxl/config.c| 718 ++

[PATCH 07/13] ocxl: Add AFU interrupt support

and a write to that page will trigger an interrupt. Signed-off-by: Frederic Barrat <fbar...@linux.vnet.ibm.com> --- arch/powerpc/include/asm/pnv-ocxl.h | 3 + arch/powerpc/platforms/powernv/ocxl.c | 30 + drivers/misc/ocxl/afu_irq.c

[PATCH 05/13] powerpc/powernv: Capture actag information for the device

quite general. The number of available actags on POWER9 makes it more likely to be hit. This is somewhat mitigated by the fact that existing AFUs are coded by requesting a reasonable count of actags and existing devices carry only one AFU. Signed-off-by: Frederic Barrat <fbar...@linux.vnet.ibm.

[PATCH 03/13] powerpc/powernv: Add opal calls for opencapi

, the host and device must negotiate what templates are supported on both sides and at what rates those messages can be sent. Signed-off-by: Frederic Barrat <fbar...@linux.vnet.ibm.com> --- arch/powerpc/include/asm/opal-api.h| 5 - arch/powerpc/include/asm/opal.h

[PATCH 04/13] powerpc/powernv: Add platform-specific services for opencapi

by the NPU - map/unmap some NPU mmio registers to get the fault context when the NPU raises an address translation fault The rest are wrappers around the previously-introduced opal calls. Signed-off-by: Frederic Barrat <fbar...@linux.vnet.ibm.com> --- arch/powerpc/include/asm/pnv-

[PATCH 02/13] powerpc/powernv: Set correct configuration space size for opencapi devices

PCI fixup to declare the correct size. Signed-off-by: Andrew Donnellan <andrew.donnel...@au1.ibm.com> Signed-off-by: Frederic Barrat <fbar...@linux.vnet.ibm.com> --- arch/powerpc/platforms/powernv/pci-ioda.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/arch/powerpc/platforms/

[PATCH 01/13] powerpc/powernv: Introduce new PHB type for opencapi links

PNV_PHB_NPU type to PNV_PHB_NPU_NVLINK and add a new type PNV_PHB_NPU_OCAPI. Signed-off-by: Frederic Barrat <fbar...@linux.vnet.ibm.com> Signed-off-by: Andrew Donnellan <andrew.donnel...@au1.ibm.com> --- arch/powerpc/platforms/powernv/npu-dma.c | 2 +- arch/powerpc/platforms/powern

[PATCH 00/13] New driver to support OpenCAPI devices on POWER9

-local memory Many people contributed directly or indirectly, from the software, hardware and bringup teams. In particular Andrew Donnellan and Alastair D'Silva, who are developing the related firmware and library. Feedback welcome! Frederic Barrat (13): powerpc/powernv: Introduce new PHB type

Re: [PATCH] cxl: Enable PCI device ID for future CAPI adapter

Le 05/12/2017 à 18:06, Christophe Lombard a écrit : Add support for future Coherent Accelerator device with an ID of 0x060e. Signed-off-by: Christophe Lombard --- mpe, you can drop that patch, it's not needed. Christophe and I have sync'd up. Fred

Re: [PATCH v3] cxl: Check if vphb exists before iterating over AFU devices

ver it for the virtual AFU pci devices. This patch fixes the kenel-oops by adding a NULL pointer check for afu->phb before it is dereferenced. Fixes: 9e8df8a2196("cxl: EEH support") Cc: sta...@vger.kernel.org Signed-off-by: Vaibhav Jain <vaib...@linux.vnet.ibm.com> --- Thanks. Acked-by:

Re: [RESEND][PATCH v2] cxl: Check if vphb exists before iterating over AFU devices

Le 22/11/2017 à 13:17, Vaibhav Jain a écrit : During an eeh a kernel-oops is reported if no vPHB to allocated to the typo, "to allocated". Not important, but AFU. This happens as during AFU init, an error in creation of vPHB is a non-fatal error. Hence afu->phb should always be checked

Re: [PATCH v2 13/18] powerpc: Add support for setting SPRN_TIDR

thread ids to all threads in the system. Signed-off-by: Sukadev Bhattiprolu <suka...@linux.vnet.ibm.com> Signed-off-by: Philippe Bergheaud <fe...@linux.vnet.ibm.com> Signed-off-by: Christophe Lombard <clomb...@linux.vnet.ibm.com> --- FWIW Reviewed-by: Frederic Barrat <fbar.

Re: [PATCH] cxl: Rework the implementation of cxl_stop_trace_psl9()

() functions by moving them to 'pci.c' from 'debugfs.c' file and marking them as static. Signed-off-by: Vaibhav Jain <vaib...@linux.vnet.ibm.com> --- Looks ok to me. Acked-by: Frederic Barrat <fbar...@linux.vnet.ibm.com> drivers/misc/cxl/cxl.h | 14 -- drivers/misc/c

Re: [PATCH v2] cxl: Dump PSL_FIR register on PSL9 error irq

com> --- Changelog: [v2] -> As created a different function to dump the FIR register for PSL9 (Fred) --- Thanks! Acked-by: Frederic Barrat <fbar...@linux.vnet.ibm.com> drivers/misc/cxl/cxl.h| 3 ++- drivers/misc/cxl/native.c | 15 --- drivers/misc/cxl/pci.c|

Re: [PATCH] cxl: Dump PSL_FIR register on PSL9 error irq

Hi Vaibhav, I think we can make it slightly cleaner by registering a different callback for psl8 and psl9. The callback 'err_irq_dump_registers' is already in place, it could just point to a different function in psl8_ops and psl9_ops. Fred Le 09/10/2017 à 19:58, Vaibhav Jain a écrit :

Re: [PATCH] cxl: Rename register PSL9_FIR2 to PSL9_FIR_MASK

the def PSL9_FIR2 to PSL9_FIR_MASK and updates the references in the code to point to the new identifier. It also removes the code to dump contents of FIR2 (FIR_MASK actually) in cxl_native_irq_dump_regs_psl9(). Fixes: f24be42aab37("cxl: Add psl9 specific code") Reported-by: Frederic Ba

Re: [PATCH] cxl: Provide debugfs access to PSL_DEBUG/XSL_DEBUG registers

/card, which will provide direct r/w access to corrosponding debug registers in the adapter config-space. Signed-off-by: Vaibhav Jain <vaib...@linux.vnet.ibm.com> --- Thanks! Acked-by: Frederic Barrat <fbar...@linux.vnet.ibm.com> drivers/misc/cxl/cxl.h | 1 + drivers/misc/cxl/d

Re: [PATCH V2] cxl: Fix memory page not handled

-by: Christophe Lombard <clomb...@linux.vnet.ibm.com> Fixes: 3ced8d730063 ("cxl: Export library to support IBM XSL"); --- Thanks, Acked-by: Frederic Barrat <fbar...@linux.vnet.ibm.com> Changelog[v2] - Rebase to latest upstream. - Change the start address of the loop.

Re: [PATCH] cxl: Fix memory page not handled

Le 22/09/2017 à 15:08, Christophe Lombard a écrit : The a in-kernel 'library' API can be called by drivers to help "the in-kernel library" interaction with an IBM XSL on a POWER9 system. The cxllib_handle_fault() API is used to handle memory fault. All memory pages of the specified

Re: [PATCH v3 1/2] powerpc/mm: Export flush_all_mm()

Le 13/09/2017 à 06:04, Alistair Popple a écrit : +static inline void hash__local_flush_all_mm(struct mm_struct *mm) +{ + /* +* There's no Page Walk Cache for hash, so what is needed is +* the same as flush_tlb_mm(), which doesn't really make sense +* with hash. So

Re: [PATCH v3 2/2] cxl: Enable global TLBIs for cxl contexts

Le 08/09/2017 à 08:56, Nicholas Piggin a écrit : On Sun, 3 Sep 2017 20:15:13 +0200 Frederic Barrat <fbar...@linux.vnet.ibm.com> wrote: The PSL and nMMU need to see all TLB invalidations for the memory contexts used on the adapter. For the hash memory model, it is done by making all

Re: [PATCH v2 2/2] powerpc/powernv/npu: Don't explicitly flush nmmu tlb

) on the NVLink2 PHB to enable it only if required. Signed-off-by: Alistair Popple <alist...@popple.id.au> --- FWIW, Reviewed-by: Frederic Barrat <fbar...@linux.vnet.ibm.com> Changes for v2: - Use mm_context_add_copro()/mm_context_remove_copro() instead of inc_mm

Re: [PATCH V2] cxl: Add support for POWER9 DD2

et rid of it). The other item is capp recovery, which is still being worked on, but any change required there would hopefully be limited to skiboot. With the above: Acked-by: Frederic Barrat <fbar...@linux.vnet.ibm.com> Fred Changelog[v2] - Rebase to latest upstream. - Update

Re: [PATCH 2/2] powerpc/powernv/npu: Don't explicitly flush nmmu tlb

Le 05/09/2017 à 05:57, Alistair Popple a écrit : The nest mmu required an explicit flush as a tlbi would not flush it in the same way as the core. However an alternate firmware fix exists which should eliminate the need for this flush, so instead add a device-tree property (ibm,nmmu-flush) on

Re: [PATCH v2] cxl: Set the valid bit in PE for dedicated mode

com> --- Changelog: v2 -> Removed a call to smp_wmb() after setting the bit [Michael Ellerman] --- Acked-by: Frederic Barrat <fbar...@linux.vnet.ibm.com> drivers/misc/cxl/native.c | 8 1 file changed, 8 insertions(+) diff --git a/drivers/misc/cxl/native.c b/drivers/misc/cxl

[PATCH v3 2/2] cxl: Enable global TLBIs for cxl contexts

-by: Frederic Barrat <fbar...@linux.vnet.ibm.com> Fixes: f24be42aab37 ("cxl: Add psl9 specific code") --- Changelog: v3: don't decrement active cpus count with hash, as we don't know how to flush v2: Replace flush_tlb_mm() by the new flush_all_mm() to flush the TLBs and PWCs (thank

[PATCH v3 1/2] powerpc/mm: Export flush_all_mm()

With the optimizations introduced by commit a46cc7a90fd8 ("powerpc/mm/radix: Improve TLB/PWC flushes"), flush_tlb_mm() no longer flushes the page walk cache with radix. This patch introduces flush_all_mm(), which flushes everything, tlb and pwc, for a given mm. Signed-off-by: Frede

Re: [PATCH v2 1/3] powerpc/mm: Export flush_all_mm()

Le 30/08/2017 à 23:01, Benjamin Herrenschmidt a écrit : On Wed, 2017-08-30 at 15:59 +0200, Frederic Barrat wrote: It's not clear why it makes sense for these to be empty. Either for the general idea of the "flush_all_mm()" API, or for your intended use by CXL. I was not too sure

Re: [PATCH v2 1/3] powerpc/mm: Export flush_all_mm()

Le 30/08/2017 à 15:17, Michael Ellerman a écrit : Frederic Barrat <fbar...@linux.vnet.ibm.com> writes: With the optimizations introduced by commit a46cc7a90fd8 ("powerpc/mm/radix: Improve TLB/PWC flushes"), flush_tlb_mm() no longer flushes the page walk cache with r

Re: [PATCH v3 0/3] powerpc/mm: Mark memory contexts requiring global TLBIs

I'm dropping this series, as there was a recent change done in the memory context that I can reuse. The follow up of the story is: http://patchwork.ozlabs.org/patch/807570/ Fred Le 02/08/2017 à 22:29, Frederic Barrat a écrit : capi2 and opencapi require the TLB invalidations being sent

[PATCH v2 3/3] cxl: Enable global TLBIs for cxl contexts

and to avoid overflowing the counter. Signed-off-by: Frederic Barrat <fbar...@linux.vnet.ibm.com> --- Changelog: v2: Replace flush_tlb_mm() by the new flush_all_mm() to flush the TLBs and PWCs (thanks to Ben) arch/powerpc/include/asm/mmu_context.h | 35 ++ arch/p

[PATCH v2 2/3] cxl: Fix driver use count

on the detach path, so it makes more sense. It affects only the user api. The kernel api is already doing The Right Thing. Signed-off-by: Frederic Barrat <fbar...@linux.vnet.ibm.com> Cc: sta...@vger.kernel.org # v4.2+ Fixes: 7bb5d91a4dda ("cxl: Rework context lifetimes") Acked-by:

[PATCH v2 1/3] powerpc/mm: Export flush_all_mm()

With the optimizations introduced by commit a46cc7a90fd8 ("powerpc/mm/radix: Improve TLB/PWC flushes"), flush_tlb_mm() no longer flushes the page walk cache with radix. This patch introduces flush_all_mm(), which flushes everything, tlb and pwc, for a given mm. Signed-off-by: Frede

Re: [PATCH 2/2] cxl: Enable global TLBIs for cxl contexts

Le 28/08/2017 à 14:03, Benjamin Herrenschmidt a écrit : On Mon, 2017-08-28 at 10:47 +0200, Frederic Barrat wrote: Signed-off-by: Frederic Barrat <fbar...@linux.vnet.ibm.com> diff --git a/arch/powerpc/include/asm/mmu_context.h b/arch/powerpc/include/asm/mmu_context.h

Re: [PATCH] cxl: Set the valid bit in PE for dedicated mode

com> --- Acked-by: Frederic Barrat <fbar...@linux.vnet.ibm.com> Thanks! drivers/misc/cxl/native.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/misc/cxl/native.c b/drivers/misc/cxl/native.c index 4a82c313cf71..0e748c682ee9 100644 --- a/drivers/misc/cxl/native.c +++ b/

[PATCH 2/2] cxl: Enable global TLBIs for cxl contexts

and to avoid overflowing the counter. Signed-off-by: Frederic Barrat <fbar...@linux.vnet.ibm.com> diff --git a/arch/powerpc/include/asm/mmu_context.h b/arch/powerpc/include/asm/mmu_context.h index 309592589e30..6447c0df7ec4 100644 --- a/arch/powerpc/include/asm/mmu_context.h +++ b/arch/p

[PATCH 1/2] cxl: Fix driver use count

on the detach path, so it makes more sense. It affects only the user api. The kernel api is already doing The Right Thing. Signed-off-by: Frederic Barrat <fbar...@linux.vnet.ibm.com> Cc: sta...@vger.kernel.org # v4.2+ Fixes: 7bb5d91a4dda ("cxl: Rework context lifetimes") ---

Re: [PATCH 5/6] powerpc/mm: Optimize detection of thread local mm's

Le 25/08/2017 à 09:44, Benjamin Herrenschmidt a écrit : On Fri, 2017-08-25 at 06:53 +0200, Frederic Barrat wrote: Le 24/08/2017 à 20:47, Benjamin Herrenschmidt a écrit : On Thu, 2017-08-24 at 18:40 +0200, Frederic Barrat wrote: The decrementing part is giving me troubles, and I think

Re: [PATCH 5/6] powerpc/mm: Optimize detection of thread local mm's

Le 24/08/2017 à 20:47, Benjamin Herrenschmidt a écrit : On Thu, 2017-08-24 at 18:40 +0200, Frederic Barrat wrote: The decrementing part is giving me troubles, and I think it makes sense: if I decrement the counter when detaching the context from the capi card, then the next TLBIs

Re: [PATCH 5/6] powerpc/mm: Optimize detection of thread local mm's

Le 21/08/2017 à 19:35, Benjamin Herrenschmidt a écrit : On Mon, 2017-08-21 at 19:27 +0200, Frederic Barrat wrote: Hi Ben, Le 24/07/2017 à 06:28, Benjamin Herrenschmidt a écrit : Instead of comparing the whole CPU mask every time, let's keep a counter of how many bits are set in the mask

Re: [PATCH 5/6] powerpc/mm: Optimize detection of thread local mm's

Le 21/08/2017 à 19:35, Benjamin Herrenschmidt a écrit : On Mon, 2017-08-21 at 19:27 +0200, Frederic Barrat wrote: Hi Ben, Le 24/07/2017 à 06:28, Benjamin Herrenschmidt a écrit : Instead of comparing the whole CPU mask every time, let's keep a counter of how many bits are set in the mask

Re: [PATCH 5/6] powerpc/mm: Optimize detection of thread local mm's

Hi Ben, Le 24/07/2017 à 06:28, Benjamin Herrenschmidt a écrit : Instead of comparing the whole CPU mask every time, let's keep a counter of how many bits are set in the mask. Thus testing for a local mm only requires testing if that counter is 1 and the current CPU bit is set in the mask.

Re: [PATCH 5/6] powerpc/mm: Optimize detection of thread local mm's

Le 24/07/2017 à 06:28, Benjamin Herrenschmidt a écrit : Instead of comparing the whole CPU mask every time, let's keep a counter of how many bits are set in the mask. Thus testing for a local mm only requires testing if that counter is 1 and the current CPU bit is set in the mask.

[PATCH v4] powerpc/powernv: Enable PCI peer-to-peer

on the PHBs by skiboot. Signed-off-by: Frederic Barrat <fbar...@linux.vnet.ibm.com> --- Requires skiboot patch: 700611a48025c5a556bb0aa011ac81bb5d1bcbc1 Changelog: v4: - resubmit with correct opal call IDs, now that the skiboot portion is merged v3: - move target reference count from s

[PATCH v3 3/3] cxl: Add memory barrier to guarantee TLBI scope

to the device, therefore we are exposed to re-ordering. It is highly unlikely as the use count for the driver is incremented on open() and the attachment to the device happens on a different system call (ioctl) Signed-off-by: Frederic Barrat <fbar...@linux.vnet.ibm.com> --- include/misc/cxl-base.

[PATCH v3 2/3] cxl: Mark context requiring global TLBIs

for contexts actually used by the device. So mark the contexts being attached to the cxl adapter as requiring global TLBIs. Signed-off-by: Frederic Barrat <fbar...@linux.vnet.ibm.com> --- drivers/misc/cxl/api.c| 12 ++-- drivers/misc/cxl/cxllib.c | 7 +++ drivers/misc/cxl/

[PATCH v3 1/3] powerpc/mm: Add marker for contexts requiring global TLB invalidations

/PSL. The NPU and the PSL keep their own translation cache so they need to see all the TLBIs for those contexts. Rename mm_is_thread_local() to mm_is_invalidation_local() to better describe what it's doing. Signed-off-by: Frederic Barrat <fbar...@linux.vnet.ibm.com> --- arch/powerpc/inclu

[PATCH v3 0/3] powerpc/mm: Mark memory contexts requiring global TLBIs

k contexts used by XSL (cxllib) as needed global invalidation RFC v2: - address comments received - rename MM_CONTEXT_GLOBAL_TLBI -> MM_GLOBAL_TLBIE - add memory barriers to make sure the device doesn't miss any TLBI - also add barrier for the hash implemention to fix the same issue Frede

[PATCH v3] powerpc/powernv: Enable PCI peer-to-peer

on the PHBs by skiboot. Signed-off-by: Frederic Barrat <fbar...@linux.vnet.ibm.com> --- Changelog: Requires skiboot patch: http://patchwork.ozlabs.org/patch/789763/ Changelog: v3: - move target reference count from skiboot to linux v2: - change of API - allow disabling of p2p setting

Re: [PATCH v2] powerpc/powernv: Enable PCI peer-to-peer

Le 12/07/2017 à 17:39, Benjamin Herrenschmidt a écrit : On Mon, 2017-06-26 at 20:08 +0200, Frederic Barrat wrote: + if (desc & OPAL_PCI_P2P_ENABLE) { + pe_init->p2p_initiator_count++; + } else { + if (pe_init->p2p_initiator

Re: [PATCH] MAINTAINERS: Remove myself as cxl maintainer

starsw...@gmail.com Signed-off-by: Ian Munsie <imun...@au1.ibm.com> Cc: Frederic Barrat <fbar...@linux.vnet.ibm.com> Cc: Andrew Donnellan <andrew.donnel...@au1.ibm.com> Cc: linuxppc-dev@lists.ozlabs.org --- Acked-by: Frederic Barrat <fbar...@linux.vnet.ibm.com> MAIN

Re: [PATCH] MAINTAINERS: cxl: update maintainership

Le 28/06/2017 à 09:22, Andrew Donnellan a écrit : As Ian's stepping down from his maintainer role now that he's leaving IBM, Frederic has asked me to add myself to the cxl maintainer list. Updating accordingly. Cc: Frederic Barrat <fbar...@linux.vnet.ibm.com> Cc: Ian Munsie <im

Re: [PATCH v2] powerpc/powernv: Enable PCI peer-to-peer

Le 27/06/2017 à 14:32, David Laight a écrit : From: Frederic Barrat Sent: 26 June 2017 19:09 P9 has support for PCI peer-to-peer, enabling a device to write in the mmio space of another device directly, without interrupting the CPU. This patch adds support for it on powernv, by adding a new

[PATCH v2] powerpc/powernv: Enable PCI peer-to-peer

desc) It uses a new OPAL call, as the configuration magic is done on the PHBs by skiboot. Signed-off-by: Frederic Barrat <fbar...@linux.vnet.ibm.com> --- Requires skiboot patch: http://patchwork.ozlabs.org/patch/780813/ Changelog: - change of API - allow disabling of p2p setting

Re: [PATCH V4] cxl: Export library to support IBM XSL

-by: Andrew Donnellan <andrew.donnel...@au1.ibm.com> Signed-off-by: Christophe Lombard <clomb...@linux.vnet.ibm.com> --- Looks ok to me, thanks! [mpe: just to make sure you notice: there's a prereq patch listed under the changelog] Acked-by: Frederic Barrat <fbar...@linux.vnet.ibm.co

Re: [PATCH V3] cxl: Export library to support IBM XSL

Salut Christophe, Since there's a respin, 2 details below. diff --git a/drivers/misc/cxl/cxllib.c b/drivers/misc/cxl/cxllib.c new file mode 100644 index 000..4f4c5ca --- /dev/null +++ b/drivers/misc/cxl/cxllib.c @@ -0,0 +1,246 @@ +/* + * Copyright 2017 IBM Corp. + * + * This program is

[RFC v2 3/3] cxl: Add memory barrier to guarantee TLBI scope

to the device, therefore we are exposed to re-ordering. It is highly unlikely as the use count for the driver is incremented on open() and the attachment to the device happens on a different system call (ioctl) Signed-off-by: Frederic Barrat <fbar...@linux.vnet.ibm.com> --- include/misc/cxl-base.

[RFC v2 2/3] cxl: Mark context requiring global TLBIs

for contexts actually used by the device. So mark the contexts being attached to the cxl adapter as requiring global TLBIs. Signed-off-by: Frederic Barrat <fbar...@linux.vnet.ibm.com> --- drivers/misc/cxl/api.c | 12 ++-- drivers/misc/cxl/file.c | 12 ++-- 2 files chang

[RFC v2 1/3] powerpc/mm: Add marker for contexts requiring global TLB invalidations

/PSL. The NPU and the PSL keep their own translation cache so they need to see all the TLBIs for those contexts. Signed-off-by: Frederic Barrat <fbar...@linux.vnet.ibm.com> --- arch/powerpc/include/asm/book3s/64/mmu.h | 18 ++ arch/powerpc/include/asm/tlb.h

[RFC v2 0/3] powerpc/mm: Mark memory contexts requiring global TLBIs

T_GLOBAL_TLBI -> MM_GLOBAL_TLBIE - add memory barriers to make sure the device doesn't miss any TLBI - also add barrier for the hash implemention to fix the same issue Frederic Barrat (3): powerpc/mm: Add marker for contexts requiring global TLB invalidations cxl: Mark context requiring global

Re: [PATCH V2] cxl: Export library to support IBM XSL

Le 16/06/2017 à 09:13, Andrew Donnellan a écrit : +config CXL_LIB +bool +default n + How necessary is this? Are there any drivers using cxllib that we're trying to get in during this cycle? That was a Mellanox request, so that they can enable code in their driver. Like we've

Re: [PATCH V2] cxl: Export library to support IBM XSL

Salut Christophe, A few comments below, nothing major... Le 14/06/2017 à 15:29, Christophe Lombard a écrit : This patch exports a in-kernel 'library' API which can be called by other drivers to help interacting with an IBM XSL on a POWER9 system. The XSL (Translation Service Layer) is a

Re: [PATCH V3] cxl: Fixes for Coherent Accelerator Interface Architecture 2.0

to handle the checkout response status. - Add comments. Signed-off-by: Christophe Lombard <clomb...@linux.vnet.ibm.com> --- Looks good to me, thanks! Acked-by: Frederic Barrat <fbar...@linux.vnet.ibm.com> drivers/misc/cxl/context.c | 6 +++--- drivers/misc/cxl/cxl.h | 18 +-

Re: [PATCH v2 3/3] powerpc/mm/cxl: Add the fault handling cpu to mm cpumask

com> --- Reviewed-by: Frederic Barrat <fbar...@linux.vnet.ibm.com> arch/powerpc/mm/pgtable-book3s64.c | 10 +- drivers/misc/cxl/fault.c | 6 ++ 2 files changed, 7 insertions(+), 9 deletions(-) diff --git a/arch/powerpc/mm/pgtable-book3s64.c b/arch/powerp

Re: [PATCH] cxl: Fixes for Coherent Accelerator Interface Architecture 2.0

Salut Christophe, It looks pretty good, but checkpatch complains about 1 or 2 items worth fixing. 2 small remarks below. Le 09/06/2017 à 12:09, Christophe Lombard a écrit : A previous set of patches "cxl: Add support for Coherent Accelerator Interface Architecture 2.0" has introduced a new

[PATCH v2] cxl: Fix error path on bad ioctl

Fix error path if we can't copy user structure on CXL_IOCTL_START_WORK ioctl. We shouldn't unlock the context status mutex as it was not locked (yet). Signed-off-by: Frederic Barrat <fbar...@linux.vnet.ibm.com> Cc: sta...@vger.kernel.org Fixes: 0712dc7e73e5 ("cxl: Fix issues whe

Re: [PATCH] cxl: Fix error path on bad ioctl

Le 06/06/2017 à 11:20, Michael Ellerman a écrit : Frederic Barrat <fbar...@linux.vnet.ibm.com> writes: Fix error path if we can't copy user structure on CXL_IOCTL_START_WORK ioctl. To be clear the error is that returning via the out label will unlock cxl->status_mutex, which has

Re: [PATCH v2] cxl: Avoid double free_irq() for psl,slice interrupts

aib...@linux.vnet.ibm.com> --- Thanks for the correction. Acked-by: Frederic Barrat <fbar...@linux.vnet.ibm.com> Fred Changelog: v2: - Use psl_hwirq instead of psl_virq to find irq mapping in cxl_native_release_psl_irq as pointed out by Fred. Re-send: - Added stable to recipients --- drivers/misc/

[PATCH] cxl: Fix error path on bad ioctl

Fix error path if we can't copy user structure on CXL_IOCTL_START_WORK ioctl. Signed-off-by: Frederic Barrat <fbar...@linux.vnet.ibm.com> Cc: sta...@vger.kernel.org --- drivers/misc/cxl/file.c | 6 ++ 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/misc/cxl/fi

Re: [RESEND-PATCH] cxl: Avoid double free_irq() for psl,slice interrupts

Le 02/06/2017 à 11:35, Vaibhav Jain a écrit : During an eeh call to cxl_remove can result in double free_irq of psl,slice interrupts. This can happen if perst_reloads_same_image == 1 and call to cxl_configure_adapter() fails during slot_reset callback. In such a case we see a kernel oops with

[PATCH] powerpc/powernv: Enable PCI peer-to-peer

pci_dev *dev); int pnv_pci_set_p2p_receiver(struct pci_dev *dev); It uses a new OPAL call, as the configuration magic is done on the PHBs by skiboot. Signed-off-by: Frederic Barrat <fbar...@linux.vnet.ibm.com> --- Need skiboot patch: http://patchwork.ozlabs.org/patch/768613/ arch/p

Re: [RFC 1/2] powerpc/mm: Add marker for contexts requiring global TLB invalidations

Le 04/05/2017 à 11:42, Michael Ellerman a écrit : Frederic Barrat <fbar...@linux.vnet.ibm.com> writes: Introduce a new 'flags' attribute per context and define its first bit to be a marker requiring all TLBIs for that context to be broadcasted globally. Once that marker is set on a c

Re: [RFC 2/2] cxl: Mark context requiring global TLBIs

Le 04/05/2017 à 09:39, Balbir Singh a écrit : On Wed, 2017-05-03 at 16:29 +0200, Frederic Barrat wrote: The PSL needs to see all TLBI pertinent to the memory contexts used on the cxl adapter. For the hash memory model, it was done by making all TLBIs global as soon as the cxl driver is in us

Re: [PATCH] cxl: Unlock on error in probe

Le 05/05/2017 à 07:34, Dan Carpenter a écrit : We should unlock if get_cxl_adapter() fails. Fixes: 594ff7d067ca ("cxl: Support to flash a new image on the adapter from a guest") Signed-off-by: Dan Carpenter <dan.carpen...@oracle.com> Acked-by: Frederic Barrat <fbar...

Re: [RFC 1/2] powerpc/mm: Add marker for contexts requiring global TLB invalidations

Le 04/05/2017 à 08:41, Aneesh Kumar K.V a écrit : Frederic Barrat <fbar...@linux.vnet.ibm.com> writes: Introduce a new 'flags' attribute per context and define its first bit to be a marker requiring all TLBIs for that context to be broadcasted globally. Once that marker is set on a c

[RFC 0/2] powerpc/mm: Mark memory contexts requiring global TLBIs

y the card. Alistair: for nvlink2, it is my understanding that all the required invalidations are already in place through software mmio/ATSD, i.e. this patch is not useful for you. Submitting as an RFC, since I don't get to touch mmu.h everyday and would like to probe people's reaction. Frederic

[RFC 2/2] cxl: Mark context requiring global TLBIs

for contexts actually used by the device. So mark the contexts being attached to the cxl adapter as requiring global TLBIs. Signed-off-by: Frederic Barrat <fbar...@linux.vnet.ibm.com> --- drivers/misc/cxl/api.c | 5 - drivers/misc/cxl/file.c | 5 - 2 files changed, 8 insertions(+), 2 del

[RFC 1/2] powerpc/mm: Add marker for contexts requiring global TLB invalidations

/PSL. The NPU and the PSL keep their own translation cache so they need to see all the TLBIs for those contexts. Signed-off-by: Frederic Barrat <fbar...@linux.vnet.ibm.com> --- arch/powerpc/include/asm/book3s/64/mmu.h | 9 + arch/powerpc/include/asm/tlb.h | 10 --

Re: [PATCH v4] cxl: mask slice error interrupts after first occurrence

t once, then mask it off to prevent it from being retriggered until the AFU is reset. Signed-off-by: Alastair D'Silva <alast...@d-silva.org> --- Thanks! Acked-by: Frederic Barrat <fbar...@linux.vnet.ibm.com> Changelog: v4: Fix duplicate/missing entries in aggregate macros

Re: [PATCH v3] cxl: mask slice error interrupts after first occurrence

_IRQ_MASKS ( \ + CXL_PSL_SERR_An_afuto_mask | CXL_PSL_SERR_An_afudup_mask | CXL_PSL_SERR_An_afuov_mask | \ + CXL_PSL_SERR_An_badsrc_mask | CXL_PSL_SERR_An_badctx_mask | CXL_PSL_SERR_An_llcmdis_mask | \ + CXL_PSL_SERR_An_llcmdto_mask | CXL_PSL_SERR_An_afupar_mask | CXL_PSL_

Re: [PATCH] cxl: Prevent IRQ storm

Le 26/04/2017 à 08:40, Alastair D'Silva a écrit : From: Alastair D'Silva In some situations, a faulty AFU slice may create an interrupt storm, rendering the machine unusable. Since these interrupts are informational only, present the interrupt once, then mask it off to

Re: [PATCH] cxl: Route eeh events to all drivers in cxl_pci_error_detected()

Jain <vaib...@linux.vnet.ibm.com> --- Looks ok to me. At least we are consistent with what is done in cxl_vphb_error_detected() Acked-by: Frederic Barrat <fbar...@linux.vnet.ibm.com> drivers/misc/cxl/pci.c | 15 +-- 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/

[PATCH V4 7/7 remix] cxl: Add psl9 specific code

<clomb...@linux.vnet.ibm.com> Acked-by: Frederic Barrat <fbar...@linux.vnet.ibm.com> --- Documentation/powerpc/cxl.txt | 15 ++- drivers/misc/cxl/context.c| 16 ++- drivers/misc/cxl/cxl.h| 137 --- drivers/misc/cxl/debugfs.c| 19 drivers/misc/cxl/

Re: [PATCH V4 7/7] cxl: Add psl9 specific code

Le 12/04/2017 à 09:52, Andrew Donnellan a écrit : On 08/04/17 00:11, Christophe Lombard wrote: +static u32 get_phb_index(struct device_node *np) { u32 phb_index; if (of_property_read_u32(np, "ibm,phb-index", _index)) -return 0; +return -ENODEV; Function is

Re: [PATCH V4 7/7] cxl: Add psl9 specific code

Le 07/04/2017 à 16:11, Christophe Lombard a écrit : The new Coherent Accelerator Interface Architecture, level 2, for the IBM POWER9 brings new content and features: - POWER9 Service Layer - Registers - Radix mode - Process element entry - Dedicated-Shared Process Programming Model -

Re: [PATCH v4] cxl: Force context lock during EEH flow

Le 11/04/2017 à 12:40, Michael Ellerman a écrit : Frederic Barrat <fbar...@linux.vnet.ibm.com> writes: Le 05/04/2017 à 13:35, Vaibhav Jain a écrit : During an eeh event when the cxl card is fenced and card sysfs attr perst_reloads_same_image is set following warning message i

Re: [PATCH V4 6/7] cxl: Isolate few psl8 specific calls

hanges in native.c which are about splitting long strings, but that's minor. And the rest looks ok. I'll do the last patch tomorrow. Acked-by: Frederic Barrat <fbar...@linux.vnet.ibm.com> drivers/misc/cxl/context.c | 28 +++- drivers/misc/cxl/cx

Re: [PATCH V4 5/7] cxl: Rename some psl8 specific functions

<clomb...@linux.vnet.ibm.com> --- Acked-by: Frederic Barrat <fbar...@linux.vnet.ibm.com> drivers/misc/cxl/cxl.h | 26 ++-- drivers/misc/cxl/debugfs.c | 6 ++--- drivers/misc/cxl/guest.c | 2 +- drivers/misc/cxl/irq.c | 2 +- drivers/misc/cxl/na

Re: [PATCH V4 4/7] cxl: Update implementation service layer

Acked-by: Frederic Barrat <fbar...@linux.vnet.ibm.com> drivers/misc/cxl/cxl.h | 40 +++-- drivers/misc/cxl/debugfs.c | 16 +++--- drivers/misc/cxl/guest.c | 2 +- drivers/misc/cxl/irq.c | 2 +- drivers/misc/cxl/na

Re: [PATCH V4 3/7] cxl: Keep track of mm struct associated with a context

), of the structure cxl_context, is removed because it's no longer useful. Signed-off-by: Christophe Lombard <clomb...@linux.vnet.ibm.com> --- Thanks for the update, I think it looks good now. Acked-by: Frederic Barrat <fbar...@linux.vnet.ibm.com> drivers/misc/cxl/api.c | 17

Re: [PATCH V4 2/7] cxl: Remove unused values in bare-metal environment.

Acked-by: Frederic Barrat <fbar...@linux.vnet.ibm.com> drivers/misc/cxl/cxl.h| 20 drivers/misc/cxl/hcalls.c | 6 +++--- drivers/misc/cxl/native.c | 5 - 3 files changed, 7 insertions(+), 24 deletions(-) diff --git a/drivers/misc/cxl/cxl.h b/drivers/misc/cxl/cxl.h i

Re: [PATCH V4 1/7] cxl: Read vsec perst load image

will be used by the following patches. Signed-off-by: Christophe Lombard <clomb...@linux.vnet.ibm.com> --- Acked-by: Frederic Barrat <fbar...@linux.vnet.ibm.com> drivers/misc/cxl/pci.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/misc/cxl/pci.c b/drivers/misc/cxl

Re: [PATCH v4] cxl: Force context lock during EEH flow

-drivers. Cc: sta...@vger.kernel.org Fixes: 70b565bbdb91("cxl: Prevent adapter reset if an active context exists") Reported-by: Andrew Donnellan <andrew.donnel...@au1.ibm.com> Signed-off-by: Vaibhav Jain <vaib...@linux.vnet.ibm.com> --- Pending test result from cxl-flash: Ack

Re: [PATCH v3] cxl: Force context lock during EEH flow

Hi Vaibhav, I like the simplified version better. However, I think it breaks cxlflash's recovery. With this patch, we are also unlocking the adapter later. It doesn't matter when the driver initializes the first time, but on EEH, we now call the "slot reset" callback of the virtual device

Re: [PATCH V3 7/7] cxl: Add psl9 specific code

Le 28/03/2017 à 17:14, Christophe Lombard a écrit : The new Coherent Accelerator Interface Architecture, level 2, for the IBM POWER9 brings new content and features: - POWER9 Service Layer - Registers - Radix mode - Process element entry - Dedicated-Shared Process Programming Model -

Re: [PATCH V3 6/7] cxl: Isolate few psl8 specific calls

Le 28/03/2017 à 17:14, Christophe Lombard a écrit : Point out the specific Coherent Accelerator Interface Architecture, level 1, registers. Code and functions specific to PSL8 (CAIA1) must be framed. Signed-off-by: Christophe Lombard ---

Re: [PATCH V3 5/7] cxl: Rename some psl8 specific functions

<clomb...@linux.vnet.ibm.com> --- Acked-by: Frederic Barrat <fbar...@linux.vnet.ibm.com> drivers/misc/cxl/cxl.h | 26 +- drivers/misc/cxl/debugfs.c | 6 +++--- drivers/misc/cxl/guest.c | 2 +- drivers/misc/cxl/irq.c | 2 +- drivers/misc/cxl/na

Re: [PATCH V3 4/7] cxl: Update implementation service layer

Le 28/03/2017 à 17:14, Christophe Lombard a écrit : The service layer API (in cxl.h) lists some low-level functions whose implementation is different on PSL8, PSL9 and XSL: - Init implementation for the adapter and the afu. - Invalidate TLB/SLB. - Attach process for dedicated/directed models.

Re: [PATCH V3 3/7] cxl: Keep track of mm struct associated with a context

Le 28/03/2017 à 17:14, Christophe Lombard a écrit : The mm_struct corresponding to the current task is acquired each time an interrupt is raised. So to simplify the code, we only get the mm_struct when attaching an AFU context to the process. The mm_count reference is increased to ensure that

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