[PATCH v2 18/20] KVM: PPC: Book3S HV: Allow guest exit path to have MMU on

to handle, we branch to the relocation-on version of the interrupt vector. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/kvm/book3s_hv_builtin.c| 38 ++--- arch/powerpc/kvm/book3s_hv_rm_xics.c| 8 +++ arch/power

[PATCH v2 17/20] KVM: PPC: Book3S HV: Invalidate TLB on radix guest vcpu movement

ush, this moves the clearing of the bit from before the actual flush to after it. This way, two threads might both do the flush, but we prevent the situation where one thread can enter the guest before the flush is finished. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/in

[PATCH v2 16/20] KVM: PPC: Book3S HV: Make HPT-specific hypercalls return error in radix mode

If the guest is in radix mode, then it doesn't have a hashed page table (HPT), so all of the hypercalls that manipulate the HPT can't work and should return an error. This adds checks to make them return H_FUNCTION ("function not supported"). Signed-off-by: Paul Mackerras <pau.

[PATCH v2 15/20] KVM: PPC: Book3S HV: Implement dirty page logging for radix guests

e.g., when the page was paged out). This bitmap is stored in the first half of the memslot->dirty_bitmap area, and kvm_vm_ioctl_get_dirty_log_hv() now uses the second half for the bitmap that gets returned to userspace. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc

[PATCH v2 14/20] KVM: PPC: Book3S HV: MMU notifier callbacks for radix guests

need to traverse rmap chains. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/include/asm/kvm_book3s.h | 6 arch/powerpc/kvm/book3s_64_mmu_hv.c| 64 +++--- arch/powerpc/kvm/book3s_64_mmu_radix.c | 54 3

[PATCH v2 13/20] KVM: PPC: Book3S HV: Page table construction and page faults for radix guests

This adds the code to construct the second-level ("partition-scoped" in architecturese) page tables for guests using the radix MMU. Apart from the PGD level, which is allocated when the guest is created, the rest of the tree is all constructed in response to hypervisor page faults. As well as

[PATCH v2 12/20] KVM: PPC: Book3S HV: Modify guest entry/exit paths to handle radix guests

register. On hypervisor data/instruction storage interrupts, we don't do the guest HPT lookup on radix, but just save the guest physical address for the fault (from the ASDR register) in the vcpu struct. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/include/asm/kvm_

[PATCH v2 11/20] KVM: PPC: Book3S HV: Add basic infrastructure for radix guests

-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/include/asm/kvm_book3s.h| 3 + arch/powerpc/include/asm/kvm_book3s_64.h | 6 ++ arch/powerpc/include/asm/kvm_host.h | 2 + arch/powerpc/kvm/Makefile| 3 +- arch/powerpc/kvm/book3s_64_mmu_hv.c | 10 ++-

[PATCH v2 10/20] KVM: PPC: Book3S HV: Use ASDR for HPT guests on POWER9

address of the access.) Thus, for HPT guests on POWER9, we can use this register rather than looking up the SLB with the slbfee. instruction. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/kvm/book3s_hv_rmhandlers.S | 8 1 file changed, 8 insertions(+) diff --git

[PATCH v2 09/20] KVM: PPC: Book3S HV: Set process table for HPT guests on POWER9

This adds the implementation of the KVM_PPC_CONFIGURE_V3_MMU ioctl for HPT guests on POWER9. With this, we can return 1 for the KVM_CAP_PPC_MMU_HASH_V3 capability. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/include/asm/kvm_host.h | 1 + arch/powerpc/kvm/book3

[PATCH v2 08/20] KVM: PPC: Book3S HV: Add userspace interfaces for POWER9 MMU

for the TLB invalidate entry instruction. Initially, both capabilities return 0 and the ioctls return -EINVAL, until the necessary infrastructure for them to operate correctly is added. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- Documentation/virtual/kvm/api.txt

[PATCH v2 07/20] powerpc/64: Allow for relocation-on interrupts from guest to host

occur with relocation on in radix guests. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/include/asm/exception-64s.h | 10 +++--- arch/powerpc/kernel/exceptions-64s.S | 53 +--- 2 files changed, 34 insertions(+), 29 deletions(-) diff --git

[PATCH v2 06/20] powerpc/64: Make type of partition table flush depend on partition type

if the partition was previously a radix partition and 0 if it was a HPT partition. This implements that logic. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/mm/pgtable_64.c | 16 +--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/mm/pgta

[PATCH v2 05/20] powerpc/64: Export pgtable_cache and pgtable_cache_add for KVM

This exports the pgtable_cache array and the pgtable_cache_add function so that HV KVM can use them for allocating radix page tables for guests. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/mm/init-common.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff

[PATCH v2 04/20] powerpc/64: More definitions for POWER9

This adds definitions for bits in the DSISR register which are used by POWER9 for various translation-related exception conditions, and for some more bits in the partition table entry that will be needed by KVM. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/inclu

[PATCH v2 03/20] powerpc/64: Enable use of radix MMU under hypervisor on POWER9

table, which points to the radix tree for each process, we need to install that using the H_REGISTER_PROC_TBL hcall. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/include/asm/book3s/64/mmu.h | 2 ++ arch/powerpc/include/asm/hvcall.h| 11 +++ arch/p

[PATCH v2 02/20] powerpc/pseries: Fixes for the "ibm, architecture-vec-5" options

tion is in byte 21 not byte 15. Note none of these options are actually looked up in "ibm,architecture-vec-5" at this time, so there is no bug. When checking whether option bits are set, we should check that the offset of the byte being checked is less than the vector length that we got f

[PATCH v2 01/20] powerpc/64: Don't try to use radix MMU under a hypervisor

the hypervisor agreed to us using radix. Cc: sta...@vger.kernel.org # v4.8+ Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/mm/init_64.c | 33 + 1 file changed, 33 insertions(+) diff --git a/arch/powerpc/mm/init_64.c b/arch/powerpc/mm/init_64.c

[PATCH v2 00/20] Support for radix guest and host on POWER9

The primary purpose of this patch series is to make it possible to run a guest on POWER9 using the radix MMU under a KVM host that also uses the radix MMU. To do this, the guest needs to say that it supports radix in the ibm,client-architecture-support vector, and if the host agrees, the guest

Re: [PATCH] KVM: PPC: Book3S PR: Refactor program interrupt related code into separate function

On Wed, Jan 25, 2017 at 01:27:22PM +0100, Thomas Huth wrote: > The function kvmppc_handle_exit_pr() is quite huge and thus hard to read, > and even contains a "spaghetti-code"-like goto between the different case > labels of the big switch statement. This can be made much more readable > by moving

Re: [PATCH v5 2/2] KVM: PPC: Exit guest upon MCE when FWNMI capability is enabled

On Wed, Jan 18, 2017 at 11:19:26AM +0530, Mahesh Jagannath Salgaonkar wrote: > On 01/16/2017 10:05 AM, Paul Mackerras wrote: > > On Fri, Jan 13, 2017 at 04:51:45PM +0530, Aravinda Prasad wrote: [snip] > >>case BOOK3S_INTERRUPT_MACHINE_CHECK: > >> + /* Exit

Re: [PATCH 3/3] KVM: PPC: Book3S: 64-bit CONFIG_RELOCATABLE support for interrupts

> Signed-off-by: Nicholas Piggin <npig...@gmail.com> Looks OK to me. I have a slight quibble about the naming of the "BRANCH_LINK_TO_KVM" macro because neither its definition nor the place where it's used have anything to do with KVM as far as I can see. That needn't stop t

Re: [PATCH 2/3] KVM: PPC: Book3S: Move 64-bit KVM interrupt handler out from alt section

rea > (name is arbitrary) in order to be closer to .text and avoid the dreaded > "relocation truncated to fit" error. > > Signed-off-by: Nicholas Piggin <npig...@gmail.com> Acked-by: Paul Mackerras <pau...@ozlabs.org>

Re: [PATCH 1/3] KVM: PPC: Book3S: Change interrupt call to reduce scratch space use on HV

back > to match the previous call convention (i.e., shared with 32-bit), for > simplicity. > > Signed-off-by: Nicholas Piggin <npig...@gmail.com> Acked-by: Paul Mackerras <pau...@ozlabs.org> I notice that I forgot to add the code to save CFAR to the __KVM_HANDLER_SKIP macro. We should fix that. Paul.

Re: [PATCH 13/18] KVM: PPC: Book3S HV: Page table construction and page faults for radix guests

On Mon, Jan 23, 2017 at 02:17:20PM +1100, Suraj Jitindar Singh wrote: > On Thu, 2017-01-12 at 20:07 +1100, Paul Mackerras wrote: > > This adds the code to construct the second-level ("partition-scoped" > > in > > architecturese) page tables for guests using

Re: [PATCH 10/18] KVM: PPC: Book3S HV: Set process table for HPT guests on POWER9

On Mon, Jan 23, 2017 at 01:39:27PM +1100, Suraj Jitindar Singh wrote: > On Thu, 2017-01-12 at 20:07 +1100, Paul Mackerras wrote: > > This adds the implementation of the KVM_PPC_CONFIGURE_V3_MMU ioctl > > for HPT guests on POWER9.  With this, we can return 1 for the > > KV

Re: [PATCH v5 2/2] KVM: PPC: Exit guest upon MCE when FWNMI capability is enabled

On Fri, Jan 13, 2017 at 04:51:45PM +0530, Aravinda Prasad wrote: > Enhance KVM to cause a guest exit with KVM_EXIT_NMI > exit reason upon a machine check exception (MCE) in > the guest address space if the KVM_CAP_PPC_FWNMI > capability is enabled (instead of delivering a 0x200 > interrupt to

Re: [PATCH v4 1/2] KVM: PPC: Add new capability to control MCE behaviour

On Mon, Jan 09, 2017 at 05:10:35PM +0530, Aravinda Prasad wrote: > This patch introduces a new KVM capability to control > how KVM behaves on machine check exception (MCE). > Without this capability, KVM redirects machine check > exceptions to guest's 0x200 vector, if the address in > error

[PATCH 18/18] KVM: PPC: Book3S HV: Use ASDR for HPT guests on POWER9

address of the access.) Thus, for HPT guests on POWER9, we can use this register rather than looking up the SLB with the slbfee. instruction. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/kvm/book3s_hv_rmhandlers.S | 8 1 file changed, 8 insertions(+) diff --git

[PATCH 17/18] KVM: PPC: Book3S HV: Enable radix guest support

one mode to the other, which enables some simplifications. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/include/asm/kvm_book3s.h | 2 + arch/powerpc/kvm/book3s_64_mmu_hv.c| 1 - arch/powerpc/kvm/book3s_64_mmu_radix.c | 45 arch/powerpc/kvm/book3

[PATCH 16/18] KVM: PPC: Book3S HV: Make HPT-specific hypercalls return error in radix mode

If the guest is in radix mode, then it doesn't have a hashed page table (HPT), so all of the hypercalls that manipulate the HPT can't work and should return an error. This adds checks to make them return H_FUNCTION ("function not supported"). Signed-off-by: Paul Mackerras <pau.

[PATCH 15/18] KVM: PPC: Book3S HV: Implement dirty page logging for radix guests

e.g., when the page was paged out). This bitmap is stored in the first half of the memslot->dirty_bitmap area, and kvm_vm_ioctl_get_dirty_log_hv() now uses the second half for the bitmap that gets returned to userspace. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc

[PATCH 14/18] KVM: PPC: Book3S HV: MMU notifier callbacks for radix guests

need to traverse rmap chains. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/include/asm/kvm_book3s.h | 6 arch/powerpc/kvm/book3s_64_mmu_hv.c| 64 +++--- arch/powerpc/kvm/book3s_64_mmu_radix.c | 54 3

[PATCH 13/18] KVM: PPC: Book3S HV: Page table construction and page faults for radix guests

This adds the code to construct the second-level ("partition-scoped" in architecturese) page tables for guests using the radix MMU. Apart from the PGD level, which is allocated when the guest is created, the rest of the tree is all constructed in response to hypervisor page faults. As well as

[PATCH 12/18] KVM: PPC: Book3S HV: Modify guest entry/exit paths to handle radix guests

the host value for the PID register. On hypervisor data/instruction storage interrupts, we don't do the guest HPT lookup on radix, but just save the guest physical address for the fault (from the ASDR register) in the vcpu struct. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/p

[PATCH 11/18] KVM: PPC: Book3S HV: Add basic infrastructure for radix guests

-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/include/asm/kvm_book3s.h| 3 + arch/powerpc/include/asm/kvm_book3s_64.h | 6 ++ arch/powerpc/include/asm/kvm_host.h | 2 + arch/powerpc/kvm/Makefile| 3 +- arch/powerpc/kvm/book3s_64_mmu_hv.c | 10 ++-

[PATCH 10/18] KVM: PPC: Book3S HV: Set process table for HPT guests on POWER9

This adds the implementation of the KVM_PPC_CONFIGURE_V3_MMU ioctl for HPT guests on POWER9. With this, we can return 1 for the KVM_CAP_PPC_MMU_HASH_V3 capability. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/include/asm/kvm_host.h | 1 + arch/powerpc/kvm/book3

[PATCH 09/18] KVM: PPC: Book3S HV: Add userspace interfaces for POWER9 MMU

for the TLB invalidate entry instruction. Initially, both capabilities return 0 and the ioctls return -EINVAL, until the necessary infrastructure for them to operate correctly is added. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- Documentation/virtual/kvm/api.txt

[PATCH 08/18] KVM: PPC: Book3S HV: Don't try to signal cpu -1

t to kvmppc_ipi_thread(). Fixes: 1704a81ccebc ("KVM: PPC: Book3S HV: Use msgsnd for IPIs to other cores on POWER9") Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/kvm/book3s_hv.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/kvm/book3s_h

[PATCH 07/18] powerpc/64: Make type of partition table flush depend on partition type

if the partition was previously a radix partition and 0 if it was a HPT partition. This implements that logic. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/mm/pgtable_64.c | 16 +--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/mm/pgta

[PATCH 06/18] powerpc/64: Export pgtable_cache and pgtable_cache_add for KVM

This exports the pgtable_cache array and the pgtable_cache_add function so that HV KVM can use them for allocating radix page tables for guests. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/mm/init-common.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff

[PATCH 05/18] powerpc/64: More definitions for POWER9

This adds definitions for bits in the DSISR register which are used by POWER9 for various translation-related exception conditions, and for some more bits in the partition table entry that will be needed by KVM. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/inclu

[PATCH 04/18] powerpc/64: Enable use of radix MMU under hypervisor on POWER9

table, which points to the radix tree for each process, we need to install that using the H_REGISTER_PROC_TBL hcall. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/include/asm/book3s/64/mmu.h | 2 ++ arch/powerpc/include/asm/hvcall.h| 11 +++ arch/p

[PATCH 03/18] powerpc/64: Always enable radix support for 64-bit Book 3S kernels

of option combinations that need to be tested, which is an ongoing burden on developers. Given that the space savings are small, let's remove the option. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/platforms/Kconfig.cputype | 7 +-- 1 file changed, 1 insertion

[PATCH 02/18] powerpc/64: Fixes for the ibm, client-architecture-support options

option is in byte 21 not byte 15. When checking whether option bits are set, we should check that the offset of the byte being checked is less than the vector length that we got from the hypervisor. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/include/asm/prom.h

[PATCH 01/18] powerpc/64: Don't try to use radix MMU under a hypervisor

the hypervisor agreed to us using radix. Cc: sta...@vger.kernel.org # v4.8+ Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/mm/init_64.c | 33 + 1 file changed, 33 insertions(+) diff --git a/arch/powerpc/mm/init_64.c b/arch/powerpc/mm/init_64.c

[PATCH 00/18] Support for radix guest and host on POWER9

The primary purpose of this patch series is to make it possible to run a guest on POWER9 using the radix MMU under a KVM host that also uses the radix MMU. To do this, the guest needs to say that it supports radix in the ibm,client-architecture-support vector, and if the host agrees, the guest

Re: [PATCH] powerpc/64: Don't try to use radix MMU under a hypervisor

On Tue, Dec 20, 2016 at 08:19:02PM +0530, Aneesh Kumar K.V wrote: > Paul Mackerras <pau...@ozlabs.org> writes: > > > Currently, if the kernel is running on a POWER9 processor under a > > hypervisor, it will try to use the radix MMU even though it doesn't > > have t

[PATCH] powerpc/64: Don't try to use radix MMU under a hypervisor

agreed to us using radix. Fixes: 17a3dd2f5fc7 ("powerpc/mm/radix: Use firmware feature to enable Radix MMU") Cc: sta...@vger.kernel.org # v4.7+ Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/mm/init_64.c | 27 +++ 1 file changed, 27 insertion

Re: [PATCH] powerpc: Fix LPCR_VRMASD definition

On Thu, Dec 08, 2016 at 11:29:30AM +0800, Jia He wrote: > Fixes: a4b349540a ("powerpc/mm: Cleanup LPCR defines") > Signed-off-by: Jia He <hejia...@gmail.com> Acked-by: Paul Mackerras <pau...@ozlabs.org>

Re: [PATCH] powerpc/mm: Fixup wrong LPCR_VRMASD value

On Thu, Dec 08, 2016 at 09:12:13AM +0530, Aneesh Kumar K.V wrote: > In commit a4b349540a26af ("powerpc/mm: Cleanup LPCR defines") we updated > LPCR_VRMASD wrongly as below. > > -#define LPCR_VRMASD (0x1ful << (63-16)) > +#define LPCR_VRMASD_SH 47 > +#define LPCR_VRMASD

Re: [PATCH 1/3] KVM: PPC: Book3S: Change interrupt call to reduce scratch space use on HV

On Thu, Dec 01, 2016 at 06:18:10PM +1100, Nicholas Piggin wrote: > Change the calling convention to put the trap number together with > CR in two halves of r12, which frees up HSTATE_SCRATCH2 in the HV > handler, and r9 free. Cute idea! Some comments below... > The 64-bit PR handler entry

[PATCH RFC v2 3/3] powerpc/64: Enable use of radix MMU under hypervisor on POWER9

table, which points to the radix tree for each process, we need to install that using the H_REGISTER_PROC_TBL hcall. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/include/asm/book3s/64/mmu.h | 2 ++ arch/powerpc/include/asm/hvcall.h| 11 +++ arch/p

Re: [PATCH RFC 3/3] powerpc/64: Enable use of radix MMU under hypervisor on POWER9

On Mon, Dec 05, 2016 at 07:55:32PM +1100, Benjamin Herrenschmidt wrote: > On Mon, 2016-12-05 at 19:04 +1100, Paul Mackerras wrote: > > +   vec5 = of_get_flat_dt_prop(chosen, "ibm,architecture-vec-5", ); > > +   if (!vec5 || size <= OV5_INDX(OV5_MMU_RADIX_300)

[PATCH RFC 3/3] powerpc/64: Enable use of radix MMU under hypervisor on POWER9

table, which points to the radix tree for each process, we need to install that using the H_REGISTER_PROC_TBL hcall. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/include/asm/book3s/64/mmu.h | 2 ++ arch/powerpc/include/asm/hvcall.h| 11 +++ arch/p

[PATCH RFC 2/3] powerpc/64: Always enable radix support for 64-bit Book 3S kernels

of option combinations that need to be tested, which is an ongoing burden on developers, as well as increasing the number of #ifdefs in the code. Given that the space savings are small, let's remove the option. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/pla

[PATCH 1/3] powerpc/64: Fixes for the ibm,client-architecture-support options

option is in byte 21 not byte 15. When checking whether option bits are set, we should check that the offset of the byte being checked is less than the vector length that we got from the hypervisor. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/include/asm/prom.h

[PATCH] KVM: PPC: Book3S: Move prototypes for KVM functions into kvm_ppc.h

but given that the functions are KVM functions, having them in a KVM header will be better for long-term maintenance. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- [For information; I intend to merge this through the KVM tree.] arch/powerpc/include/asm/asm-prototypes.h | 44 -

Re: [PATCH v5 1/7] powerpc/mm: update ptep_set_access_flag to not do full mm tlb flush

On Wed, Nov 23, 2016 at 04:39:57PM +0530, Aneesh Kumar K.V wrote: > When we are updating pte, we just need to flush the tlb mapping for > that pte. Right now we do a full mm flush because we don't track page > size. Update the interface to track the page size and use that to > do the right tlb

Re: [PATCH 0/2] Preliminary cleanups for HPT resizing

On Wed, Nov 23, 2016 at 04:14:05PM +1100, David Gibson wrote: > Hi Paul, > > I'm still chasing this confusion about the CAS bit to send the real > HPT resizing patches. However, in the meantime, here are some > preliminary cleanups. > > These cleanups stand on their own, although I wrote them

Re: [PATCH 00/11] KVM: PPC: Book3S HV: Support KVM guests on POWER9

On Wed, Nov 23, 2016 at 11:31:54AM +1100, Paul Mackerras wrote: > This series of patches adds support to HV KVM for running KVM guests > on POWER9 systems. This allows us to run KVM guests that use HPT > (hashed page table) address translation and know about the POWER9 > processor. W

[PATCH v2 11/11] KVM: PPC: Book3S HV: Update kvmppc_set_arch_compat() for ISA v3.00

v3.00 of the ISA which adds an ISA v2.07 compatilibity mode to the PCR. We also add a check to ensure the processor we are running on is capable of emulating the chosen processor (for example a POWER7 cannot emulate a POWER8, similarly with a POWER8 and a POWER9). Based on work by: Paul Mackerra

[PATCH v2 10/11] KVM: PPC: Book3S HV: Treat POWER9 CPU threads as independent subcores

on POWER9 as long as the host is running with HPT translation. Since userspace currently has no way to request radix tree translation for the guest, the guest has no choice but to use HPT translation. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/kvm/book3s_hv.

[PATCH v2 09/11] KVM: PPC: Book3S HV: Enable hypervisor virtualization interrupts while in guest

hypervisor virtualization interrupts can occur while we are in the guest. We then also need to cope with exiting the guest because of a hypervisor virtualization interrupt. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/include/asm/kvm_asm.h | 1 + arch/powerpc

[PATCH v2 08/11] KVM: PPC: Book3S HV: Use stop instruction rather than nap on POWER9

ring guest execution with the stop instruction, and adds code to set PSSCR to a value which will allow an SMT mode switch while the thread is idle (given that the core as a whole won't be idle in these cases). Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/kvm/book3s_hv_r

[PATCH v2 07/11] KVM: PPC: Book3S HV: Use OPAL XICS emulation on POWER9

turns from kvmppc_read_one_intr(). Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/include/asm/kvm_ppc.h | 7 +++-- arch/powerpc/kvm/book3s_hv.c | 28 +++-- arch/powerpc/kvm/book3s_hv_builtin.c | 59 ++-- arch/powerpc/kvm/book3s_h

[PATCH v2 05/11] KVM: PPC: Book3S HV: Adapt TLB invalidations to work on POWER9

, we don't need to do the TLB flush on first entry to the guest on each processor. Therefore we don't set all bits in the tlb_need_flush bitmap on VM startup on POWER9. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/include/asm/kvm_host.h | 1 + arch/powerpc/kern

[PATCH v2 06/11] KVM: PPC: Book3S HV: Use msgsnd for IPIs to other cores on POWER9

On POWER9, the msgsnd instruction is able to send interrupts to other cores, as well as other threads on the local core. Since msgsnd is generally simpler and faster than sending an IPI via the XICS, we use msgsnd for all IPIs sent by KVM on POWER9. Signed-off-by: Paul Mackerras <

[PATCH v2 03/11] KVM: PPC: Book3S HV: Adjust host/guest context switch for POWER9

, but we had to context-switch them on POWER8 to avoid creating a covert channel. They are: SPMC1, SPMC2, MMCRS, CSIGR, TACR, TCSCR, and ACOP. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/kvm/book3s_hv_rmhandlers.S | 50 - 1 file chang

[PATCH v2 04/11] KVM: PPC: Book3S HV: Add new POWER9 guest-accessible SPRs

contains some fields which are guest-accessible and some which are only accessible in hypervisor mode. We only allow the guest-accessible fields to be read or set by userspace. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- Documentation/virtual/kvm/api.txt | 2 ++ arch/p

[PATCH v2 02/11] KVM: PPC: Book3S HV: Set partition table rather than SDR1 on POWER9

(logical partition ID register), not the SDR1 register. There is also no requirement now to transition via a reserved LPID value. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/kvm/book3s_hv.c| 36 +++-- arch/powerpc/kvm/book3s_hv_rmhand

[PATCH v2 01/11] KVM: PPC: Book3S HV: Adapt to new HPTE format on POWER9

) and ARPN (abbreviated real page number) fields. As far as possible, the conversion is done when reading or writing the HPT entries, and the rest of the code continues to use the old format. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/kvm/book3s_64_mmu_hv.c

[PATCH 00/11] KVM: PPC: Book3S HV: Support KVM guests on POWER9

This series of patches adds support to HV KVM for running KVM guests on POWER9 systems. This allows us to run KVM guests that use HPT (hashed page table) address translation and know about the POWER9 processor. With suitable changes to the user-mode driver, this can also run guests on POWER9 in

Re: [PATCH v2] powernv: Handle wakeup from idle due to SRESET

On Tue, Nov 22, 2016 at 11:06:32PM +0530, Gautham R. Shenoy wrote: > From: "Gautham R. Shenoy" > > The existing code doesn't handle the case when CPU which was in a > hardware-idle state (nap,sleep,winkle on POWER8 and various stop > states on POWER9) gets woken up due

Re: [PATCH 2/4] powerpc/64: Provide functions for accessing POWER9 partition table

a note to > > help improve the system] > > > > url: > > https://github.com/0day-ci/linux/commits/Paul-Mackerras/powerpc-64-Preparation-for-KVM-support-on-POWER9/20161121-133431 > > base: https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git >

Re: [PATCH 1/2] KVM: PPC: Fix sparse static warning.

On Mon, Oct 10, 2016 at 11:31:19AM +1100, Daniel Axtens wrote: > Squash a couple of sparse warnings by making things static. > > Build tested. > > Signed-off-by: Daniel Axtens Thanks, applied to kvm-ppc-next. Paul.

Re: [PATCH -next] KVM: PPC: Book3S HV: Use list_move_tail instead of list_del/list_add_tail

On Mon, Oct 17, 2016 at 03:15:50PM +, Wei Yongjun wrote: > From: Wei Yongjun > > Using list_move_tail() instead of list_del() + list_add_tail(). > > Signed-off-by: Wei Yongjun Thanks, applied to kvm-ppc-next. Paul.

Re: [PATCH 2/2] KVM: PPC: sparse: prototypes for functions called from assembler

On Mon, Oct 10, 2016 at 11:31:20AM +1100, Daniel Axtens wrote: > A bunch of KVM functions are only called from assembler. > Give them prototypes in asm-prototypes.h > This reduces sparse warnings. > > Signed-off-by: Daniel Axtens Thanks, applied to kvm-ppc-next. Paul.

[PATCH 4/4] powerpc/64: Define new ISA v3.00 logical PVR value and PCR register value

value into next patch] Signed-off-by: Suraj Jitindar Singh <sjitindarsi...@gmail.com> Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/include/asm/reg.h | 7 +++ 1 file changed, 7 insertions(+) diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/r

[PATCH 2/4] powerpc/64: Provide functions for accessing POWER9 partition table

, the call gets moved to near the end of radix__early_init_mmu(). It now gets called when running as a guest, whereas previously it would only be called if the kernel is running as the host. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/include/asm/mmu.h | 5 + arch/p

[PATCH 1/4] powerpc/64: Add some more SPRs and SPR bits for POWER9

These definitions will be needed by KVM. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/include/asm/reg.h | 5 + 1 file changed, 5 insertions(+) diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h index c491cfe..d2f868a 100644 --- a/arch/p

[PATCH 3/4] powerpc/powernv: Define real-mode versions of OPAL XICS accessors

This defines real-mode versions of opal_int_get_xirr(), opal_int_eoi() and opal_int_set_mfrr(), for use by KVM real-mode code. It also exports opal_int_set_mfrr() so that the modular part of KVM can use it to send IPIs. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/i

[PATCH 0/4] powerpc/64: Preparation for KVM support on POWER9

This patch series, based on the current powerpc next branch, adds various things we need in arch/powerpc in order to support KVM on POWER9. Michael, could you put these in a topic branch that I can pull? Paul. --- arch/powerpc/include/asm/mmu.h | 5

Re: [PATCH 02/13] powerpc/64: Provide functions for accessing POWER9 partition table

On Sat, Nov 19, 2016 at 12:05:21PM +0530, Aneesh Kumar K.V wrote: > Paul Mackerras <pau...@ozlabs.org> writes: > > > On Fri, Nov 18, 2016 at 07:57:30PM +0530, Aneesh Kumar K.V wrote: > >> Paul Mackerras <pau...@ozlabs.org> writes: > >> + > >&g

Re: [PATCH 05/13] KVM: PPC: Book3S HV: Adapt to new HPTE format on POWER9

On Sat, Nov 19, 2016 at 11:38:40AM +1100, Balbir Singh wrote: > > > On 18/11/16 18:28, Paul Mackerras wrote: > > This adapts the KVM-HV hashed page table (HPT) code to read and write > > HPT entries in the new format defined in Power ISA v3.00 on POWER9 > > machines.

Re: [PATCH 02/13] powerpc/64: Provide functions for accessing POWER9 partition table

On Sat, Nov 19, 2016 at 11:45:52AM +1100, Balbir Singh wrote: > > +#ifdef CONFIG_PPC_BOOK3S_64 > > +void mmu_partition_table_init(void) > > +{ > > + unsigned long patb_size = 1UL << PATB_SIZE_SHIFT; > > + > > + BUILD_BUG_ON_MSG((PATB_SIZE_SHIFT > 24), "Partition table size too > > large."); >

Re: [PATCH 09/13] KVM: PPC: Book3S HV: Adapt TLB invalidations to work on POWER9

On Sat, Nov 19, 2016 at 08:57:28AM +1100, Benjamin Herrenschmidt wrote: > On Fri, 2016-11-18 at 20:11 +0530, Aneesh Kumar K.V wrote: > > > +  * Work out how many sets the TLB has, for the use of > > > +  * the TLB invalidation loop in book3s_hv_rmhandlers.S. > > > +  */ > > > + if

Re: [PATCH 09/13] KVM: PPC: Book3S HV: Adapt TLB invalidations to work on POWER9

On Fri, Nov 18, 2016 at 08:11:34PM +0530, Aneesh Kumar K.V wrote: > > @@ -3287,6 +3290,17 @@ static int kvmppc_core_init_vm_hv(struct kvm *kvm) > > kvm->arch.lpcr = lpcr; > > > > /* > > +* Work out how many sets the TLB has, for the use of > > +* the TLB invalidation loop in

Re: [PATCH 10/13] KVM: PPC: Book3S HV: Use msgsnd for IPIs to other cores on POWER9

On Fri, Nov 18, 2016 at 08:17:25PM +0530, Aneesh Kumar K.V wrote: > Paul Mackerras <pau...@ozlabs.org> writes: > > > On POWER9, the msgsnd instruction is able to send interrupts to > > other cores, as well as other threads on the local core. Since > > msgsnd is gen

Re: [PATCH 02/13] powerpc/64: Provide functions for accessing POWER9 partition table

On Fri, Nov 18, 2016 at 07:57:30PM +0530, Aneesh Kumar K.V wrote: > Paul Mackerras <pau...@ozlabs.org> writes: > + > > + /* Global flush of TLBs and partition table caches for this lpid */ > > + asm volatile("ptesync"); > > + asm volatile(PPC_TLBIE_

Re: [PATCH 07/13] KVM: PPC: Book3S HV: Adjust host/guest context switch for POWER9

On Fri, Nov 18, 2016 at 08:05:47PM +0530, Aneesh Kumar K.V wrote: > Paul Mackerras <pau...@ozlabs.org> writes: > > > Some special-purpose registers that were present and accessible > > by guests on POWER8 no longer exist on POWER9, so this adds > > feature sectio

[PATCH 13/13] KVM: PPC: Book3S HV: Treat POWER9 CPU threads as independent subcores

on POWER9 as long as the host is running with HPT translation. Since userspace currently has no way to request radix tree translation for the guest, the guest has no choice but to use HPT translation. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/kvm/book3s_hv.

[PATCH 12/13] KVM: PPC: Book3S HV: Use stop instruction rather than nap on POWER9

ring guest execution with the stop instruction, and adds code to set PSSCR to a value which will allow an SMT mode switch while the thread is idle (given that the core as a whole won't be idle in these cases). Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/kvm/book3s_hv_r

[PATCH 11/13] KVM: PPC: Book3S HV: Use OPAL XICS emulation on POWER9

turns from kvmppc_read_one_intr(). Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/include/asm/kvm_ppc.h | 7 +++-- arch/powerpc/kvm/book3s_hv.c | 28 +++-- arch/powerpc/kvm/book3s_hv_builtin.c | 59 ++-- arch/powerpc/kvm/book3s_h

[PATCH 10/13] KVM: PPC: Book3S HV: Use msgsnd for IPIs to other cores on POWER9

On POWER9, the msgsnd instruction is able to send interrupts to other cores, as well as other threads on the local core. Since msgsnd is generally simpler and faster than sending an IPI via the XICS, we use msgsnd for all IPIs sent by KVM on POWER9. Signed-off-by: Paul Mackerras <

[PATCH 09/13] KVM: PPC: Book3S HV: Adapt TLB invalidations to work on POWER9

, we don't need to do the TLB flush on first entry to the guest on each processor. Therefore we don't set all bits in the tlb_need_flush bitmap on VM startup on POWER9. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/include/asm/kvm_host.h | 1 + arch/powerpc/kern

[PATCH 08/13] KVM: PPC: Book3S HV: Add new POWER9 guest-accessible SPRs

contains some fields which are guest-accessible and some which are only accessible in hypervisor mode. We only allow the guest-accessible fields to be read or set by userspace. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- Documentation/virtual/kvm/api.txt | 2 ++ arch/p

[PATCH 07/13] KVM: PPC: Book3S HV: Adjust host/guest context switch for POWER9

, but we had to context-switch them on POWER8 to avoid creating a covert channel. They are: SPMC1, SPMC2, MMCRS, CSIGR, TACR, TCSCR, and ACOP. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/kvm/book3s_hv_rmhandlers.S | 50 - 1 file chang

[PATCH 06/13] KVM: PPC: Book3S HV: Set partition table rather than SDR1 on POWER9

(logical partition ID register), not the SDR1 register. There is also no requirement now to transition via a reserved LPID value. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/kvm/book3s_hv.c| 36 +++-- arch/powerpc/kvm/book3s_hv_rmhand

[PATCH 05/13] KVM: PPC: Book3S HV: Adapt to new HPTE format on POWER9

) and ARPN (abbreviated real page number) fields. As far as possible, the conversion is done when reading or writing the HPT entries, and the rest of the code continues to use the old format. Signed-off-by: Paul Mackerras <pau...@ozlabs.org> --- arch/powerpc/kvm/book3s_64_mmu_hv.c

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