Tighten up time timing around the gpio reset functionality. Add a 200ns
delay before remuxing the pins back to ac97 to comply with the ac97 spec.
This delay ensures that sync and sdata_out are held low while reset
transitions to high.
Signed-off-by: Eric Millbrandt emillbra...@dekaresearch.com
On Fri, Sep 03, 2010 at 11:45:22AM -0400, Eric Millbrandt wrote:
Tighten up time timing around the gpio reset functionality. Add a 200ns
delay before remuxing the pins back to ac97 to comply with the ac97 spec.
This delay ensures that sync and sdata_out are held low while reset
transitions to
On Fri, 3 Sep 2010 at 12:02:09 Wolfram Sang wrote:
On Fri, Sep 03, 2010 at 11:45:22AM -0400, Eric Millbrandt wrote:
Tighten up time timing around the gpio reset functionality. Add a 200ns
delay before remuxing the pins back to ac97 to comply with the ac97
spec. This delay ensures that sync and
- udelay(2);
+ udelay(1);
/* Deassert reset */
setbits8(wkup_gpio-wkup_dvo, reset);
+ /* wait at least 200ns */
+ __delay(7);
ndelay(200)?
Is ndelay defined for powerpc? I was under the impression that it was
being redefined to
On Fri, 3 Sep 2010 at 12:22:24 Wolfram Sang wrote:
- udelay(2);
+ udelay(1);
/* Deassert reset */
setbits8(wkup_gpio-wkup_dvo, reset);
+ /* wait at least 200ns */
+ __delay(7);
ndelay(200)?
Is ndelay defined for powerpc? I was under the
Yes, but it is way more readable. Does the extra delay hurt? The value
of 7 looks a bit magic to me. Are you sure it will do for various
clock frequencies?
The reset is happening in the gpio spinlock, so I am trying to keep busy
waiting to a minimum. The magic value of 7 calculates
