Re: [PATCH 1/4] [v4][POWERPC] refactor dcr code

2008-05-06 Thread Josh Boyer
On Tue, 6 May 2008 10:34:36 -0700 "Stephen Neuendorffer" <[EMAIL PROTECTED]> wrote: > > I'll fix it. Great. Otherwise the patch looks pretty good in my review. I'll queue it up for 2.6.27. josh ___ Linuxppc-dev mailing list Linuxppc-dev@ozlabs.org h

RE: [PATCH 1/4] [v4][POWERPC] refactor dcr code

2008-05-06 Thread Stephen Neuendorffer
I'll fix it. > -Original Message- > From: Benjamin Herrenschmidt [mailto:[EMAIL PROTECTED] > Sent: Monday, May 05, 2008 9:02 PM > To: Stephen Rothwell > Cc: Stephen Neuendorffer; [EMAIL PROTECTED]; [EMAIL PROTECTED]; linuxppc- > [EMAIL PROTECTED] > Subject: Re

Re: [PATCH 1/4] [v4][POWERPC] refactor dcr code

2008-05-05 Thread Benjamin Herrenschmidt
On Tue, 2008-05-06 at 13:40 +1000, Stephen Rothwell wrote: > Since find_dcr_parent has done a of_node_get on its return value, you > leak a reference to dp here i.e. you need an of_node_put(dp) before > you return. He inherited that bug from other dcr.c functions I wrote, my fault. Stephen (N. n

Re: [PATCH 1/4] [v4][POWERPC] refactor dcr code

2008-05-05 Thread Stephen Rothwell
Hi Stephen, On Mon, 5 May 2008 10:56:38 -0700 Stephen Neuendorffer <[EMAIL PROTECTED]> wrote: > > +static struct device_node *find_dcr_parent(struct device_node *node) > +{ > + struct device_node *par, *tmp; > + const u32 *p; > + > + for (par = of_node_get(node); par;) { > +

Re: [PATCH 1/4] [v4][POWERPC] refactor dcr code

2008-05-05 Thread Benjamin Herrenschmidt
On Mon, 2008-05-05 at 10:56 -0700, Stephen Neuendorffer wrote: > Previously, dcr support was configured at compile time to either using > MMIO or native dcr instructions. Although this works for most > platforms, it fails on FPGA platforms: > > 1) Systems may include more than one dcr bus. > 2)

[PATCH 1/4] [v4][POWERPC] refactor dcr code

2008-05-05 Thread Stephen Neuendorffer
Previously, dcr support was configured at compile time to either using MMIO or native dcr instructions. Although this works for most platforms, it fails on FPGA platforms: 1) Systems may include more than one dcr bus. 2) Systems may be native dcr capable and still use memory mapped dcr interface.