On Aug 19, 2009, at 7:43 PM, Benjamin Herrenschmidt wrote:
On Wed, 2009-08-19 at 16:37 -0500, Kumar Gala wrote:
On Aug 19, 2009, at 2:25 AM, Benjamin Herrenschmidt wrote:
The whole thing only ever gets called if we had tlbsrx. so is there
any utility in making a part of conditional on
On Mon, 2009-08-24 at 11:12 -0500, Kumar Gala wrote:
Duh. Wasn't looking at the fall through.
But is there any reason to even have any of the 6 instructions in
the
'virt_page_table_tlb_miss_done' path if we don't have TLBSRX?
No, that's what I said in my initial email :-) You can
On Wed, 2009-08-19 at 00:08 -0500, Kumar Gala wrote:
Support for TLB reservation (or TLB Write Conditional) and Paired MAS
registers are optional for a processor implementation so we handle
them via MMU feature sections.
We currently only used paired MAS registers to access the full RPN +
On Aug 19, 2009, at 2:25 AM, Benjamin Herrenschmidt wrote:
On Wed, 2009-08-19 at 00:08 -0500, Kumar Gala wrote:
Support for TLB reservation (or TLB Write Conditional) and Paired MAS
registers are optional for a processor implementation so we handle
them via MMU feature sections.
We currently
On Wed, 2009-08-19 at 16:37 -0500, Kumar Gala wrote:
On Aug 19, 2009, at 2:25 AM, Benjamin Herrenschmidt wrote:
The whole thing only ever gets called if we had tlbsrx. so is there
any utility in making a part of conditional on tlbsrx?
I don't think so ... this is the second level TLB miss
Support for TLB reservation (or TLB Write Conditional) and Paired MAS
registers are optional for a processor implementation so we handle
them via MMU feature sections.
We currently only used paired MAS registers to access the full RPN + perm
bits that are kept in MAS7||MAS3. We assume that if an
