On Tue, 2008-05-20 at 15:53 -0700, David Miller wrote:
From: Scott Wood [EMAIL PROTECTED]
Date: Tue, 20 May 2008 17:43:58 -0500
David Miller wrote:
The __volatile__ in the asm construct disallows movement of the
inline asm relative to statements surrounding it.
The only reason
On Fri, 23 May 2008, Benjamin Herrenschmidt wrote:
On Tue, 2008-05-20 at 15:53 -0700, David Miller wrote:
From: Scott Wood [EMAIL PROTECTED]
Date: Tue, 20 May 2008 17:43:58 -0500
David Miller wrote:
The __volatile__ in the asm construct disallows movement of the
inline asm relative to
Trent Piepho [EMAIL PROTECTED] writes:
On Wed, 21 May 2008, Andreas Schwab wrote:
Trent Piepho [EMAIL PROTECTED] writes:
It's the _le versions that have a problem, since we can't get gcc to just
use
the register indexed mode. It seems like an obvious thing to have a
constraint for, but I
Depends on what you define as necessary. It's seem clear that I/O accessors
_no not_ need to be strictly ordered with respect to normal memory accesses,
by what's defined in memory-barriers.txt. So if by necessary you mean what
the Linux standard for I/O accessors requires (and what other
On Tue, 2008-05-20 at 15:55 -0700, Trent Piepho wrote:
here doesn't appear to be any barriers to use for coherent dma other than
mb() and wmb().
Correct me if I'm wrong, but I think the sync isn't actually _required_ (by
memory-barriers.txt's definitions), and it would be enough to use
On Wed, 21 May 2008, Benjamin Herrenschmidt wrote:
Depends on what you define as necessary. It's seem clear that I/O accessors
_no not_ need to be strictly ordered with respect to normal memory accesses,
by what's defined in memory-barriers.txt. So if by necessary you mean what
the Linux
On Wed, 21 May 2008, Andreas Schwab wrote:
Trent Piepho [EMAIL PROTECTED] writes:
On Wed, 21 May 2008, Andreas Schwab wrote:
Trent Piepho [EMAIL PROTECTED] writes:
It's the _le versions that have a problem, since we can't get gcc to just use
the register indexed mode. It seems like an
On Wed, 2008-05-21 at 12:44 -0700, Trent Piepho wrote:
Someone should update memory-barriers.txt, because it doesn't say
that, and
all I/O accessors for all the arches, because none of them are.
There have been long discussions about that. The end result was that
being too weakly ordered is
Benjamin Herrenschmidt wrote:
On Tue, 2008-05-20 at 13:40 -0700, Trent Piepho wrote:
There was some discussion on a Freescale list if the powerpc I/O accessors
should be strictly ordered w.r.t. normal memory. Currently they are not. It
does not appear as if any other architecture's I/O
Trent Piepho [EMAIL PROTECTED] writes:
For the LE versions, eventually they boil down to an asm that will look
something like this:
asm(sync; stwbrx %1,0,%2 : =m (*addr) : r (val), r (addr));
While not perfect, this appears to be the best one can do. The issue is
that the stwbrx
On Tue, 2008-05-20 at 16:38 -0500, Scott Wood wrote:
It looks like we rely on -fno-strict-aliasing to prevent reordering
ordinary memory accesses (such as to DMA descriptors) past the I/O
access. It won't prevent reordering of memory reads around an I/O
read,
though, which could be a
On Tue, 20 May 2008, Benjamin Herrenschmidt wrote:
On Tue, 2008-05-20 at 13:40 -0700, Trent Piepho wrote:
There was some discussion on a Freescale list if the powerpc I/O accessors
should be strictly ordered w.r.t. normal memory. Currently they are not. It
does not appear as if any other
On Wed, 21 May 2008, Andreas Schwab wrote:
Trent Piepho [EMAIL PROTECTED] writes:
For the LE versions, eventually they boil down to an asm that will look
something like this:
asm(sync; stwbrx %1,0,%2 : =m (*addr) : r (val), r (addr));
While not perfect, this appears to be the best one can do.
On Tue, 20 May 2008, Benjamin Herrenschmidt wrote:
On Tue, 2008-05-20 at 16:38 -0500, Scott Wood wrote:
It looks like we rely on -fno-strict-aliasing to prevent reordering
ordinary memory accesses (such as to DMA descriptors) past the I/O
access. It won't prevent reordering of memory reads
Alan Cox wrote:
It looks like we rely on -fno-strict-aliasing to prevent reordering
ordinary memory accesses (such as to DMA descriptors) past the I/O
DMA descriptors in main memory are dependant on cache behaviour anyway
and the dma_* operators should be the ones enforcing the needed
From: Scott Wood [EMAIL PROTECTED]
Date: Tue, 20 May 2008 17:35:56 -0500
Alan Cox wrote:
It looks like we rely on -fno-strict-aliasing to prevent reordering
ordinary memory accesses (such as to DMA descriptors) past the I/O
DMA descriptors in main memory are dependant on cache
David Miller wrote:
From: Scott Wood [EMAIL PROTECTED]
Date: Tue, 20 May 2008 17:35:56 -0500
Alan Cox wrote:
It looks like we rely on -fno-strict-aliasing to prevent reordering
ordinary memory accesses (such as to DMA descriptors) past the I/O
DMA descriptors in main memory are dependant on
Trent Piepho [EMAIL PROTECTED] writes:
It's the _le versions that have a problem, since we can't get gcc to just use
the register indexed mode. It seems like an obvious thing to have a
constraint for, but I guess there weren't enough instructions that only come
in 'x' versions to bother with
From: Scott Wood [EMAIL PROTECTED]
Date: Tue, 20 May 2008 17:43:58 -0500
David Miller wrote:
The __volatile__ in the asm construct disallows movement of the
inline asm relative to statements surrounding it.
The only reason barrier() in kernel.h needs a memory clobber is
because of a
It looks like we rely on -fno-strict-aliasing to prevent reordering
ordinary memory accesses (such as to DMA descriptors) past the I/O
DMA descriptors in main memory are dependant on cache behaviour anyway
and the dma_* operators should be the ones enforcing the needed behaviour.
Alan
On Tue, 20 May 2008, Scott Wood wrote:
Alan Cox wrote:
It looks like we rely on -fno-strict-aliasing to prevent reordering
ordinary memory accesses (such as to DMA descriptors) past the I/O
DMA descriptors in main memory are dependant on cache behaviour anyway
and the dma_* operators
On Wed, 21 May 2008, Andreas Schwab wrote:
Trent Piepho [EMAIL PROTECTED] writes:
It's the _le versions that have a problem, since we can't get gcc to just use
the register indexed mode. It seems like an obvious thing to have a
constraint for, but I guess there weren't enough instructions
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