-Original Message-
From: Wood Scott-B07421
Sent: Monday, August 06, 2012 11:16 PM
To: Jia Hongtao-B38951
Cc: Wood Scott-B07421; Kumar Gala; linuxppc-dev@lists.ozlabs.org; Li
Yang-R58472
Subject: Re: [PATCH V4 3/3] powerpc/fsl-pci: Unify pci/pcie
initialization code
On 08/05/2012
-Original Message-
From: Wood Scott-B07421
Sent: Monday, August 06, 2012 11:10 PM
To: Jia Hongtao-B38951
Cc: Wood Scott-B07421; linuxppc-dev@lists.ozlabs.org;
ga...@kernel.crashing.org; Li Yang-R58472
Subject: Re: [PATCH V5 3/3] powerpc/fsl-pci: Unify pci/pcie
initialization code
In sleep PM mode, the clocks of e500 core and unused IP blocks is
turned off. IP blocks which are allowed to wake up the processor
are still running.
Some Freescale chips like MPC8536 and P1022 has deep sleep PM mode
in addtion to the sleep PM mode.
While in deep sleep PM mode, additionally, the
The cpufreq driver of mpc85xx will disable/enable cpu hotplug temporarily.
Therefore, the related functions should be exported.
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
---
include/linux/cpu.h |4
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git
Some 85xx silicons like MPC8536 and P1022 have a JOG feature, which provides
a dynamic mechanism to lower or raise the CPU core clock at runtime.
This patch adds the support to change CPU frequency using the standard
cpufreq interface. The ratio CORE to CCB can be 1:1(except MPC8536), 3:2,
2:1,
Add APIs for setting wakeup source and lossless Ethernet in low power modes.
These APIs can be used by wake-on-packet feature.
Signed-off-by: Dave Liu dave...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Jin Qing b24...@freescale.com
Signed-off-by: Zhao Chenhui
Hi Ira,
I remember you said you always disable CONFIG_NET_DMA to make sure dma engine
won't be locked, actually if this options may affect some behavior of fsl-dma
in current kernel, it is possible to issue pending descriptors if there is any
network actions.
Set CONFIG_NET_DMA=y,
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
---
Replace this patch mpc85xx_defconfig: add IDE support for MPC85xxCDS.
arch/powerpc/configs/mpc85xx_defconfig |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/configs/mpc85xx_defconfig
-Original Message-
From: Kumar Gala [mailto:ga...@kernel.crashing.org]
Sent: Tuesday, July 31, 2012 9:37 PM
To: Jia Hongtao-B38951
Cc: linuxppc-dev@lists.ozlabs.org; Wood Scott-B07421; Li Yang-R58472
Subject: Re: [PATCH 5/6] powerpc/fsl-pci: Add pci inbound/outbound PM
support
On 08/07/2012 01:23 AM, Jia Hongtao-B38951 wrote:
-Original Message-
From: Wood Scott-B07421
Sent: Monday, August 06, 2012 11:16 PM
To: Jia Hongtao-B38951
Cc: Wood Scott-B07421; Kumar Gala; linuxppc-dev@lists.ozlabs.org; Li
Yang-R58472
Subject: Re: [PATCH V4 3/3] powerpc/fsl-pci:
On 08/06/2012 11:20 PM, Li Yang wrote:
On Mon, Aug 6, 2012 at 11:09 PM, Scott Wood scottw...@freescale.com wrote:
On 08/05/2012 10:07 PM, Jia Hongtao-B38951 wrote:
-Original Message-
From: Wood Scott-B07421
Sent: Saturday, August 04, 2012 12:28 AM
To: Jia Hongtao-B38951
Cc:
On 08/07/2012 03:09 AM, Jia Hongtao-B38951 wrote:
I am really not sure that all boards need primary bus. Could you give me
the link of discussion about primary that you mentioned?
https://lists.ozlabs.org/pipermail/linuxppc-dev/2012-June/098586.html
-Scott
On 08/07/2012 05:11 AM, Jia Hongtao-B38951 wrote:
-Original Message-
From: Kumar Gala [mailto:ga...@kernel.crashing.org]
Sent: Tuesday, July 31, 2012 9:37 PM
To: Jia Hongtao-B38951
Cc: linuxppc-dev@lists.ozlabs.org; Wood Scott-B07421; Li Yang-R58472
Subject: Re: [PATCH 5/6]
On Aug 7, 2012, at 10:34 AM, Scott Wood wrote:
On 08/07/2012 05:11 AM, Jia Hongtao-B38951 wrote:
-Original Message-
From: Kumar Gala [mailto:ga...@kernel.crashing.org]
Sent: Tuesday, July 31, 2012 9:37 PM
To: Jia Hongtao-B38951
Cc: linuxppc-dev@lists.ozlabs.org; Wood
On Aug 7, 2012, at 3:43 AM, Zhao Chenhui wrote:
The cpufreq driver of mpc85xx will disable/enable cpu hotplug temporarily.
Therefore, the related functions should be exported.
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
---
include/linux/cpu.h |4
1 files changed, 4
On 08/06/2012 11:22 AM, Sethi Varun-B16395 wrote:
-Original Message-
From: Kumar Gala [mailto:ga...@kernel.crashing.org]
Sent: Monday, August 06, 2012 9:23 PM
To: Sethi Varun-B16395
Cc: linuxppc-dev@lists.ozlabs.org; Hamciuc Bogdan-BHAMCIU1
Subject: Re: [PATCH 3/3 v4]
On 08/03/2012 02:32 PM, Sethi Varun-B16395 wrote:
-Original Message-
From: Kumar Gala [mailto:ga...@kernel.crashing.org]
Sent: Saturday, August 04, 2012 12:55 AM
To: Sethi Varun-B16395
Cc: linuxppc-dev@lists.ozlabs.org; Hamciuc Bogdan-BHAMCIU1
Subject: Re: [PATCH 3/3 v3]
This has two outcomes:
* we give the TTY layer a tty_port
* we do not find the info structure every time open is called on that
tty
Since we take a reference to a port in -install, we need also
-cleanup to drop that reference.
Signed-off-by: Jiri Slaby jsl...@suse.cz
Cc:
This has two outcomes:
* we give the TTY layer a tty_port
* we do not find the info structure every time open is called on that
tty
From now on, we only increase the reference count in -install (and
decrease in -cleanup).
Signed-off-by: Jiri Slaby jsl...@suse.cz
Cc:
On Tuesday 07 August 2012, Ian Molton wrote:
I think it documents some of the same thing,
Not really. It documents some godawful hack that recycled the platform
device -based driver and provided a DT binding for it, just for PPC.
I cant even find anything that implements code for whatever
When a 'gpios' property defines multiple GPIO pins, is there any kind of
expectation on the endian order of those pins? For example, take this:
gpios = gpio0 0 0
gpio0 1 0;
If I write a value of 2 to this GPIO pair, should I expect a value of 1
to be written to pin 0
These patches add support for IBM vTPM for PPC64. This new device driver
works on firmware that supports vTPM (firmware release 740 or higher).
Tested on Power7+ system with firmware level ZM770_001.
Applied to Kent Yoder patch to modularize event log located at:
This patch instantiate Stored Measurement Log (SML) and put the
log address and size in the device tree.
Signed-off-by: Ashley Lai ad...@us.ibm.com
---
arch/powerpc/kernel/prom_init.c | 64 +++
1 files changed, 64 insertions(+), 0 deletions(-)
diff --git
This patch retrieves the event log from the device tree and the
event log data will be displayed through securityfs.
Signed-off-by: Ashley Lai ad...@us.ibm.com
---
drivers/char/tpm/Makefile |8 -
drivers/char/tpm/tpm.h| 12 --
drivers/char/tpm/tpm_eventlog.c |
This patch adds a new device driver to support IBM virtual TPM
(vTPM) for PPC64. This driver provides TPM functionalities
by communicating with the vTPM adjunct through Hypervisor
calls (Hcalls) and Command/Response Queue (CRQ) commands.
Signed-off-by: Ashley Lai ad...@us.ibm.com
---
From 21e9d1775f0c6f37a39e5d682ff74693fa9a4004 Mon Sep 17 00:00:00 2001
From: Sukadev Bhattiprolu suka...@linux.vnet.ibm.com
Date: Tue, 7 Aug 2012 17:53:24 -0700
Subject: [PATCH] Use pmc_overflow to detect rolled back events.
For certain speculative events on Power7, 'perf stat' reports far
-Original Message-
From: Kumar Gala [mailto:ga...@kernel.crashing.org]
Sent: Wednesday, August 08, 2012 1:34 AM
To: Wood Scott-B07421
Cc: Jia Hongtao-B38951; linuxppc-dev@lists.ozlabs.org; Wood Scott-B07421;
Li Yang-R58472
Subject: Re: [PATCH 5/6] powerpc/fsl-pci: Add pci
powerpc: Use enhanced touch instructions in POWER7
copy_to_user/copy_from_user was applied twice. Remove one.
Signed-off-by: Anton Blanchard an...@samba.org
---
Index: b/arch/powerpc/lib/copyuser_power7.S
===
---
The enhanced prefetch hint patches corrupt the condition register
that was used to check if we are in interrupt. Fix this by using cr1.
Signed-off-by: Anton Blanchard an...@samba.org
---
Index: b/arch/powerpc/lib/copyuser_power7.S
-Original Message-
From: Wood Scott-B07421
Sent: Tuesday, August 07, 2012 11:20 PM
To: Jia Hongtao-B38951
Cc: Wood Scott-B07421; Kumar Gala; linuxppc-dev@lists.ozlabs.org; Li
Yang-R58472
Subject: Re: [PATCH V4 3/3] powerpc/fsl-pci: Unify pci/pcie
initialization code
On
All SOC device error interrupts are muxed and delivered to the core
as a single MPIC error interrupt. Currently all the device drivers
requiring access to device errors have to register for the MPIC error
interrupt as a shared interrupt.
With this patch we add interrupt demuxing capability in the
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