Fwd: running qemu for powerpc (32bits) architecture

-- Forwarded message -- From: Scott Wood Date: 2016-06-04 1:23 GMT+01:00 Subject: Re: running qemu for powerpc (32bits) architecture To: Marwa Hamza , linuxppc-dev@lists.ozlabs.org On Mon, 2016-05-30 at 10:04 +0100, Marwa Hamza wrote: >

Kernel 4.7: PAGE_GUARDED and _PAGE_NO_CACHE

All, I need an answer because I think Darren's guess is correct. It isn't a problem in the pci code. I replaced the file head_64.S that Darren mentioned with the one from the kernel 4.6 and it compiled but unfortunately it doesn't boot. We know "head_64.S" is one file for the early boot

Re: [RESEND PATCH v2 2/6] PCI: Set PCI_BUS_FLAGS_MSI_REMAP if MSI controller enables IRQ remapping

Hi, [auto build test ERROR on vfio/next] [also build test ERROR on v4.7-rc1 next-20160603] [cannot apply to pci/next] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url:

Re: [PATCH 7/7] thermal: qoriq: Add thermal management support

Hi, [auto build test ERROR on v4.7-rc1] [also build test ERROR on next-20160603] [cannot apply to robh/for-next soc-thermal/next] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url:

Re: [PATCH v5 08/11] powerpc/powernv: Add platform support for stop instruction

On Thu, 2016-06-02 at 07:38 -0500, Shreyas B. Prabhu wrote: > @@ -61,8 +72,13 @@ save_sprs_to_stack: > * Note all register i.e per-core, per-subcore or per-thread is saved > * here since any thread in the core might wake up first > */ > +BEGIN_FTR_SECTION > +   mfspr 

Re: [PATCH V2] powerpc/ptrace: Fix out of bounds array access warning

On Wed, May 11, 2016 at 10:51 AM, Aaro Koskinen wrote: > Hi, > > On Mon, Apr 25, 2016 at 09:19:17AM -0700, Khem Raj wrote: >> gcc-6 correctly warns about a out of bounds access >> >> arch/powerpc/kernel/ptrace.c:407:24: warning: index 32 denotes an offset >> greater than

Re: [RESEND PATCH v2 2/6] PCI: Set PCI_BUS_FLAGS_MSI_REMAP if MSI controller enables IRQ remapping

Hi, [auto build test ERROR on vfio/next] [also build test ERROR on v4.7-rc1 next-20160603] [cannot apply to pci/next] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url:

Re: [PATCH] powerpc/mm: use _raw variant of page table accessors

On Fri, 2016-06-03 at 15:34 +1000, Balbir Singh wrote: > > Can we just save the cpu_to_be64(_PAGE_PTE) as _BE64_PAGE_PTE constant > in big-endian (pgtable-be-types.h) and similar for other things. I know its > not the best option, but we don't really expect these bits to change often or >

Re: [v2] powerpc: spinlock: Fix spin_unlock_wait()

On Fri, 2016-03-06 at 03:49:48 UTC, Boqun Feng wrote: > There is an ordering issue with spin_unlock_wait() on powerpc, because > the spin_lock primitive is an ACQUIRE and an ACQUIRE is only ordering > the load part of the operation with memory operations following it. ... > diff --git

Re: [v2] powerpc: spinlock: Fix spin_unlock_wait()

On Mon, Jun 06, 2016 at 02:52:05PM +1000, Michael Ellerman wrote: > On Fri, 2016-03-06 at 03:49:48 UTC, Boqun Feng wrote: > > There is an ordering issue with spin_unlock_wait() on powerpc, because > > the spin_lock primitive is an ACQUIRE and an ACQUIRE is only ordering > > the load part of the

Kernel 4.7: PAGE_GUARDED and _PAGE_NO_CACHE

Thanks. I'll try it. - Christian On 06 June 2016 at 02:51 AM, Michael Ellerman wrote: On Sat, 2016-06-04 at 17:07 +0200, Christian Zigotzky wrote: Aneesh, Shall I bisect the kernel from the powerpc git? No just use linus' tree. Shall I start with the following commit?

Re: powerpc/nvram: Fix an incorrect partition merge

On 2016年06月03日 19:47, Michael Ellerman wrote: On Thu, 2015-10-12 at 07:30:02 UTC, xinhui wrote: From: Pan Xinhui When we merge two contiguous partitions whose signatures are marked NVRAM_SIG_FREE, We need update prev's length and checksum, then write it to

Re: [PATCH] powerpc/mm: use _raw variant of page table accessors

On 06/06/16 08:30, Benjamin Herrenschmidt wrote: > On Fri, 2016-06-03 at 15:34 +1000, Balbir Singh wrote: >> >> Can we just save the cpu_to_be64(_PAGE_PTE) as _BE64_PAGE_PTE constant >> in big-endian (pgtable-be-types.h) and similar for other things. I know its >> not the best option, but we

[PATCH v3] powerpc: Define and use PPC64_ELF_ABI_v2/v1

We're approaching 20 locations where we need to check for ELF ABI v2. That's fine, except the logic is a bit awkward, because we have to check that _CALL_ELF is defined and then what its value is. So check it once in asm/types.h and define PPC64_ELF_ABI_v2 when ELF ABI v2 is detected. We also

Re: [PATCH V3 8/9] cpufreq: Keep policy->freq_table sorted in ascending order

On 03-06-16, 16:48, Steve Muckle wrote: > On Fri, Jun 03, 2016 at 07:05:14PM +0530, Viresh Kumar wrote: > ... > > @@ -468,20 +469,15 @@ unsigned int acpi_cpufreq_fast_switch(struct > > cpufreq_policy *policy, > > struct acpi_cpufreq_data *data = policy->driver_data; > > struct

Re: [1/3] powerpc/mm/radix: Update LPCR only if it is powernv

On Tue, 2016-31-05 at 06:26:29 UTC, "Aneesh Kumar K.V" wrote: > LPCR cannot be updated when running in guest mode. > > Signed-off-by: Aneesh Kumar K.V Applied to powerpc fixes, thanks. https://git.kernel.org/powerpc/c/d6c886006c948141f24e84aceb cheers

Re: Kernel 4.7: PAGE_GUARDED and _PAGE_NO_CACHE

On Sat, 2016-06-04 at 20:16 +0530, Aneesh Kumar K.V wrote: > Christian Zigotzky writes: > > > Hi All, > > > > I compiled the latest git version of kernel 4.7 with all PowerPC > > commits. Maybe the latest commit powerpc-4.7-2 solved the boot issues. > > Our latest Nemo

Re: Kernel 4.7: PAGE_GUARDED and _PAGE_NO_CACHE

On Sat, 2016-06-04 at 17:07 +0200, Christian Zigotzky wrote: > Aneesh, > > Shall I bisect the kernel from the powerpc git? No just use linus' tree. > Shall I start with the following commit? > >

Re: Kernel 4.7: PAGE_GUARDED and _PAGE_NO_CACHE

On Sun, 2016-06-05 at 18:09 +0200, Christian Zigotzky wrote: > All, > > I need an answer because I think Darren's guess is correct. It isn't a > problem in the pci code. I replaced the file head_64.S that Darren > mentioned with the one from the kernel 4.6 and it compiled but > unfortunately

Re: Kernel 4.7: PAGE_GUARDED and _PAGE_NO_CACHE

On 6/5/2016 8:57 PM, Michael Ellerman wrote: On Sun, 2016-06-05 at 18:09 +0200, Christian Zigotzky wrote: All, I need an answer because I think Darren's guess is correct. It isn't a problem in the pci code. I replaced the file head_64.S that Darren mentioned with the one from the kernel 4.6

Re: Kernel 4.7: PAGE_GUARDED and _PAGE_NO_CACHE

On Sun, 2016-06-05 at 21:23 -0400, Julian Margetson wrote: > > > > > > drivers/gpu/drm/drm_vm.c: In function ‘drm_dma_prot’: > > > drivers/gpu/drm/drm_vm.c:83:6: error: invalid operands to binary | > > > (have ‘pgprot_t {aka struct }’ and ‘int’) > > > tmp |= _PAGE_NO_CACHE; >

Re: [2/3] powerpc/mm/hash: Fix the reference bit update when handling hash fault

On Tue, 2016-31-05 at 06:26:30 UTC, "Aneesh Kumar K.V" wrote: > When we converted the asm routines to C functions, we missed updating > HPTE_R_R based on _PAGE_ACCESSED. ASM code used to copy over the lower > bits from pte via. ... > > Signed-off-by: Benjamin Herrenschmidt

Re: [3/3] powerpc/mm/radix: Add missing tlb flush

On Tue, 2016-31-05 at 06:26:31 UTC, "Aneesh Kumar K.V" wrote: > This should not have any impact on hash, because hash does tlb > invalidate with every pte update and we don't implement > flush_tlb_* functions for hash. With radix we should make an explicit > call to flush tlb outside pte update. >

Re: powerpc/pseries: Add POWER8NVL support to ibm, client-architecture-support call

On Tue, 2016-31-05 at 05:51:17 UTC, Thomas Huth wrote: > If we do not provide the PVR for POWER8NVL, a guest on this > system currently ends up in PowerISA 2.06 compatibility mode on > KVM, since QEMU does not provide a generic PowerISA 2.07 mode yet. > So some new instructions from POWER8 (like

Re: powerpc/pseries: Fix PCI config address for DDW

On Wed, 2016-25-05 at 23:56:07 UTC, Gavin Shan wrote: > In commit <8445a87f7092> ("powerpc/iommu: Remove the dependency > on EEH struct in DDW mechanism"), the PE address was replaced > with the PCI config address in order to remove dependency on EEH. > According to PAPR spec, firmware (pHyp or