Re: [PATCH] ibmvnic: Fix unused variable warning

On 08/09/2017 04:16 AM, Michal Suchanek wrote: > Fixes: a248878d7a1d ("ibmvnic: Check for transport event on driver resume") > > Signed-off-by: Michal Suchanek > --- Reviewed-by: Tyrel Datwyler

[PATCH V11 0/3] powernv : Add support for OPAL-OCC command/response interface

In P9, OCC (On-Chip-Controller) supports shared memory based commad-response interface. Within the shared memory there is an OPAL command buffer and OCC response buffer that can be used to send inband commands to OCC. The following commands are supported: 1) Set system powercap 2) Set CPU-GPU

Re: [PATCH 02/10] powerpc/xive: guest exploitation of the XIVE interrupt controller

On Wed, Aug 09, 2017 at 10:48:48AM +0200, Cédric Le Goater wrote: > On 08/09/2017 05:53 AM, David Gibson wrote: > > On Tue, Aug 08, 2017 at 10:56:12AM +0200, Cédric Le Goater wrote: > >> This is the framework for using XIVE in a PowerVM guest. The support > >> is very similar to the native one in

Re: [PATCH 02/10] powerpc/xive: guest exploitation of the XIVE interrupt controller

On Thu, 2017-08-10 at 14:28 +1000, David Gibson wrote: > > Also, will POWER9 always have doorbells? In which case you could > reduce it to 3 options. The problem with doorbells on POWER9 guests is that they may have to trap and be emulated by the hypervisor, since the guest threads on P9 don't

[PATCH V11 3/3] powernv: Add support to clear sensor groups data

Adds support for clearing different sensor groups. OCC inband sensor groups like CSM, Profiler, Job Scheduler can be cleared using this driver. The min/max of all sensors belonging to these sensor groups will be cleared. Signed-off-by: Shilpasri G Bhat ---

[PATCH V11 1/3] powernv: powercap: Add support for powercap framework

Adds a generic powercap framework to change the system powercap inband through OPAL-OCC command/response interface. Signed-off-by: Shilpasri G Bhat --- .../ABI/testing/sysfs-firmware-opal-powercap | 31 +++ arch/powerpc/include/asm/opal-api.h

Re: [PATCH] powerpc: xive: ensure active irqd when setting affinity

Sukadev Bhattiprolu writes: > Michael Ellerman [m...@ellerman.id.au] wrote: >> Sukadev Bhattiprolu writes: >> > From fd0abf5c61b6041fdb75296e8580b86dc91d08d6 Mon Sep 17 00:00:00 2001 >> > From: Benjamin Herrenschmidt

Re: [PATCH 3/3] powerpc/mm: Mark __init memory no-execute when STRICT_KERNEL_RWX=y

Le 09/08/2017 à 04:29, Michael Ellerman a écrit : Christophe LEROY writes: Le 14/07/2017 à 08:51, Michael Ellerman a écrit : diff --git a/arch/powerpc/include/asm/book3s/64/pgtable.h b/arch/powerpc/include/asm/book3s/64/pgtable.h index c0737c86a362..3d562b210c65

Re: [PATCH 03/10] powerpc/xive: rename xive_poke_esb in xive_esb_read

On 08/09/2017 05:55 AM, David Gibson wrote: > On Tue, Aug 08, 2017 at 10:56:13AM +0200, Cédric Le Goater wrote: >> xive_poke_esb() is performing a load/read so it is better named as >> xive_esb_read(). > > Uh, patch seems to mismatch the comment here, calling it > xive_peek_esb() instead. euh

Re: [PATCH 0/3] Minor updates for PS3

Jens Axboe writes: > On 08/08/2017 04:16 AM, Michael Ellerman wrote: >> Geoff Levand writes: >> >>> Hi Michael, >>> >>> A few very minor updates for PS3. Please apply. >> >> Jens do you want to take the block ones, or should I just take the lot? > > Up

Re: [PATCH 10/10] powerpc/xive: fix the size of the cpumask used in xive_find_target_in_mask()

Cédric Le Goater writes: > When called from xive_irq_startup(), the size of the cpumask can be > larger than nr_cpu_ids. Most of time, its value is NR_CPUS (2048). Ugh, you're right. #define nr_cpumask_bits ((unsigned int)NR_CPUS) ... /** * cpumask_weight - Count

Re: [RFC PATCH v5 1/5] iommu: Add capabilities to a group

On Mon, Aug 07, 2017 at 05:25:44PM +1000, Alexey Kardashevskiy wrote: > This introduces capabilities to IOMMU groups. The first defined > capability is IOMMU_GROUP_CAP_ISOLATE_MSIX which tells the IOMMU > group users that a particular IOMMU group is capable of MSIX message > filtering; this is

Re: [RFC PATCH v5 5/5] vfio-pci: Allow to expose MSI-X table to userspace when safe

On Mon, Aug 07, 2017 at 05:25:48PM +1000, Alexey Kardashevskiy wrote: 1;4803;0c> Some devices have a MSIX BAR not aligned to the system page size > greater than 4K (like 64k for ppc64) which at the moment prevents > such MMIO pages from being mapped to the userspace for the sake of > the MSIX BAR

Re: [PATCH 08/10] powerpc/xive: take into account '/ibm,plat-res-int-priorities'

On 08/09/2017 06:02 AM, David Gibson wrote: > On Tue, Aug 08, 2017 at 10:56:18AM +0200, Cédric Le Goater wrote: >> '/ibm,plat-res-int-priorities' contains a list of priorities that the >> hypervisor has reserved for its own use. Scan these ranges to choose >> the lowest unused priority for the

Re: [PATCH 10/10] powerpc/xive: fix the size of the cpumask used in xive_find_target_in_mask()

On Wed, 2017-08-09 at 17:06 +1000, Michael Ellerman wrote: > /** >* cpumask_weight - Count of bits in *srcp >* @srcp: the cpumask to count bits (< nr_cpu_ids) in. >*/ > static inline unsigned int cpumask_weight(const struct cpumask *srcp) > { > return

Re: [PATCH] powerpc: xive: ensure active irqd when setting affinity

On Wed, 2017-08-09 at 16:15 +1000, Michael Ellerman wrote: > I'm not sure I'm convinced. We can't handle every possible case of the > higher level code calling us in situations we don't expect. > > For example irq_data could be NULL, but we trust the higher level code > not to do that to us. > >

Re: [PATCH 10/10] powerpc/xive: fix the size of the cpumask used in xive_find_target_in_mask()

On 08/09/2017 09:06 AM, Michael Ellerman wrote: > Cédric Le Goater writes: >> When called from xive_irq_startup(), the size of the cpumask can be >> larger than nr_cpu_ids. Most of time, its value is NR_CPUS (2048). > > Ugh, you're right. > > #define nr_cpumask_bits

Re: [PATCH] powerpc/mm: Invalidate partition table cache on host proc tbl base update

Suraj Jitindar Singh writes: > The host process table base is stored in the partition table by calling > the function native_register_process_table(). Currently this just sets > the entry in memory and is missing a proceeding cache invalidation > instruction. Any update

Re: [PATCH 02/10] powerpc/xive: guest exploitation of the XIVE interrupt controller

On 08/09/2017 05:53 AM, David Gibson wrote: > On Tue, Aug 08, 2017 at 10:56:12AM +0200, Cédric Le Goater wrote: >> This is the framework for using XIVE in a PowerVM guest. The support >> is very similar to the native one in a much simpler form. >> >> Instead of OPAL calls, a set of Hypervisors

Re: [PATCH 02/16] mm: Prepare for FAULT_FLAG_SPECULATIVE

On Tue, Aug 08, 2017 at 04:35:35PM +0200, Laurent Dufour wrote: > @@ -2295,7 +2302,11 @@ static int wp_page_copy(struct vm_fault *vmf) > /* >* Re-check the pte - we dropped the lock >*/ > - vmf->pte = pte_offset_map_lock(mm, vmf->pmd, vmf->address, >ptl); > + if

Re: [PATCH 05/16] mm: Protect VMA modifications using VMA sequence count

On Tue, Aug 08, 2017 at 04:35:38PM +0200, Laurent Dufour wrote: > The VMA sequence count has been introduced to allow fast detection of > VMA modification when running a page fault handler without holding > the mmap_sem. > > This patch provides protection agains the VMA modification done in : >

Re: [PATCH 02/16] mm: Prepare for FAULT_FLAG_SPECULATIVE

On 09/08/2017 12:08, Kirill A. Shutemov wrote: > On Tue, Aug 08, 2017 at 04:35:35PM +0200, Laurent Dufour wrote: >> @@ -2295,7 +2302,11 @@ static int wp_page_copy(struct vm_fault *vmf) >> /* >> * Re-check the pte - we dropped the lock >> */ >> -vmf->pte =

[PATCH] powerpc/configs: Re-enable HARD/SOFT lockup detectors

In commit 05a4a9527931 ("kernel/watchdog: split up config options"), CONFIG_LOCKUP_DETECTOR was split into two separate config options, CONFIG_HARDLOCKUP_DETECTOR and CONFIG_SOFTLOCKUP_DETECTOR. Our defconfigs still have CONFIG_LOCKUP_DETECTOR=y, but that is no longer user selectable, and we

[PATCH] ibmvnic: Fix unused variable warning

Fixes: a248878d7a1d ("ibmvnic: Check for transport event on driver resume") Signed-off-by: Michal Suchanek --- drivers/net/ethernet/ibm/ibmvnic.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/net/ethernet/ibm/ibmvnic.c b/drivers/net/ethernet/ibm/ibmvnic.c index

Re: [PATCH 05/16] mm: Protect VMA modifications using VMA sequence count

On 09/08/2017 12:12, Kirill A. Shutemov wrote: > On Tue, Aug 08, 2017 at 04:35:38PM +0200, Laurent Dufour wrote: >> The VMA sequence count has been introduced to allow fast detection of >> VMA modification when running a page fault handler without holding >> the mmap_sem. >> >> This patch provides

[PATCH 0/6] watchdog and NMI IPI locking improvements

It was noticed that the watchdog was causing hangs and lockups in some cases, hammering on the watchdog lock, so I've found a few other improvements and bugs. Thanks to Paulus for finding the problem and fixing the lock primitives (I fixed it a bit differently but the idea is his). Thanks, Nick

[PATCH 1/6] powerpc: NMI IPI improve lock primitive

When the NMI IPI lock is contended, spin at low SMT priority, using loads only, and with interrupts enabled (where possible). This improves behaviour under high contention (e.g., a system crash when a number of CPUs are trying to enter the debugger). Signed-off-by: Nicholas Piggin

[PATCH 2/6] powerpc/watchdog: Improve watchdog lock primitive

- Hard-disable interrupts before taking the lock, which prevents soft-NMI re-entrancy and therefore can prevent deadlocks. - Use raw_ variants of local_irq_disable to avoid irq debugging. - When the lock is contended, spin at low SMT priority, using loads only, and with interrupts enabled

[PATCH 3/6] powerpc/watchdog: Moderate touch_nmi_watchdog overhead

Some code can go into a tight loop calling touch_nmi_watchdog (e.g., stop_machine CPU hotplug code). This can cause contention on watchdog locks particularly if all CPUs with watchdog enabled are spinning in the loops. Avoid this storm of activity by running the watchdog timer callback from this

[PATCH 4/6] powerpc/watchdog: Fix final-check recovered case

When the watchdog decides to panic, it takes the lock and double checks everything (to avoid races with the CPU being unstuck or panic()ed by something else). The exit label was misplaced and would result in all-CPUs backtrace and watchdog panic even in the case that the condition was found to be

[PATCH 5/6] powerpc/watchdog: Fix marking of stuck CPUs

When the SMP detector finds other CPUs stuck, it iterates over them and marks them as stuck. This pulls them out of the pending mask and allows the detector to continue with remaining good CPUs (if nmi_watchdog=panic is not enabled). The code to dothat was buggy because when setting a CPU stuck,

[PATCH 6/6] powerpc/watchdog: add locking around init/exit functions

When CPUs start and stop the watchdog, they manipulate shared data that is normally protected by the lock. Other CPUs can be running concurrently at this time, so it's a good idea to use locking here to be on the safe side. Remove the barrier which is undocumented and didn't do anything.

[PATCH v7 7/9] mm: Add address parameter to arch_validate_prot()

A protection flag may not be valid across entire address space and hence arch_validate_prot() might need the address a protection bit is being set on to ensure it is a valid protection flag. For example, sparc processors support memory corruption detection (as part of ADI feature) flag on memory

Re: [PATCH] PCI: Convert to using %pOF instead of full_name

On Wed, Aug 2, 2017 at 5:39 PM, Bjorn Helgaas wrote: > On Tue, Jul 18, 2017 at 04:43:21PM -0500, Rob Herring wrote: >> Now that we have a custom printf format specifier, convert users of >> full_name to use %pOF instead. This is preparation to remove storing >> of the full

Re: [PATCH] soc: Convert to using %pOF instead of full_name

On Tue, Jul 18, 2017 at 4:43 PM, Rob Herring wrote: > Now that we have a custom printf format specifier, convert users of > full_name to use %pOF instead. This is preparation to remove storing > of the full path string for each node. > > Signed-off-by: Rob Herring

[PATCH v7 0/9] Application Data Integrity feature introduced by SPARC M7

SPARC M7 processor adds additional metadata for memory address space that can be used to secure access to regions of memory. This additional metadata is implemented as a 4-bit tag attached to each cacheline size block of memory. A task can set a tag on any number of such blocks. Access to such

Re: [PATCH] mtd: nand: Rename nand.h into rawnand.h

* Boris Brezillon [170804 08:30]: > We are planning to share more code between different NAND based > devices (SPI NAND, OneNAND and raw NANDs), but before doing that > we need to move the existing include/linux/mtd/nand.h file into >

Re: [RFC Part1 PATCH v3 02/17] x86/CPU/AMD: Add the Secure Encrypted Virtualization CPU feature

On 7/25/2017 10:33 AM, Borislav Petkov wrote: On Tue, Jul 25, 2017 at 10:29:40AM -0500, Tom Lendacky wrote: But early_identify_cpu() calls get_cpu_cap() which will check for cpuid leaf 0x8008 support and set x86_phys_bits. Right, but it can't be less than 32, can it? And if it is more

Re: [PATCH 05/16] mm: Protect VMA modifications using VMA sequence count

On Wed, Aug 09, 2017 at 12:43:33PM +0200, Laurent Dufour wrote: > On 09/08/2017 12:12, Kirill A. Shutemov wrote: > > On Tue, Aug 08, 2017 at 04:35:38PM +0200, Laurent Dufour wrote: > >> The VMA sequence count has been introduced to allow fast detection of > >> VMA modification when running a page

Re: [PATCH 08/10] powerpc/xive: take into account '/ibm,plat-res-int-priorities'

On Wed, Aug 09, 2017 at 09:14:49AM +0200, Cédric Le Goater wrote: > On 08/09/2017 06:02 AM, David Gibson wrote: > > On Tue, Aug 08, 2017 at 10:56:18AM +0200, Cédric Le Goater wrote: > >> '/ibm,plat-res-int-priorities' contains a list of priorities that the > >> hypervisor has reserved for its own

Re: [v6 1/2] raid6/altivec: Add vpermxor implementation for raid6 Q syndrome

On Wed, Aug 9, 2017 at 11:26 PM, Michael Ellerman wrote: > Matt Brown writes: > >> This patch uses the vpermxor instruction to optimise the raid6 Q syndrome. >> This instruction was made available with POWER8, ISA version 2.07. >> It allows for

Re: [PATCH] mtd: nand: Rename nand.h into rawnand.h

On Fri, Aug 04, 2017 at 05:29:10PM +0200, Boris Brezillon wrote: > We are planning to share more code between different NAND based > devices (SPI NAND, OneNAND and raw NANDs), but before doing that > we need to move the existing include/linux/mtd/nand.h file into > include/linux/mtd/rawnand.h so

[PATCH V11 2/3] powernv: Add support to set power-shifting-ratio

This patch adds support to set power-shifting-ratio which hints the firmware how to distribute/throttle power between different entities in a system (e.g CPU v/s GPU). This ratio is used by OCC for power capping algorithm. Signed-off-by: Shilpasri G Bhat ---

Re: [v2] powerpc/powernv/idle: Disable LOSE_FULL_CONTEXT states when stop-api fails

On Tue, 2017-08-08 at 08:43:15 UTC, "Gautham R. Shenoy" wrote: > From: "Gautham R. Shenoy" > > Currently, we use the opal call opal_slw_set_reg() to inform the > Sleep-Winkle Engine (SLW) to restore the contents of some of the > Hypervisor state on wakeup from deep idle

Re: [PATCH 03/10] powerpc/xive: rename xive_poke_esb in xive_esb_read

On Wed, Aug 09, 2017 at 09:12:29AM +0200, Cédric Le Goater wrote: > On 08/09/2017 05:55 AM, David Gibson wrote: > > On Tue, Aug 08, 2017 at 10:56:13AM +0200, Cédric Le Goater wrote: > >> xive_poke_esb() is performing a load/read so it is better named as > >> xive_esb_read(). > > > > Uh, patch

Re: [PATCH 13/16] perf: Add a speculative page fault sw events

Laurent Dufour writes: > Add new software events to count succeeded and failed speculative page > faults. > > Signed-off-by: Laurent Dufour > --- > include/uapi/linux/perf_event.h | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git

Re: [PATCH 3/3] powerpc/mm: Mark __init memory no-execute when STRICT_KERNEL_RWX=y

Christophe LEROY writes: ... > At least it is correct for the ones that use regular pages, and kernel > can also be started with nobats or noltlbs at command line, in which > case it is usefull to have the page tables correct. Yep OK. >> So yes we *should* always mark

Re: [PATCH] powerpc/64s: Add support for ASB_Notify on POWER9

Le 05/08/2017 à 06:28, Benjamin Herrenschmidt a écrit : On Fri, 2017-08-04 at 16:56 +0200, Christophe Lombard wrote: The POWER9 core supports a new feature: ASB_Notify which requires the support of the Special Purpose Register: TIDR. The ASB_Notify command, generated by the AFU, will attempt

Re: [PATCH 13/16] perf: Add a speculative page fault sw events

On 09/08/2017 15:18, Michael Ellerman wrote: > Laurent Dufour writes: > >> Add new software events to count succeeded and failed speculative page >> faults. >> >> Signed-off-by: Laurent Dufour >> --- >> include/uapi/linux/perf_event.h | 2

Re: [v6 1/2] raid6/altivec: Add vpermxor implementation for raid6 Q syndrome

Matt Brown writes: > This patch uses the vpermxor instruction to optimise the raid6 Q syndrome. > This instruction was made available with POWER8, ISA version 2.07. > It allows for both vperm and vxor instructions to be done in a single > instruction. This has been