This arranges for the lppaca structs for most cpus to be dynamically
allocated in the same manner as the paca structs. If we don't include
support for legacy iSeries, only the first lppaca is statically
allocated; the rest are dynamically allocated. If we include legacy
iSeries support, then we
Currently we have the lppaca structs as a simple array of NR_CPUS
entries, taking up space in the data section of the kernel image.
In future we would like to allocate them dynamically, so this
abstracts out the accesses to the array, making it easier to
change how we locate the lppaca for a given
Hi Paul,
Is there any specific person(s) whom we whom we should direct this mail
to ? We have not received any response from CGROUP developers on this.
Kindly let me know whom to contact for this. I am adding few more people
i know :-)
Regards--
Subrata
On Mon, 2010-08-09 at 09:12 -0700, Paul
As early setup calls down to slb_initialize(), we must have kstack
initialised before checking should we add a bolted SLB entry for our kstack?
Failing to do so means stack access requires an SLB miss exception to refill
an entry dynamically, if the stack isn't accessible via SLB(0) (kernel text
On Fri, Aug 13, 2010 at 8:55 AM, Subrata Modak
subr...@linux.vnet.ibm.com wrote:
Hi Paul,
Is there any specific person(s) whom we whom we should direct this mail
to ? We have not received any response from CGROUP developers on this.
Kindly let me know whom to contact for this. I am adding few
Adding CONTROL GROUP Maintainers/Mailing list..
Regards--
Subrata
On Mon, 2010-08-09 at 09:12 -0700, Paul E. McKenney wrote:
On Mon, Aug 02, 2010 at 02:22:12PM +0530, Subrata Modak wrote:
Hi,
The following suspicious rcu_dereference_check() usage is detected
during 2.6.35-stable boot
On Tue, Jun 15, 2010 at 01:11:30PM -0600, Grant Likely wrote:
On Tue, Jun 15, 2010 at 10:09 AM, Richard Cochran
+static DEFINE_SPINLOCK(clocks_lock); /* protects 'clocks' */
Doesn't appear that clocks is manipulated at atomic context. Mutex instead?
...
If the spinlock is changed to a
On Wed, Aug 11, 2010 at 10:15 PM, Anton Vorontsov cbouatmai...@gmail.comwrote:
Hi,
On Wed, Aug 11, 2010 at 06:57:16PM +0530, Ravi Gupta wrote:
I am new to device driver development. I am trying to access the GPIO of
MPC837xERDB eval board. I have upgraded its kernel to linux-2.6.28.9 and
Looking at the device tree for this board, it appears U-Boot remaps the
IMMR registers to 0xe000. They are no longer accessible at
0xff40.
I would recommend studying arch/powerpc/boot/dts/mpc8377_rdb.dts in the
Linux source code. That describes the device layout on your board after
Hi,
On Fri, Aug 13, 2010 at 03:29:11PM +0530, Ravi Gupta wrote:
[...]
Thanks for the reply.
I had added the entries for gpio pin 9 for both controllers(I was not sure
with controller's pin is connected to LED, but now I know it is pin no. 233
i.e 224+9) in the mpc8377_rdb.dts file. Below is a
Makes RapidIO devices appear in /sys/devices/rapidio directory instead of top
of /sys/devices directory.
Signed-off-by: Alexandre Bounine alexandre.boun...@idt.com
Reviewed-by: Thomas Moll thomas.m...@sysgo.com
Cc: Matt Porter mpor...@kernel.crashing.org
Cc: Li Yang le...@freescale.com
Cc: Kumar
This set of RapidIO patches adds support for new IDT Gen2 sRIO switch
devices - CPS-1848 and CPS-1616.
Adding these sRIO switches required to implement standard error recovery
mechanism defined by the RapidIO specification.
___
Linuxppc-dev mailing list
- Rearranged RIO port-write interrupt handling to perform message buffering
as soon as possible.
- Modified to disable port-write controller when clearing Transaction Error (TE)
bit.
Signed-off-by: Alexandre Bounine alexandre.boun...@idt.com
Reviewed-by: Thomas Moll thomas.m...@sysgo.com
Cc: Matt
A switch ingress port number has to be saved for software assisted error
recovery from the error-stopped state. Saving this information also allows
to remove several register reads from the RIO enumeration process.
Signed-off-by: Alexandre Bounine alexandre.boun...@idt.com
Reviewed-by: Thomas
Create back and forward links between RIO devices. These links are intended for
use by error management and hot-plug extensions.
Signed-off-by: Alexandre Bounine alexandre.boun...@idt.com
Reviewed-by: Thomas Moll thomas.m...@sysgo.com
Cc: Matt Porter mpor...@kernel.crashing.org
Cc: Li Yang
The default error-stopped state handler provides recovery mechanism as defined
by RIO specification.
Signed-off-by: Alexandre Bounine alexandre.boun...@idt.com
Reviewed-by: Thomas Moll thomas.m...@sysgo.com
Cc: Matt Porter mpor...@kernel.crashing.org
Cc: Li Yang le...@freescale.com
Cc: Kumar Gala
Add callback that allows to create/remove switch-specific sysfs attributes.
Signed-off-by: Alexandre Bounine alexandre.boun...@idt.com
Reviewed-by: Thomas Moll thomas.m...@sysgo.com
Cc: Matt Porter mpor...@kernel.crashing.org
Cc: Li Yang le...@freescale.com
Cc: Kumar Gala
Add check if PW message source device is accessible and change PW message
handler to recover if PW message source device is not available anymore (power
down or link disconnect).
To avoid possible loss of notification, the PW message handler scans the route
back from the source device to identify
Add explicit device access check before performing device enumeration.
This gives a chance to clear possible link error conditions by issuing safe
maintenance read request(s).
Signed-off-by: Alexandre Bounine alexandre.boun...@idt.com
Reviewed-by: Thomas Moll thomas.m...@sysgo.com
Cc: Matt Porter
Add the RIO switch driver and definitions for IDT CPS-1848 and CPS-1616 Gen2
devices.
Signed-off-by: Alexandre Bounine alexandre.boun...@idt.com
Reviewed-by: Thomas Moll thomas.m...@sysgo.com
Cc: Matt Porter mpor...@kernel.crashing.org
Cc: Li Yang le...@freescale.com
Cc: Kumar Gala
I have an odd problem when using the 460ex rev b processors. Previously,
I'd used the rev A without any issues on the same pcbs. This happens on
multiple units now. Basically, while running the system will just
randomly kernel panic. We have seen this probably 4 or 5 times on a
over the
On Fri, 2010-08-13 at 15:36 -0500, Ayman El-Khashab wrote:
The exact details (though I don't think they are too useful are as follows.
The one interesting item if I read it correctly, is that the CPU was
trying to get instructions from c002 address. However, this board only
has 512MB
On Fri, Aug 13, 2010 at 3:34 AM, Richard Cochran
richardcoch...@gmail.com wrote:
On Tue, Jun 15, 2010 at 01:11:30PM -0600, Grant Likely wrote:
On Tue, Jun 15, 2010 at 10:09 AM, Richard Cochran
+static DEFINE_SPINLOCK(clocks_lock); /* protects 'clocks' */
Doesn't appear that clocks is
This patch enables support for Xilinx Virtex 4 FX singe-float FPU.
Changelog v2-v3:
-Fixed whitespaces for SAVE_FPR/REST_FPR.
-Changed description of MSR_AP bit.
-Removed the stub for APU unavailable exception.
Changelog v1-v2:
-Added MSR_AP bit definition
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