Hi Ben,
You're alright! I hadn't thought to use le32_to_cpu.
Do you want I make a new patch?
Cedric
Le 12/06/2011 00:45, Benjamin Herrenschmidt a écrit :
On Fri, 2011-06-10 at 15:56 +0200, Cédric Cano wrote:
Hi,
Marvell SAS driver doesn't work on powerpc architecture due to big
endian swap.
On Tue, 2011-06-14 at 08:42 +0200, Cédric Cano wrote:
Hi Ben,
You're alright! I hadn't thought to use le32_to_cpu.
Do you want I make a new patch?
Well, I'm not the maintainer of the subsystem or of the driver, so I'm
not going to be the one accepting/merging it :-)
I'm just reviewing the
Hi,
On Sun, May 29, 2011 at 4:53 PM, Tabi Timur-B04825 b04...@freescale.com wrote:
On Fri, May 27, 2011 at 8:25 AM, Thomas De Schampheleire
patrickdepinguin+linux...@gmail.com wrote:
Although I realize that what I need to achieve is unconventional, what
is the correct way of mapping a
Hi,
have someone tried to support RELOCATABLE kernel on ppc44x?
Thanks,
Michal
--
Michal Simek, Ing. (M.Eng)
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/
Microblaze U-BOOT custodian
On Tue, Jun 14, 2011 at 02:04:45PM +0200, Michal Simek wrote:
Hi,
have someone tried to support RELOCATABLE kernel on ppc44x?
Suzuki will be working on this eventually as part of getting kexec/kdump
working for 44x. I've CC'd him.
josh
___
On Tue, 14 Jun 2011, Benjamin Herrenschmidt wrote:
On Mon, 2011-06-13 at 14:00 -0700, Hugh Dickins wrote:
On Mon, Jun 13, 2011 at 1:34 PM, Pekka Enberg penb...@kernel.org wrote:
On Mon, Jun 13, 2011 at 10:29 PM, Christoph Lameter c...@linux.com
wrote:
On Mon, 13 Jun 2011, Pekka Enberg
Various kernel asm modifies SRR0/SRR1 just before executing
a rfi. If such code crosses a page boundary you risk a TLB miss
which will clobber SRR0/SRR1. Avoid this by always pinning
kernel instruction TLB space.
Signed-off-by: Joakim Tjernlund joakim.tjernl...@transmode.se
---
This is an assembler version to fixup DAR not being set
by dcbX, icbi instructions. There are two versions, one
uses selfmodifing code, the other uses a
jump table but is much bigger(default).
Signed-off-by: Joakim Tjernlund joakim.tjernl...@transmode.se
---
arch/ppc/kernel/head_8xx.S | 149
dcbz, dcbf, dcbi, dcbst and icbi do not set DAR when they
cause a DTLB Error. Dectect this by tagging DAR with 0x00f0
at every exception exit that modifies DAR.
This also fixes MachineCheck to pass DAR and DSISR as well.
Signed-off-by: Joakim Tjernlund joakim.tjernl...@transmode.se
---
Update the TLB asm to make proper use of _PAGE_DIRTY and _PAGE_ACCESSED.
Get rid of _PAGE_HWWRITE too.
Pros:
- PRESENT is copied to ACCESSED, fixing accounting
- DIRTY is mapped to 0x100, the changed bit, and is set directly
when a page has been made dirty.
- Proper RO/RW mapping of user
only DTLB Miss did set this bit, DTLB Error needs too otherwise
the setting is lost when the page becomes dirty.
Signed-off-by: Joakim Tjernlund joakim.tjernl...@transmode.se
---
arch/ppc/kernel/head_8xx.S | 12 +---
1 files changed, 9 insertions(+), 3 deletions(-)
diff --git
Only update pte w.r.t ACCESSED if it isn't already set
Wrap ACCESSED with #ifndef NO_SWAP for too ease optimization.
Signed-off-by: Joakim Tjernlund joakim.tjernl...@transmode.se
---
arch/ppc/kernel/head_8xx.S | 11 +--
1 files changed, 9 insertions(+), 2 deletions(-)
diff --git
8xx sometimes need to load a invalid/non-present TLBs in
it DTLB asm handler.
These must be invalidated separately as 8xx MMU don't.
Signed-off-by: Joakim Tjernlund joakim.tjernl...@transmode.se
---
arch/ppc/kernel/head_8xx.S | 12 ++--
1 files changed, 10 insertions(+), 2 deletions(-)
branch to common code in DTLB Miss instead.
Signed-off-by: Joakim Tjernlund joakim.tjernl...@transmode.se
---
arch/ppc/kernel/head_8xx.S | 23 ++-
1 files changed, 2 insertions(+), 21 deletions(-)
diff --git a/arch/ppc/kernel/head_8xx.S b/arch/ppc/kernel/head_8xx.S
index
This is a backport from 2.6 which I did to overcome 8xx CPU
bugs. 8xx does not update the DAR register when taking a TLB
error caused by dcbX and icbi insns which makes it very
tricky to use these insns. Also the dcbst wrongly sets the
the store bit when faulting into DTLB error.
A few more bugs
Don't check for kernel space if no modules.
Signed-off-by: Joakim Tjernlund joakim.tjernl...@transmode.se
---
arch/ppc/kernel/head_8xx.S |5 +
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/arch/ppc/kernel/head_8xx.S b/arch/ppc/kernel/head_8xx.S
index a4290b5..7f9e647
Use the PTE #defines where possible instead of
hardcoded constants.
Signed-off-by: Joakim Tjernlund joakim.tjernl...@transmode.se
---
arch/ppc/kernel/head_8xx.S | 12 ++--
1 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/ppc/kernel/head_8xx.S
8xx has not had WRITETHRU due to lack of bits in the pte.
After the recent rewrite of the 8xx TLB code, there are
two bits left. Use one of them to WRITETHRU.
Signed-off-by: Joakim Tjernlund joakim.tjernl...@transmode.se
---
arch/ppc/kernel/head_8xx.S |8
include/asm-ppc/pgtable.h
The wrong register was loaded into MD_RPN.
Signed-off-by: Joakim Tjernlund joakim.tjernl...@transmode.se
---
arch/ppc/kernel/head_8xx.S |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/ppc/kernel/head_8xx.S b/arch/ppc/kernel/head_8xx.S
index b3aff21..9d8a1b5
Now that 8xx can fixup dcbX instructions, start using them
where possible like every other PowerPc arch do.
Signed-off-by: Joakim Tjernlund joakim.tjernl...@transmode.se
---
arch/ppc/kernel/misc.S | 18 --
arch/ppc/lib/string.S | 17 -
2 files changed, 0
DTLB Error needs to adjust the HW PTE bits as DTLB Miss
does.
Signed-off-by: Joakim Tjernlund joakim.tjernl...@transmode.se
---
arch/ppc/kernel/head_8xx.S |7 ++-
1 files changed, 6 insertions(+), 1 deletions(-)
diff --git a/arch/ppc/kernel/head_8xx.S b/arch/ppc/kernel/head_8xx.S
index
Signed-off-by: Joakim Tjernlund joakim.tjernl...@transmode.se
---
arch/ppc/kernel/head_8xx.S | 84 +++
1 files changed, 22 insertions(+), 62 deletions(-)
diff --git a/arch/ppc/kernel/head_8xx.S b/arch/ppc/kernel/head_8xx.S
index f9a30f3..ba05a57 100644
Hi Joakim.
On Jun 14, 2011, at 6:54 AM, Joakim Tjernlund wrote:
Various kernel asm modifies SRR0/SRR1 just before executing
a rfi. .
I'm going to argue we can easily visually inspect for this
since the code is static with just a couple of RFIs in these
exception handlers.
Some 8xx
Hi Joakim.
On Jun 14, 2011, at 6:54 AM, Joakim Tjernlund wrote:
I know 2.4 is in strict maintenance mode and 8xx is obsolete
but as it is still in use I wanted 8xx to age with grace.
Thanks for your continued support. I have recently become
involved in some 8xx development again, and have
Provide devmem_is_allowed() routine to restrict access to kernel
memory from userspace.
Set CONFIG_STRICT_DEVMEM config option to switch on checking.
Signed-off-by: Steve Best sfb...@us.ibm.com
diff --git a/arch/powerpc/Kconfig.debug b/arch/powerpc/Kconfig.debug
index
Hi Steve,
On Tue, 2011-06-14 at 12:58 -0400, Steve Best wrote:
diff --git a/arch/powerpc/Kconfig.debug b/arch/powerpc/Kconfig.debug
index e72dcf6..e1aab6b 100644
--- a/arch/powerpc/Kconfig.debug
+++ b/arch/powerpc/Kconfig.debug
@@ -283,4 +283,15 @@ config PPC_EARLY_DEBUG_CPM_ADDR
Dan Malek ppc6...@digitaldans.com wrote on 2011/06/14 18:06:45:
Hi Joakim.
On Jun 14, 2011, at 6:54 AM, Joakim Tjernlund wrote:
Various kernel asm modifies SRR0/SRR1 just before executing
a rfi. .
I'm going to argue we can easily visually inspect for this
since the code is static
Dan Malek digitald...@digitaldans.com wrote on 2011/06/14 18:11:51:
Hi Joakim.
On Jun 14, 2011, at 6:54 AM, Joakim Tjernlund wrote:
I know 2.4 is in strict maintenance mode and 8xx is obsolete
but as it is still in use I wanted 8xx to age with grace.
Thanks for your continued support.
Hi Joakim.
On Jun 14, 2011, at 11:00 AM, Joakim Tjernlund wrote:
I don't have a mpc850, do you?
I have to say I do :-)
Probably but that is another matter. You could continue with that
if you like but I am stopping here ATM.
Oh, come on... I've been thinking about this for years,
On Tue, 2011-06-14 at 12:30 -0500, Nathan Lynch wrote:
Hi Steve,
On Tue, 2011-06-14 at 12:58 -0400, Steve Best wrote:
diff --git a/arch/powerpc/Kconfig.debug b/arch/powerpc/Kconfig.debug
index e72dcf6..e1aab6b 100644
--- a/arch/powerpc/Kconfig.debug
+++ b/arch/powerpc/Kconfig.debug
Dan Malek ppc6...@digitaldans.com wrote on 2011/06/14 20:11:18:
Hi Joakim.
On Jun 14, 2011, at 11:00 AM, Joakim Tjernlund wrote:
I don't have a mpc850, do you?
I have to say I do :-)
Good, you get to beat the crap out of it then :)
Probably but that is another matter. You could
Hi,
Sorry for the noise ... But if anyone knows what a Cube power button
gasket is made of please share! Is it conductive?
Again, sorry for the noise. But I figured there might be some cube
owners out here.
Thanks!
kevin
___
Linuxppc-dev mailing list
On Tue, 14 Jun 2011 14:17:01 -0400
Steve Best sfb...@us.ibm.com wrote:
On Tue, 2011-06-14 at 12:30 -0500, Nathan Lynch wrote:
Hi Steve,
On Tue, 2011-06-14 at 12:58 -0400, Steve Best wrote:
+/*
+ * devmem_is_allowed() checks to see if /dev/mem access to a certain
address
+ *
CONFIG_PPC_EPAPR_HV_BYTECHAN adds support for the Freescale hypervisor
byte channel tty driver.
CONFIG_VIRT_DRIVERS and CONFIG_FSL_HV_MANAGER add support for the Freescale
hypervisor management driver.
Signed-off-by: Timur Tabi ti...@freescale.com
---
The PC parallel port Kconfig as acquired one of those messy terms to
describe it's architecture dependencies:
depends on (!SPARC64 || PCI) !SPARC32 !M32R !FRV \
(!M68K || ISA) !MN10300 !AVR32 !BLACKFIN
This isn't just ugly - it also almost certainly describes the
Hi Joakim,
On Tue, Jun 14, 2011 at 03:54:45PM +0200, Joakim Tjernlund wrote:
This is a backport from 2.6 which I did to overcome 8xx CPU
bugs. 8xx does not update the DAR register when taking a TLB
error caused by dcbX and icbi insns which makes it very
tricky to use these insns. Also the
Thomas De Schampheleire wrote:
* However, if you jump to an address in that page, you'll have to make
sure that the entire code that executes is mapped (make map_size large
enough).
Well, that seems obvious.
* When that range spanned multiple pages, I faced the issue of only
one page being
Timur Tabi wrote:
Hmmm I find that surprising. Memory allocated via ioremap() is supposed
to
be available in interrupt handlers, where TLB mappings can't be created
on-the-fly. I'm not sure that your observation is correct.
Ok, it turns out I'm wrong. As long as the page is in the
On Tue, 14 Jun 2011 10:56:31 +0200
Thomas De Schampheleire patrickdepinguin+linux...@gmail.com wrote:
* Therefore, to make sure that the mapping I intended with __ioremap()
is actually reflected in the TLB tables, I added dummy reads of each
page in the TLB, prior to jumping to the boot code,
On Tuesday 14 June 2011 21:08:50 Ralf Baechle wrote:
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 9adc278..2968751f 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -21,6 +21,7 @@ config ARM
select HAVE_KERNEL_LZO
select HAVE_KERNEL_LZMA
select
On Tue, Jun 14, 2011 at 21:08, Ralf Baechle r...@linux-mips.org wrote:
The PC parallel port Kconfig as acquired one of those messy terms to
describe it's architecture dependencies:
depends on (!SPARC64 || PCI) !SPARC32 !M32R !FRV \
(!M68K || ISA) !MN10300 !AVR32
On 06/14/2011 12:08 PM, Ralf Baechle wrote:
The PC parallel port Kconfig as acquired one of those messy terms to
describe it's architecture dependencies:
depends on (!SPARC64 || PCI) !SPARC32 !M32R !FRV \
(!M68K || ISA) !MN10300 !AVR32 !BLACKFIN
This isn't
On Tuesday 14 June 2011 22:25:46 H. Peter Anvin wrote:
On 06/14/2011 12:08 PM, Ralf Baechle wrote:
The PC parallel port Kconfig as acquired one of those messy terms to
describe it's architecture dependencies:
depends on (!SPARC64 || PCI) !SPARC32 !M32R !FRV \
diff --git a/arch/ia64/Kconfig b/arch/ia64/Kconfig
index 38280ef..849805a 100644
--- a/arch/ia64/Kconfig
+++ b/arch/ia64/Kconfig
@@ -23,6 +23,7 @@ config IA64
select HAVE_ARCH_TRACEHOOK
select HAVE_DMA_API_DEBUG
select HAVE_GENERIC_HARDIRQS
+ select HAVE_PC_PARPORT
The Freescale hypervisor does not allow guests to write to the timebase
registers (virtualizing the timebase register was deemed too complicated),
so don't try to synchronize the timebase registers when we're running
under the hypervisor.
This typically happens when kexec support is enabled.
On Tue, 14 Jun 2011 18:04:33 -0500
Timur Tabi ti...@freescale.com wrote:
The Freescale hypervisor does not allow guests to write to the timebase
registers (virtualizing the timebase register was deemed too complicated),
so don't try to synchronize the timebase registers when we're running
Scott Wood wrote:
FWIW, it's not supported under KVM either -- though we don't support an SMP
guest under KVM yet, and KVM silently ignores it rather than logs errors as
the FSL HV does.
Does KVM set the root compatible to fsl,P4080DS-hv?
--
Timur Tabi
Linux kernel developer at Freescale
On Tue, Jun 14, 2011 at 01:25:46PM -0700, H. Peter Anvin wrote:
On 06/14/2011 12:08 PM, Ralf Baechle wrote:
The PC parallel port Kconfig as acquired one of those messy terms to
describe it's architecture dependencies:
depends on (!SPARC64 || PCI) !SPARC32 !M32R !FRV \
On Tue, 14 Jun 2011 18:15:26 -0500
Timur Tabi ti...@freescale.com wrote:
Scott Wood wrote:
FWIW, it's not supported under KVM either -- though we don't support an SMP
guest under KVM yet, and KVM silently ignores it rather than logs errors as
the FSL HV does.
Does KVM set the root
On Tue, 2011-06-14 at 20:08 +0100, Ralf Baechle wrote:
The PC parallel port Kconfig as acquired one of those messy terms to
describe it's architecture dependencies:
depends on (!SPARC64 || PCI) !SPARC32 !M32R !FRV \
(!M68K || ISA) !MN10300 !AVR32 !BLACKFIN
On Tue, 2011-06-14 at 18:25 -0500, Scott Wood wrote:
On Tue, 14 Jun 2011 18:15:26 -0500
Timur Tabi ti...@freescale.com wrote:
Scott Wood wrote:
FWIW, it's not supported under KVM either -- though we don't support an
SMP
guest under KVM yet, and KVM silently ignores it rather than
Benjamin Herrenschmidt wrote:
We might want to generically have a CPU feature bit indicating we are
running in guest vs. HV mode. I know Paulus is planning to introduce one
so you may want to sync with him.
Are you talking about CPU_FTR_HVMODE_206?
--
Timur Tabi
Linux kernel developer at
On Wed, 2011-06-15 at 02:10 +, Tabi Timur-B04825 wrote:
Benjamin Herrenschmidt wrote:
We might want to generically have a CPU feature bit indicating we are
running in guest vs. HV mode. I know Paulus is planning to introduce one
so you may want to sync with him.
Are you talking about
On 06/14/2011 03:34 PM, Ralf Baechle wrote:
There is no point in offering to build something that couldn't possibly be
used. It just makes the kernel harder to configure and inflates the test
matrix for no good reason.
I see... that's why a bunch of devices that only exist on ARM and MIPS
On 06/14/2011 02:33 PM, Arnd Bergmann wrote:
Why on earth restrict it like that? It's just a device driver, like
more or less any other device driver...
I'd say any other classic ISA/PC driver, including floppy, gameport or
serial-8250. One problem with these is that we never fully worked
On 06/14/2011 03:08 PM, Luck, Tony wrote:
diff --git a/arch/ia64/Kconfig b/arch/ia64/Kconfig
index 38280ef..849805a 100644
--- a/arch/ia64/Kconfig
+++ b/arch/ia64/Kconfig
@@ -23,6 +23,7 @@ config IA64
select HAVE_ARCH_TRACEHOOK
select HAVE_DMA_API_DEBUG
select
On Wed, Jun 15, 2011 at 12:18:36AM -0400, H. Peter Anvin wrote:
On 06/14/2011 03:34 PM, Ralf Baechle wrote:
There is no point in offering to build something that couldn't possibly be
used. It just makes the kernel harder to configure and inflates the test
matrix for no good reason.
On 06/14/2011 09:40 PM, Guenter Roeck wrote:
On Wed, Jun 15, 2011 at 12:18:36AM -0400, H. Peter Anvin wrote:
On 06/14/2011 03:34 PM, Ralf Baechle wrote:
There is no point in offering to build something that couldn't possibly be
used. It just makes the kernel harder to configure and inflates
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