On Fri, 2013-04-19 at 10:10 +0800, Li Zhong wrote:
On Thu, 2013-04-18 at 11:46 +1000, Michael Ellerman wrote:
On Wed, May 30, 2012 at 05:31:58PM +0800, Li Zhong wrote:
I'm not sure whether it makes sense to add this dependency to avoid
CONFI_NUMA !CONFIG_SMP.
I want to do this
2013.04.18. 15:09 keltezéssel, Jason Cooper írta:
On Thu, Apr 18, 2013 at 01:59:10PM +0100, Andrew Murray wrote:
On Wed, Apr 17, 2013 at 04:42:48PM +0100, Linus Walleij wrote:
On Tue, Apr 16, 2013 at 12:18 PM, Andrew Murray andrew.mur...@arm.com
wrote:
This patch converts the
On the most boards of Freescale platform, they use the PCI-Express
Intel(R) PRO/1000 gigabit ethernet card to work. So enable the
corresponding driver for it.
Signed-off-by: Chunhe Lan chunhe@freescale.com
---
arch/powerpc/configs/mpc85xx_smp_defconfig |1 +
1 files changed, 1
The EOI handler of MSI/MSI-X interrupts for P8 (PHB3) need additional
steps to handle the P/Q bits in IVE before EOIing the corresponding
interrupt. The patch changes the EOI handler to cover that.
Signed-off-by: Gavin Shan sha...@linux.vnet.ibm.com
---
arch/powerpc/platforms/powernv/pci-ioda.c
The patch intends to initialize PHB3 during system boot stage. The
flag PNV_PHB_MODEL_PHB3 is introduced to differentiate IODA2
compatible PHB3 from other types of PHBs.
Signed-off-by: Benjamin Herrenschmidt b...@kernel.crashing.org
---
arch/powerpc/platforms/powernv/pci-ioda.c | 62
The PHB3, which is compatible with IODA2, have lots of tables (RTT/
PETLV/PEST/IVT/RBA) in system memory and have corresponding BARs to
trace the system memory address. The patch configures the addresses
of variable tables explicitly through OPAL API.
Signed-off-by: Gavin Shan
These cache operations support Freescale SoCs based on BOOK3E.
Move L1 cache operations to fsl_booke_cache.S in order to maintain
easily. And, add cache operations for backside L2 cache and platform cache.
The backside L2 cache appears on e500mc and e5500 core. The platform cache
supported by
Some Freescale SoCs like MPC8536 and P1022 has the deep sleep mode
in addtion to the sleep mode.
In sleep PM mode, the clocks of e500 core and unused IP blocks is
turned off. IP blocks which are allowed to wake up the processor
are still running.
While in deep sleep PM mode, additionally, the
From: chenhui zhao chenhui.z...@freescale.com
Add APIs for setting wakeup source and lossless Ethernet in low power modes.
These APIs can be used by wake-on-packet feature.
Change-Id: I1803dcd4571af1eac49b43d99c578e7f99e2c278
Signed-off-by: Dave Liu dave...@freescale.com
Signed-off-by: Li Yang
The Power Management device tree stub indicated that the platform
supports Power Management feature.
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
---
arch/powerpc/boot/dts/fsl/mpc8536si-post.dtsi | 14 ++-
arch/powerpc/boot/dts/fsl/mpc8544si-post.dtsi |2 +
From: Li Yang le...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
---
.../devicetree/bindings/powerpc/fsl/pmc.txt| 59 +++
1 files changed, 34 insertions(+), 25 deletions(-)
diff --git
From: chenhui zhao chenhui.z...@freescale.com
Some 85xx silicons like MPC8536 and P1022 have a JOG feature, which provides
a dynamic mechanism to lower or raise the CPU core clock at runtime.
This patch adds the support to change CPU frequency using the standard
cpufreq interface. The ratio CORE
From: Chen-Hui Zhao chenhui.z...@freescale.com
Add support to disable and re-enable individual cores at runtime.
This supports e500mc/e5500 core based SoCs.
To prevent the register access race, only read/write RCPM registers
in platform_cpu_die() on the boot cpu instead of accessing by
The SoCs which have a RCPM (Run Control/Power Management) module
support power management feature. This patch implements sleep feature.
In sleep mode, the clocks of cores and unused IP blocks will be
turned off. The IP blocks which are allowed to wake up the system
are still running.
From: Chen-Hui Zhao chenhui.z...@freescale.com
* The paca[cpu].cpu_start is used as a signal to indicate if the cpu
should start. So it should be cleard in .cpu_die().
* The limit memory routine only needs to be ran once at boot time
by the boot cpu. Prevent other cpus running it again.
*
From: Chen-Hui Zhao chenhui.z...@freescale.com
In the case of SMP, during the time base sync period, all time bases of
online cores must stop, then start simultaneously.
There is a RCPM (Run Control/Power Management) module in CoreNet based SoCs.
Define a struct ccsr_rcpm to describe the
From: Chen-Hui Zhao chenhui.z...@freescale.com
Add struct ccsr_rcpm_v2 to descibe the v2 RCPM register map on some SoCs,
such as T4240, etc.
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Andy Fleming aflem...@freescale.com
---
From: Chen-Hui Zhao chenhui.z...@freescale.com
The L1 Data Cache of e6500 contains no modified data, no flush
is required.
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Andy Fleming aflem...@freescale.com
---
From: Chen-Hui Zhao chenhui.z...@freescale.com
* Only if two threads of one core are offline, the core can
enter PH20 state.
* Clear PH20 bits before core reset, or core will not restart.
* Introduced a variable l2cache_type in the struce cpu_spec to
indentify the type of L2 cache.
From: Chen-Hui Zhao chenhui.z...@freescale.com
RCPM unit controls the power managment of T4/B4 chips. Software can
access RCPM registers to put specific thread/core in PH10/PH15/PH20/PH30
state or put the device in LPM10/LPM20/LPM40 mode.
The RCPM unit supports several wake up sources through
From: Chen-Hui Zhao chenhui.z...@freescale.com
For e6500, two threads in one core share one time base. Just need
to do time base sync on first thread of one core, and skip it on
the other thread.
Signed-off-by: Zhao Chenhui chenhui.z...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
setup_pci_atmu() only has one parameter and remove the extra one, or
build will fail due to un-match.
Signed-off-by: Roy Zang tie-fei.z...@freescale.com
---
arch/powerpc/sysdev/fsl_pci.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/sysdev/fsl_pci.c
On 04/20/2013 02:55 AM, Roy Zang wrote:
setup_pci_atmu() only has one parameter and remove the extra one, or
build will fail due to un-match.
Signed-off-by: Roy Zang tie-fei.z...@freescale.com
---
based on Kumar's next branch.
Roy
___
Linuxppc-dev
Add new return code to rtas_flash to indicate firmware entitlement
expiry. This will be used by the update_flash script to return
appropriate message to the user.
Signed-off-by: Ananth N Mavinakayanahalli ana...@in.ibm.com
Signed-off-by: Vasant Hegde hegdevas...@linux.vnet.ibm.com
---
Memory allocated to flash_block_list in rtas_flash_write
is not freed during module exit. We hit below call trace
if we unload rtas_flash module after loading new firmware
image and before rebooting the system.
Feb 6 08:42:10 eagle3 kernel: kmem_cache_destroy rtas_flash_cache: Slab cache
still
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