On Mon, 1 Aug 2016 11:39:18 +0530
Madhavan Srinivasan wrote:
> On Monday 01 August 2016 10:59 AM, Nicholas Piggin wrote:
> > On Mon, 1 Aug 2016 00:36:27 +0530
> > Madhavan Srinivasan wrote:
> > And that would disable both handlers that test with IRQ_DISABLE_LEVEL_LINUX
> > and IRQ_DISABLE_LEVE
From: Alastair D'Silva
This patch fixes the following warning:
arch/powerpc/platforms/pseries/hotplug-memory.c:323:29: error:
'lmb_to_memblock' defined but not used [-Werror=unused-function]
static struct memory_block *lmb_to_memblock(struct of_drconf_cell *lmb)
^~
On Monday 01 August 2016 10:59 AM, Nicholas Piggin wrote:
On Mon, 1 Aug 2016 00:36:27 +0530
Madhavan Srinivasan wrote:
/*
* flags for paca->soft_enabled
*/
#define IRQ_DISABLE_LEVEL_NONE0
#define IRQ_DISABLE_LEVEL_LINUX 1
+#define IRQ_DISABLE_LEVEL_
On Monday 01 August 2016 10:51 AM, Nicholas Piggin wrote:
On Mon, 1 Aug 2016 00:36:26 +0530
Madhavan Srinivasan wrote:
Make it explicit the interrupt masking level supported
by a gievn interrupt handler. Patch correspondingly
extends the MASKABLE_* macros with an addition's parameter.
"mask
On Mon, 1 Aug 2016 00:36:27 +0530
Madhavan Srinivasan wrote:
> /*
> * flags for paca->soft_enabled
> */
> #define IRQ_DISABLE_LEVEL_NONE 0
> #define IRQ_DISABLE_LEVEL_LINUX 1
> +#define IRQ_DISABLE_LEVEL_PMU2
> +
> +#define MASK_IRQ_LEVEL
On Mon, 1 Aug 2016 00:36:26 +0530
Madhavan Srinivasan wrote:
> Make it explicit the interrupt masking level supported
> by a gievn interrupt handler. Patch correspondingly
> extends the MASKABLE_* macros with an addition's parameter.
> "mask_lvl" parameter is passed to SOFTEN_TEST macro to decid
On Thu, 28 Jul 2016 16:07:18 -0700
Andrey Smirnov wrote:
> Convert fsl_rstcr_restart into a function to be registered with
> register_reset_handler().
>
> Signed-off-by: Andrey Smirnov
> ---
>
> Changes since v1:
>
> - fsl_rstcr_restart is registered as a reset handler in
> se
On Thu, 28 Jul 2016 16:07:17 -0700
Andrey Smirnov wrote:
> Call out to all restart handlers that were added via
> register_restart_handler() API when restarting the machine.
>
> Signed-off-by: Andrey Smirnov
> ---
>
> No changes compared to v1
>
> arch/powerpc/kernel/setup-common.c | 4
On Thu, 28 Jul 2016 16:07:16 -0700
Andrey Smirnov wrote:
> Factor out a small bit of common code in machine_restart(),
> machine_power_off() and machine_halt().
>
> Signed-off-by: Andrey Smirnov
> ---
>
> No changes compared to v1.
>
> arch/powerpc/kernel/setup-common.c | 23 ++--
The codes of qe_ic init from a variety of platforms are redundant,
merge them to a common function and put it to irqchip/irq-qeic.c
For non-p1021_mds mpc85xx_mds boards, use "qe_ic_init(np, 0,
qe_ic_cascade_low_mpic, qe_ic_cascade_high_mpic);" instead of
"qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic
qeic_of_init just get device_node of qeic from dtb and call qe_ic_init,
pass the device_node to qe_ic_init.
So merge qeic_of_init into qe_ic_init to get the qeic node in
qe_ic_init.
Signed-off-by: Zhao Qiang
---
Changes for v2:
- modify subject and commit msg
- return 0 and add pu
move the driver from drivers/soc/fsl/qe to drivers/irqchip,
merge qe_ic.h and qe_ic.c into irq-qeic.c.
Signed-off-by: Zhao Qiang
---
Changes for v2:
- modify the subject and commit msg
Changes for v3:
- merge .h file to .c, rename it with irq-qeic.c
Changes for v4:
- modif
Signed-off-by: Madhavan Srinivasan
---
arch/powerpc/perf/power9-events-list.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/perf/power9-events-list.h
b/arch/powerpc/perf/power9-events-list.h
index cda6fcb809ca..6447dc1c3d89 100644
--- a/arch/powerpc/perf/
Local atomic operations are fast and highly reentrant per CPU counters.
Used for percpu variable updates. Local atomic operations only guarantee
variable modification atomicity wrt the CPU which owns the data and
these needs to be executed in a preemption safe way.
Here is the design of this patch
Code to replay the Performance Monitoring Interrupts(PMI).
In the masked_interrupt handler, for PMIs we reset the MSR[EE]
and return. This is due the fact that PMIs are level triggered.
In the __check_irq_replay(), we enabled the MSR[EE] which will
fire the interrupt for us.
Patch also adds a new
To support masking of the PMI interrupts, couple of new interrupt handler
macros are added MASKABLE_EXCEPTION_PSERIES_OOL and
MASKABLE_RELON_EXCEPTION_PSERIES_OOL. These are needed to include the
SOFTEN_TEST and implement the support at both host and guest kernel.
Couple of new irq #defs "PACA_IRQ
Make it explicit the interrupt masking level supported
by a gievn interrupt handler. Patch correspondingly
extends the MASKABLE_* macros with an addition's parameter.
"mask_lvl" parameter is passed to SOFTEN_TEST macro to decide
on masking the interrupt.
Signed-off-by: Madhavan Srinivasan
---
ar
To support addition of "mask_level" to MASKABLE_* macros,
factor out the EXCPETION_PROLOG_1 macro.
Signed-off-by: Madhavan Srinivasan
---
arch/powerpc/include/asm/exception-64s.h | 30 ++
1 file changed, 26 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/incl
Currently we use both EXCEPTION_PROLOG_1 amd __EXCEPTION_PROLOG_1
in the MASKABLE_* macros. As a cleanup, this patch makes MASKABLE_*
to use only __EXCEPTION_PROLOG_1. There is no logic change.
Signed-off-by: Madhavan Srinivasan
---
arch/powerpc/include/asm/exception-64s.h | 4 ++--
1 file chang
"paca->soft_enabled" is used as a flag to mask some of interrupts.
Currently supported flags values and their details:
soft_enabledMSR[EE]
0 0 Disabled (PMI and HMI not masked)
1 1 Enabled
"paca->soft_enabled" is initialized to 1 to make the interripts
Signed-off-by: Madhavan Srinivasan
---
arch/powerpc/include/asm/kvm_ppc.h | 2 +-
arch/powerpc/kernel/irq.c | 2 +-
arch/powerpc/kernel/setup_64.c | 4 ++--
arch/powerpc/kernel/time.c | 4 ++--
4 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/includ
Replace the hardcoded values used when updating
paca->soft_enabled with IRQ_DISABLE_LEVEL_* #def.
No logic change.
Signed-off-by: Madhavan Srinivasan
---
arch/powerpc/include/asm/exception-64s.h | 2 +-
arch/powerpc/include/asm/hw_irq.h| 15 ---
arch/powerpc/include/asm/irqf
Move set_soft_enabled() from powerpc/kernel/irq.c to
asm/hw_irq.c. this way updation of paca->soft_enabled
can be forced wherever possible.
Signed-off-by: Madhavan Srinivasan
---
arch/powerpc/include/asm/hw_irq.h | 6 ++
arch/powerpc/kernel/irq.c | 6 --
2 files changed, 6 insert
Two #defs IRQ_DISABLE_LEVEL_NONE and
IRQ_DISABLE_LEVEL_LINUX are added to be used
when updating paca->soft_enabled.
Signed-off-by: Madhavan Srinivasan
---
arch/powerpc/include/asm/hw_irq.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/powerpc/include/asm/hw_irq.h
b/arch/powerp
Local atomic operations are fast and highly reentrant per CPU counters.
Used for percpu variable updates. Local atomic operations only guarantee
variable modification atomicity wrt the CPU which owns the data and
these needs to be executed in a preemption safe way.
Here is the design of the patchs
IS_ERR_VALUE() assumes that parameter is an unsigned long.
It can not be used to check if 'unsigned int' is passed insted.
Which tends to reflect an error.
In 64bit architectures sizeof (int) == 4 && sizeof (long) == 8.
IS_ERR_VALUE(x) is ((x) >= (unsigned long)-4095).
IS_ERR_VALUE() of 'unsigned
All assignments to components of priv should only
occur after the check if prif is NULL.
Signed-off-by: Heinrich Schuchardt
---
drivers/net/wan/fsl_ucc_hdlc.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/net/wan/fsl_ucc_hdlc.c b/drivers/net/wan/fsl_ucc_hdlc.c
ind
Here you are:
i2c-0i2c Radeon i2c bit bus 0x90 I2C adapter
i2c-1i2c Radeon i2c bit bus 0x91 I2C adapter
i2c-2i2c Radeon i2c bit bus 0x92 I2C adapter
i2c-3i2c Radeon i2c bit bus 0x93 I2C adapter
Hi Linus,
Please pull powerpc updates for 4.8:
The following changes since commit 5edb56491d4812c42175980759da53388e5d86f5:
Linux 4.7-rc3
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git
tags/powerpc-4.8-1
for you to fetch changes up
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