Re: [PATCH v2] powerpc/mm: Only read faulting instruction when necessary in do_page_fault()

On Fri, 28 Apr 2017 08:13:01 +0200 (CEST) Christophe Leroy wrote: > Commit a7a9dcd882a67 ("powerpc: Avoid taking a data miss on every > userspace instruction miss") has shown that limiting the read of > faulting instruction to likely cases improves performance. > > This

Re: powerpc/mm/hash: Fix off-by-one in comment about kernel contexts ids

On Fri, 2017-04-28 at 12:05:23 UTC, Michael Ellerman wrote: > Michal Suchánek noticed a comment in book3s/64/mmu-hash.h about the context > ids > we use for the kernel was inconsistent with the code and other comments in the > same file. > > It should read 1-4 not 1-5. > > While we're touching

Re: [kernel] powerpc/powernv: Fix iommu table size calculation hook for small tables

On Thu, 2017-04-13 at 07:05:27 UTC, Alexey Kardashevskiy wrote: > When the userspace requests a small TCE table (which takes less than > the system page size) and more than 1 TCE level, the existing code > returns a single page size which is a bug as each additional TCE level > requires at least

Re: [kernel, v2] powerpc/powernv: Check kzalloc() return value in pnv_pci_table_alloc

On Mon, 2017-03-27 at 08:27:37 UTC, Alexey Kardashevskiy wrote: > pnv_pci_table_alloc() ignores possible failure from kzalloc_node(), > this adds a check. There are 2 callers of pnv_pci_table_alloc(), > one already checks for tbl!=NULL, this adds WARN_ON() to the other path > which only happens

Re: [guest,kernel] powerpc/pseries: Enable VFIO

On Fri, 2017-03-24 at 06:37:21 UTC, Alexey Kardashevskiy wrote: > This enables VFIO on pseries host in order to allow VFIO in nested guest > under PR KVM or DPDK in a HV guest. This adds support of > the VFIO_SPAPR_TCE_IOMMU type. > > This adds exchange() callback to allow TCE updates by the

Re: [kernel, v11, 04/10] powerpc/vfio_spapr_tce: Add reference counting to iommu_table

On Wed, 2017-03-22 at 04:21:50 UTC, Alexey Kardashevskiy wrote: > So far iommu_table obejcts were only used in virtual mode and had > a single owner. We are going to change this by implementing in-kernel > acceleration of DMA mapping requests. The proposed acceleration > will handle requests in

Re: [kernel, v11, 03/10] powerpc/iommu/vfio_spapr_tce: Cleanup iommu_table disposal

On Wed, 2017-03-22 at 04:21:49 UTC, Alexey Kardashevskiy wrote: > At the moment iommu_table can be disposed by either calling > iommu_table_free() directly or it_ops::free(); the only implementation > of free() is in IODA2 - pnv_ioda2_table_free() - and it calls > iommu_table_free() anyway. > >

Re: [kernel, v11, 02/10] powerpc/powernv/iommu: Add real mode version of iommu_table_ops::exchange()

On Wed, 2017-03-22 at 04:21:48 UTC, Alexey Kardashevskiy wrote: > In real mode, TCE tables are invalidated using special > cache-inhibited store instructions which are not available in > virtual mode > > This defines and implements exchange_rm() callback. This does not > define

Re: [kernel, v11, 01/10] powerpc/mmu: Add real mode support for IOMMU preregistered memory

On Wed, 2017-03-22 at 04:21:47 UTC, Alexey Kardashevskiy wrote: > This makes mm_iommu_lookup() able to work in realmode by replacing > list_for_each_entry_rcu() (which can do debug stuff which can fail in > real mode) with list_for_each_entry_lockless(). > > This adds realmode version of

Re: [1/2] powerpc/pasemi: do not process external or decrementer interrupts from sreset

On Mon, 2017-03-20 at 06:31:48 UTC, Nicholas Piggin wrote: > PA Semi will wake from low power state at the system reset interrupt, > with the event encoded in SRR1, rather than waking at the interrupt > vector that corresponds to that event. > > The system reset handler for this platform decodes

Re: [01/10] powerpc/64s: add exception macro that does not enable RI

On Mon, 2016-12-19 at 18:30:02 UTC, Nicholas Piggin wrote: > Subsequent patches will add more non-RI variant exceptions, so > create a macro for it rather than open-code it. > > This does not change generated instructions. > > Signed-off-by: Nicholas Piggin Series applied to

Re: [2/4] powerpc: add arch/powerpc/tools directory

On Sat, 2016-11-26 at 03:26:10 UTC, Nicholas Piggin wrote: > Move a couple of existing scripts under there. Remove scripts directory: > a script is a tool, a tool is not a script. > > Signed-off-by: Nick Piggin Applied to powerpc next, thanks.

Re: [1/4] powerpc: use the new post-link pass to check relocations

On Sat, 2016-11-26 at 03:26:09 UTC, Nicholas Piggin wrote: > Currently powerpc has to introduce a dependency on its default > build target zImage in order to run a relocation check pass > over the linked vmlinux. This is deficient because the check > is not run if the plain vmlinux target is

Re: [PATCH net] bnx2x: Align RX buffers

From: Scott Wood Date: Fri, 28 Apr 2017 19:17:41 -0500 > The bnx2x driver is not providing proper alignment on the receive buffers it > passes to build_skb(), causing skb_shared_info to be misaligned. > skb_shared_info contains an atomic, and while PPC normally supports >

Re: [PATCH v4] cxl: mask slice error interrupts after first occurrence

On 01/05/17 10:53, Alastair D'Silva wrote: From: Alastair D'Silva In some situations, a faulty AFU slice may create an interrupt storm of slice errors, rendering the machine unusable. Since these interrupts are informational only, present the interrupt once, then mask it

Re: [PATCH v2] powerpc/xmon: Wait for secondaries before IPI'ing on system reset

On Sun, 30 Apr 2017 22:27:58 +1000 Anton Blanchard wrote: > Hi Nick, > > > An externally triggered system reset (e.g., via QEMU nmi command, or > > pseries reset button) can cause system reset interrupts on all CPUs. > > In case this causes xmon to be entered, it is undesirable

[PATCH v4] cxl: mask slice error interrupts after first occurrence

From: Alastair D'Silva In some situations, a faulty AFU slice may create an interrupt storm of slice errors, rendering the machine unusable. Since these interrupts are informational only, present the interrupt once, then mask it off to prevent it from being retriggered

[PATCH] TLB flush concerns with POWER9/radix for init and machine checks

Hi, I've had a few concerns with the TLB flushing for POWER9 as implemented for cpu_setup/cpu_restore and machine check exception flushes. - tlbiel is undefined if R does not match the current radix mode. The TLB clearing in cpu_setup should match hash mode, but in machine check and

Re: [PATCH v2] powerpc/xmon: Wait for secondaries before IPI'ing on system reset

Hi Nick, > An externally triggered system reset (e.g., via QEMU nmi command, or > pseries reset button) can cause system reset interrupts on all CPUs. > In case this causes xmon to be entered, it is undesirable for the > primary (first) CPU into xmon to trigger an NMI IPI to others, > because

Re: [PATCH] powerpc/64s: use ibm,tlbiel-congruence-classes-(hash|radix) dt property

On Mon, 24 Apr 2017 10:13:23 +1000 Benjamin Herrenschmidt wrote: > On Sun, 2017-04-23 at 19:57 +1000, Nicholas Piggin wrote: > > On Sun, 23 Apr 2017 10:39:11 +1000 > > Benjamin Herrenschmidt wrote: > > > > > On Sun, 2017-04-23 at 09:14

Re: [1/1] powerpc/traps : Updated MC for E6500 L1D cache err

On Thu, Apr 27, 2017 at 12:59:40PM -0500, Matt Weber wrote: > This patch updates the machine check handler of Linux kernel to > handle the e6500 architecture case. In e6500 core, L1 Data Cache Write > Shadow Mode (DCWS) register is not implemented but L1 data cache always > runs in write shadow

Re: Freescale mpc8315 IRQ0 setup

On Mon, Apr 10, 2017 at 04:53:18PM +0200, Juergen Schindele wrote: > Dear mailing list, > i found out on our platform with freescale mpc8315 SOC that in > linux kernel code the setup of IRQ0 which we use is not correct. > One should be able to use falling EDGE interrupt capabilities like on >

Re: powerpc/8xx: Adding support of IRQ in MPC8xx GPIO

On Thu, Mar 09, 2017 at 10:42:04AM +0100, Christophe Leroy wrote: > This patch allows the use of IRQ to notify the change of GPIO status > on MPC8xx CPM IO ports. This then allows to associate IRQs to GPIOs > in the Device Tree. > > Ex: > CPM1_PIO_C: gpio-controller@960 { >