On Tue, Feb 27, 2018 at 8:33 AM, Christophe LEROY
wrote:
>
>
> Le 27/02/2018 à 08:25, Mathieu Malaterre a écrit :
>>
>> On Mon, Feb 26, 2018 at 3:45 PM, Andy Shevchenko
>> wrote:
>>>
>>> On Mon, Feb 26, 2018 at 4:44 PM, Andy Shevchenko
>>> wrote:
On Sun, Feb 25, 2018 at 7:22 PM, Mathie
Le 27/02/2018 à 08:25, Mathieu Malaterre a écrit :
On Mon, Feb 26, 2018 at 3:45 PM, Andy Shevchenko
wrote:
On Mon, Feb 26, 2018 at 4:44 PM, Andy Shevchenko
wrote:
On Sun, Feb 25, 2018 at 7:22 PM, Mathieu Malaterre wrote:
static void __init check_cpu_feature_properties(unsigned long no
Christophe Leroy writes:
> The slice_mask cache was a basic conversion which copied the slice
> mask into caller's structures, because that's how the original code
> worked. In most cases the pointer can be used directly instead, saving
> a copy and an on-stack structure.
>
> This also converts t
On Mon, Feb 26, 2018 at 3:45 PM, Andy Shevchenko
wrote:
> On Mon, Feb 26, 2018 at 4:44 PM, Andy Shevchenko
> wrote:
>> On Sun, Feb 25, 2018 at 7:22 PM, Mathieu Malaterre wrote:
>
>>> static void __init check_cpu_feature_properties(unsigned long node)
>>> {
>>> - unsigned long i;
>>>
Christophe Leroy writes:
+ if ((start + len) > SLICE_LOW_TOP) {
> + unsigned long start_index = GET_HIGH_SLICE_INDEX(start);
> + unsigned long align_end = ALIGN(end, (1UL << SLICE_HIGH_SHIFT));
> + unsigned long count = GET_HIGH_SLICE_INDEX(align_end) -
>
Le 27/02/2018 à 08:02, Aneesh Kumar K.V a écrit :
Hi,
Do you have an updated series for this with your latest PPC32 slice
post?
No, but I can make one if it is on any interest.
Christophe
Christophe Leroy writes:
Pass around const pointers to struct slice_mask where possible, rather
Murilo Opsfelder Araujo writes:
> On 02/26/2018 11:08 AM, Aneesh Kumar K.V wrote:
>> ---
>> arch/powerpc/include/asm/book3s/64/hash-64k.h | 2 +-
>> arch/powerpc/include/asm/processor.h | 9 -
>> arch/powerpc/mm/init_64.c | 6 --
>> arch/powerpc/mm/pgtabl
Nicholas Piggin writes:
> I had a series which goes significantly further with stack reduction. What
> do you think about just going with that?
I am yet to review that. What I did here is minimum that is required to
get 4PB series compiled.
>
> I wonder if we should switch to dynamically alloc
Nicholas Piggin writes:
> On 27 Feb. 2018 00:34, "Aneesh Kumar K.V"
> wrote:
>
> futex_detect_cmpxchg() does a cmpxchg_futex_value_locked on a NULL user
> addr to
> runtime detect whether architecture implements atomic cmpxchg for futex.
> POWER
> do implement the feature and hence we can enable
On 26-02-18, 22:53, Michael Ellerman wrote:
> Viresh Kumar writes:
> > Subject: Re: [PATCH 15/27] cpufreq: powerenv: Don't validate the frequency
> > table twice
>^
> powernv
>
> > The cpufreq core is already valid
> @aneesh can you please look at this? @mpe can we pick this up if there
> are no objections?
@mpe any objections to picking this up for this release? Or do you want to wait
for the next one? (there are likely more bugfixes coming for ATS support).
- Alistair
> Balbir Singh
>
On Mon, 2018-02-26 at 17:06 +0530, Vaibhav Jain wrote:
> Presently sysrq key for xmon('x') is registered during kernel init
> irrespective of the value of kernel param 'xmon'. Thus xmon is enabled
> even if 'xmon=off' is passed on the kernel command line. However this
> doesn't enable the kernel de
Hi All,
Could you please add Olof's patch?
---
arch/powerpc/platforms/pasemi/pci.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/powerpc/platforms/pasemi/pci.c
b/arch/powerpc/platforms/pasemi/pci.c
index 5ff6108..ea54ed2 100644
--- a/arch/powerpc/platforms/pasemi/pci.c
+++ b/arch
I had a series which goes significantly further with stack reduction. What
do you think about just going with that?
I wonder if we should switch to dynamically allocating the slice stuff on
ppc64
On 27 Feb. 2018 00:28, "Aneesh Kumar K.V"
wrote:
> This patch kill potential_mask and compat_mask v
On 27 Feb. 2018 00:34, "Aneesh Kumar K.V"
wrote:
futex_detect_cmpxchg() does a cmpxchg_futex_value_locked on a NULL user
addr to
runtime detect whether architecture implements atomic cmpxchg for futex.
POWER
do implement the feature and hence we can enable the config instead of
depending
on runti
This commit enables the OCXL operations for the OCXL devices.
Signed-off-by: Uma Krishnan
Acked-by: Matthew R. Ochs
---
drivers/scsi/cxlflash/main.c | 9 +++--
drivers/scsi/cxlflash/main.h | 1 +
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/scsi/cxlflash/main.c b/d
The cxlflash core driver resets the AFU when the master contexts are
created in the initialization or recovery paths. Today, the OCXL
provider service to perform this operation is pending implementation.
To avoid a crash due to a missing fop, log an error once and return
success to continue with ex
While enabling a context on the link, a predefined callback can be
registered with the OCXL provider services to be notified on translation
errors. These errors can in turn be passed back to the user on a read
operation.
Signed-off-by: Uma Krishnan
Acked-by: Matthew R. Ochs
---
drivers/scsi/cxl
In order to protect the OCXL hardware contexts from getting clobbered,
a simple state machine is added to indicate when a context is in open,
close or start state. The expected states are validated throughout the
code to prevent illegal operations on a context. A mutex is added to
protect writes to
The SISLite specification has been updated to define new synchronous
interrupt status bits. These bits are set by the AFU when a given PASID or
EA is bad and a synchronous interrupt is triggered.
The SISLite header file is updated to support these new bits. Note that
there are also some formatting
Similar to user contexts, master contexts also require that the per-context
LISN registers be programmed for certain AFUs. The mapped trigger page is
obtained from underlying transport and registered with AFU for each master
context.
Signed-off-by: Uma Krishnan
Acked-by: Matthew R. Ochs
---
dri
The SISLite specification has been updated for OCXL to support
communicating data to generate AFU interrupts to the AFU. This includes
a new capability bit that is advertised for OCXL AFUs and new registers
to hold the object handle and translation PASID of each interrupt. For
Power, the object han
OCXL requires that AFUs use an opaque object handle to represent
an AFU interrupt. The specification does not provide a common means
to communicate the object handle to the AFU - each AFU must define
this within the AFU specification. To support this model, the object
handle must be passed back to
The cxlflash core fop API requires a way to invoke the fault and release
handlers of underlying transports using their native file-based APIs. This
provides the core with the ability to insert selectively itself into the
processing stream of these operations for cleanup. Implement these two
fops to
The cxlflash userspace API requires that users be able to mmap and release
the adapter context. Support mapping by implementing the AFU mmap fop to
map the context MMIO space and install the corresponding page table entry
upon page fault. Similarly, implement the AFU release fop to terminate and
cl
The cxlflash userspace API requires that users be able to read the adapter
context for any pending events or interrupts from the AFU. Support reading
various events by implementing the AFU read fop to copy out event data.
Signed-off-by: Uma Krishnan
Acked-by: Matthew R. Ochs
---
drivers/scsi/cx
The cxlflash userspace API requires that users be able to poll the adapter
context for any pending events or interrupts from the AFU. Support polling
on various events by implementing the AFU poll fop using a waitqueue.
Signed-off-by: Uma Krishnan
Acked-by: Matthew R. Ochs
---
drivers/scsi/cxlf
User contexts request interrupts and are started using the "start work"
interface. Populate the start_work() fop to allocate and map interrupts
before starting the user context. As part of starting the context, update
the user process identification logic to properly derive the data required
by the
Add support to map and unmap the irq space and manage irq registrations
with the kernel for each allocated AFU interrupt. Also support mapping
the physical trigger page to obtain an effective address that will be
provided to the cxlflash core in a future commit.
Signed-off-by: Uma Krishnan
Acked-
Add support to allocate and free AFU interrupts using the OCXL provider
services. The trigger page returned upon successful allocation will be
mapped and exposed to the cxlflash core in a future commit.
Signed-off-by: Uma Krishnan
Acked-by: Matthew R. Ochs
---
drivers/scsi/cxlflash/ocxl_hw.c |
As part of the context lifecycle, the associated process element within
the Shared Process Area (SPA) of the link must be updated. Each process
is defined by various parameters (pid, tid, PASID mm) that are stored in
the SPA upon starting a context and invalidated when a context is stopped.
Use th
The first function of the link needs to configure the transaction layer
between the host and device. This is accomplished by a call to the OCXL
provider services.
Signed-off-by: Uma Krishnan
Acked-by: Matthew R. Ochs
---
drivers/scsi/cxlflash/ocxl_hw.c | 10 ++
1 file changed, 10 insert
After reading and modifying the function configuration, setup the OCXL
link using the OCXL provider services. The link is released when the
adapter is unconfigured.
Signed-off-by: Uma Krishnan
Acked-by: Matthew R. Ochs
---
drivers/scsi/cxlflash/ocxl_hw.c | 25 ++---
drivers/
Use the PCI VPD services to support reading the VPD data of the
underlying adapter.
Signed-off-by: Uma Krishnan
Acked-by: Matthew R. Ochs
---
drivers/scsi/cxlflash/ocxl_hw.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/scsi/cxlflash/ocxl_hw.c b/drivers/scsi/cxlfl
The AFU should be enabled following a successful configuration and
disabled near the end of the cleanup path.
Signed-off-by: Uma Krishnan
Acked-by: Matthew R. Ochs
---
drivers/scsi/cxlflash/ocxl_hw.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/scsi/cxlflash/ocxl_hw.c b/
Once the context is started, the assigned MMIO space can be mapped
and unmapped. Provide means to map and unmap the context MMIO space.
Signed-off-by: Uma Krishnan
Acked-by: Matthew R. Ochs
---
drivers/scsi/cxlflash/ocxl_hw.c | 24
1 file changed, 24 insertions(+)
diff
Once the adapter context is created, it needs to be started by assigning
the MMIO space for the context and by enabling the process element in the
link. This commit adds the skeleton for starting the context and assigns
the context specific MMIO space. Master contexts have access to the global
MMIO
When the AFU is configured, the global and per process MMIO regions
are presented by the configuration space. Save these regions and
map the global MMIO region that is used to access all of the control
and provisioning data in the AFU.
Signed-off-by: Uma Krishnan
Acked-by: Matthew R. Ochs
---
d
On a PERST, the AFU image can be reloaded or left intact. Provide means to
set this image reload policy.
Signed-off-by: Uma Krishnan
Acked-by: Matthew R. Ochs
---
drivers/scsi/cxlflash/ocxl_hw.c | 13 +
drivers/scsi/cxlflash/ocxl_hw.h | 1 +
2 files changed, 14 insertions(+)
diff
Provide means to obtain the process element of an adapter context as well
as locate an adapter context by file.
Signed-off-by: Uma Krishnan
Acked-by: Matthew R. Ochs
---
drivers/scsi/cxlflash/ocxl_hw.c | 26 ++
1 file changed, 26 insertions(+)
diff --git a/drivers/scsi/
Allocate a file descriptor for an adapter context when requested. In order
to allocate inodes for the file descriptors, a pseudo filesystem is created
and used.
Signed-off-by: Uma Krishnan
Acked-by: Matthew R. Ochs
---
drivers/scsi/cxlflash/ocxl_hw.c | 200 ++
A range of PASIDs are used as identifiers for the adapter contexts. These
contexts may be destroyed and created randomly. Use an IDR to keep track
of contexts that are in use and assign a unique identifier to new ones.
Signed-off-by: Uma Krishnan
Acked-by: Matthew R. Ochs
---
drivers/scsi/cxlfl
Add support to create and release the adapter contexts for OCXL and
provide means to specify certain contexts as a master.
The existing cxlflash core has a design requirement that each host will
have a single host context available by default. To satisfy this
requirement, one host adapter context
Per the OCXL specification, the maximum PASID supported by the AFU is
indicated by a field within the configuration space. Similar to acTags,
implementations can choose to use any sub-range of PASID within their
assigned range. For cxlflash, the entire range is used.
Signed-off-by: Uma Krishnan
A
The OCXL specification supports distributing acTags amongst different
AFUs and functions on the link. As cxlflash devices are expected to only
support a single AFU and function, the entire range that was assigned to
the function is also assigned to the AFU.
Signed-off-by: Uma Krishnan
Acked-by: M
The host AFU configuration is read on the initialization path to identify
the features and configuration of the AFU. This data is cached for use in
later configuration steps.
Signed-off-by: Uma Krishnan
Acked-by: Matthew R. Ochs
---
drivers/scsi/cxlflash/ocxl_hw.c | 34 +
The OCXL specification supports distributing acTags amongst different
AFUs and functions on the link. The platform-specific acTag range for the
link is obtained using the OCXL provider services and then assigned to the
host function based on implementation. For cxlflash devices only a single
functi
Per the OCXL specification, the underlying host can have multiple AFUs
per function with each function supporting its own configuration. The host
function configuration is read on the initialization path to evaluate the
number of functions present and identify the features and configuration of
the
When an adapter is initialized, transport specific configuration and MMIO
mapping details need to be saved. For CXL, this data is managed by the
underlying kernel module. To maintain a separation between the cxlflash
core and underlying transports, introduce a new structure to store data
specific t
Add initial infrastructure to support a new cxlflash transport, OCXL.
Claim a dependency on OCXL and add a new file, ocxl_hw.c, which will host
the backend routines that are specific to OCXL.
Signed-off-by: Uma Krishnan
Acked-by: Matthew R. Ochs
---
drivers/scsi/cxlflash/Kconfig | 2 +-
dri
Checkpatch throws a warning when the argument identifier names are not
included in the function definitions.
To avoid these warnings, argument identifiers are added in the existing
function definitions.
Signed-off-by: Uma Krishnan
Acked-by: Matthew R. Ochs
---
drivers/scsi/cxlflash/backend.h |
From: "Matthew R. Ochs"
The SISLite specification originally defined the context control
register with a single field of bits to represent the LISN and
also stipulated that the register reset value be 0. The cxlflash
driver took advantage of this when programming the LISN for the
master contexts
The number of interrupts requested for user contexts are stored in the
context specific structures and utilized to manage the interrupts. For the
master contexts, this number is only used once and therefore not saved.
To prepare for future commits where the number of interrupts will be
required in
This patch series adds OCXL support to the cxlflash driver. With this
support, new devices using the OCXL transport will be supported by the
cxlflash driver along with the existing CXL devices. An effort is made
to keep this transport specific function independent of the existing
core driver that c
On Mon, Feb 26, 2018 at 09:00:09PM +0100, christophe leroy wrote:
> Le 26/02/2018 à 18:50, Mathieu Malaterre a écrit :
> >On Mon, Feb 26, 2018 at 8:44 AM, Mathieu Malaterre
> >wrote:
> >>On Mon, Feb 26, 2018 at 7:50 AM, Christophe LEROY
> >> wrote:
> >>>Note that I already try to submit a fix for
On 02/21/2018 03:52 PM, Ram Pai wrote:
> Currently the architecture specific code is expected to
> display the protection keys in smap for a given vma.
> This can lead to redundant code and possibly to divergent
> formats in which the key gets displayed.
>
> This patch changes the imple
On 02/21/2018 03:52 PM, Ram Pai wrote:
> diff --git a/include/linux/mm.h b/include/linux/mm.h
> index ad207ad..d534f46 100644
> --- a/include/linux/mm.h
> +++ b/include/linux/mm.h
> @@ -231,9 +231,10 @@ extern int overcommit_kbytes_handler(struct ctl_table *,
> int, void __user *,
> #ifdef CONFIG
On 02/21/2018 03:52 PM, Ram Pai wrote:
> VM_PKEY_BITx are defined only if CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
> is enabled. Powerpc also needs these bits. Hence lets define the
> VM_PKEY_BITx bits for any architecture that enables
> CONFIG_ARCH_HAS_PKEYS.
Your fixed version looks fine to me.
postmigration/memory: Now apply changes to the associativity of memory
blocks described by the 'ibm,dynamic-memory-v2' property regarding
the topology of LPARS in Post Migration events.
* Extend the previous work done for the 'ibm,associativity-lookup-array'
to apply to either property 'ibm,dyna
postmigration/memory: In an LPAR migration scenario, the property
"ibm,associativity-lookup-arrays" may change. In the event that a
row of the array differs, locate all assigned memory blocks with that
'aa_index' and 're-add' them to the system memory block data structures.
In the process of the '
hotplug/mobility: Recognize more changes to the associativity of
memory blocks described by the 'ibm,dynamic-memory' and 'cpu'
properties when processing the topology of LPARS in Post Migration
events. Previous efforts only recognized whether a memory block's
assignment had changed in the property
The migration of LPARs across Power systems affects many attributes
including that of the associativity of memory blocks and CPUs. The
patches in this set execute when a system is coming up fresh upon a
migration target. They are intended to,
* Recognize changes to the associativity of memory an
Hi Laurent,
This series doesn't build for me[*] when CONFIG_TRANSPARENT_HUGEPAGE is unset.
The problem seems to be that the BUILD_BUG() version of pmd_same is called in
pte_map_lock:
On 02/16/2018 10:25 AM, Laurent Dufour wrote:
+static bool pte_map_lock(struct vm_fault *vmf)
+{
...snip...
Le 26/02/2018 à 18:50, Mathieu Malaterre a écrit :
On Mon, Feb 26, 2018 at 8:44 AM, Mathieu Malaterre wrote:
On Mon, Feb 26, 2018 at 7:50 AM, Christophe LEROY
wrote:
Le 26/02/2018 à 07:34, Christophe LEROY a écrit :
Le 25/02/2018 à 18:22, Mathieu Malaterre a écrit :
Rewrite check si
On 02/26/2018 11:08 AM, Aneesh Kumar K.V wrote:
> ---
> arch/powerpc/include/asm/book3s/64/hash-64k.h | 2 +-
> arch/powerpc/include/asm/processor.h | 9 -
> arch/powerpc/mm/init_64.c | 6 --
> arch/powerpc/mm/pgtable_64.c | 5 -
> 4 fi
On Mon, Feb 26, 2018 at 8:44 AM, Mathieu Malaterre wrote:
> On Mon, Feb 26, 2018 at 7:50 AM, Christophe LEROY
> wrote:
>>
>>
>> Le 26/02/2018 à 07:34, Christophe LEROY a écrit :
>>>
>>>
>>>
>>> Le 25/02/2018 à 18:22, Mathieu Malaterre a écrit :
Rewrite check size - 1 <= Y as size < Y si
req_ctx->hw_context is mainly used only by the HW. So it is not needed
to sync the HW and the CPU each time hw_context in DMA mapped.
This patch modifies the DMA mapping in order to limit synchronisation
to necessary situations.
Signed-off-by: Christophe Leroy
---
drivers/crypto/talitos.c | 85 +
Commit 49f9783b0cea ("crypto: talitos - do hw_context DMA mapping
outside the requests") introduced a persistent dma mapping of
req_ctx->hw_context
Commit 37b5e8897eb5 ("crypto: talitos - chain in buffered data for ahash
on SEC1") introduced a persistent dma mapping of req_ctx->buf
As there is no
On Mon, Feb 26, 2018 at 4:44 PM, Andy Shevchenko
wrote:
> On Sun, Feb 25, 2018 at 7:22 PM, Mathieu Malaterre wrote:
>> static void __init check_cpu_feature_properties(unsigned long node)
>> {
>> - unsigned long i;
>> struct feature_property *fp = feature_properties;
>> co
On Sun, Feb 25, 2018 at 7:22 PM, Mathieu Malaterre wrote:
> When neither CONFIG_ALTIVEC, nor CONFIG_VSX or CONFIG_PPC64 is defined, the
> array feature_properties is defined as an empty array, which in turn
> triggers the following warning (treated as error on W=1):
>
> CC arch/powerpc/kern
On Thu, Feb 22, 2018 at 04:20:10PM -0600, Uma Krishnan wrote:
> This patch series adds OpenCXL support to the cxlflash driver. With
> this support, new devices using the OpenCXL transport will be supported
> by the cxlflash driver along with the existing CXL devices. An effort is
> made to keep thi
On 02/26/2018 07:38 PM, Aneesh Kumar K.V wrote:
This patch series extended the max virtual address space value from 512TB
to 4PB with 64K page size. We do that by allocating one vsid context for
each 512TB range. More details of that is explained in patch 3.
Aneesh Kumar K.V (4):
powerpc/m
futex_detect_cmpxchg() does a cmpxchg_futex_value_locked on a NULL user addr to
runtime detect whether architecture implements atomic cmpxchg for futex. POWER
do implement the feature and hence we can enable the config instead of depending
on runtime detection.
We could possible enable this on eve
---
arch/powerpc/include/asm/book3s/64/hash-64k.h | 2 +-
arch/powerpc/include/asm/processor.h | 9 -
arch/powerpc/mm/init_64.c | 6 --
arch/powerpc/mm/pgtable_64.c | 5 -
4 files changed, 9 insertions(+), 13 deletions(-)
diff --git a/
For address above 512TB we allocate additonal mmu context. To make it all
easy address above 512TB is handled with IR/DR=1 and with stack frame setup.
We do the additonal context allocation in SLB miss handler. If the context is
not allocated, we enable interrupts and allocate the context and retr
This patch kill potential_mask and compat_mask variable and instead use tmp_mask
so that we can reduce the stack usage. This is required so that we can increase
the high_slices bitmap to a larger value.
The patch does result in extra computation in final stage, where it ends up
recomputing the com
We will make code changes in the next patch. To make the review easier split
the documentation update in to a seperate patch.
Signed-off-by: Aneesh Kumar K.V
---
arch/powerpc/mm/slice.c | 27 +++
1 file changed, 19 insertions(+), 8 deletions(-)
diff --git a/arch/powerpc/
This patch series extended the max virtual address space value from 512TB
to 4PB with 64K page size. We do that by allocating one vsid context for
each 512TB range. More details of that is explained in patch 3.
Aneesh Kumar K.V (4):
powerpc/mm/slice: Update documentation in the file.
powerpc/
linux/processor.h has exactly same defination for spin_until_cond.
Drop the redundant defination in asm/processor.h
Cc: Nicholas Piggin
Cc: Michael Ellerman
Signed-off-by: Sudeep Holla
---
arch/powerpc/include/asm/processor.h | 11 ---
1 file changed, 11 deletions(-)
Hi,
(Resending as
This implementation uses spin_until_cond in wd_smp_lock including
neither linux/processor.h nor asm/processor.h
This patch includes linux/processor.h here for spin_until_cond usage.
Cc: Nicholas Piggin
Cc: Michael Ellerman
Signed-off-by: Sudeep Holla
---
arch/powerpc/kernel/watchdog.c | 1 +
Viresh Kumar writes:
> Subject: Re: [PATCH 15/27] cpufreq: powerenv: Don't validate the frequency
> table twice
^
powernv
> The cpufreq core is already validating the CPU frequency table after
> calling the ->init()
Thanks for the feedback Mpe,
I have sent-out a new patch incorporating your review comments at
http://patchwork.ozlabs.org/patch/877792/
--
Vaibhav Jain
Linux Technology Center, IBM India Pvt. Ltd.
Presently sysrq key for xmon('x') is registered during kernel init
irrespective of the value of kernel param 'xmon'. Thus xmon is enabled
even if 'xmon=off' is passed on the kernel command line. However this
doesn't enable the kernel debugger hooks needed for instruction or data
breakpoints. Thus
On 26.02.2018 04:05, Linus Torvalds wrote:
> We're on the normal schedule for 4.16 and everything still looks very regular.
Hi! Find below my second regression report for Linux 4.16. It lists 8
regressions I'm currently aware of.
To anyone reading this: Are you aware of any other regressions that
On Mon, Feb 12, 2018 at 11:33 AM, Shilpasri G Bhat
wrote:
> Hi,
>
> On 02/12/2018 03:59 PM, Viresh Kumar wrote:
>> On 12-02-18, 15:51, Shilpasri G Bhat wrote:
>>> This patch fixes the below Coverity warning:
>>>
>>> *** CID 182816: Memory - illegal accesses (NEGATIVE_RETURNS)
>>> /drivers/cpufre
On Sun, Jan 28, 2018 at 12:51 AM, Finn Thain wrote:
> The PMU watchdog will power down the system if the kernel is slow
> to start up, e.g. due to unpacking a large initrd. The powerpc
> version of this driver (via-pmu.c) has a solution for the same
> problem. It uses this call sequence:
>
> setup
On Mon, Feb 26, 2018 at 07:32:03AM +0100, Christophe LEROY wrote:
> Le 25/02/2018 à 18:22, Mathieu Malaterre a écrit :
> >-#define pfn_valid(pfn) ((pfn) >= ARCH_PFN_OFFSET && (pfn) <
> >max_mapnr)
> >+#define pfn_valid(pfn) \
> >+(((pfn) - ARCH_PFN_OFFSET) < (max_mapnr - A
On Mon, Feb 26, 2018 at 01:13:17PM +1100, Michael Ellerman wrote:
> The backport of commit aa8a5e0062ac ("powerpc/64s: Add support for RFI
> flush of L1-D cache"), incorrectly placed the new RFI flush code
> inside an existing #ifdef CONFIG_HARDLOCKUP_DETECTOR block.
>
> This has the obvious effec
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